Peripheral memory map for MK70F12. More...

#include <stdint.h>

Data Structures
struct	ADC_MemMap

struct	AIPS_MemMap

struct	AXBS_MemMap

struct	CAN_MemMap

struct	CAU_MemMap

struct	CMP_MemMap

struct	CMT_MemMap

struct	CRC_MemMap

struct	CoreDebug_MemMap

struct	DAC_MemMap

struct	DDR_MemMap

struct	DMA_MemMap

struct	DMAMUX_MemMap

struct	DWT_MemMap

struct	ENET_MemMap

struct	ETB_MemMap

struct	ETF_MemMap

struct	ETM_MemMap

struct	EWM_MemMap

struct	FB_MemMap

struct	FMC_MemMap

struct	FPB_MemMap

struct	FTFE_MemMap

struct	FTM_MemMap

struct	GPIO_MemMap

struct	I2C_MemMap

struct	I2S_MemMap

struct	ITM_MemMap

struct	LCDC_MemMap

struct	LLWU_MemMap

struct	LMEM_MemMap

struct	LPTMR_MemMap

struct	MCG_MemMap

struct	MCM_MemMap

struct	MPU_MemMap

struct	NFC_MemMap

struct	NV_MemMap

struct	NVIC_MemMap

struct	OSC_MemMap

struct	PDB_MemMap

struct	PIT_MemMap

struct	PMC_MemMap

struct	PORT_MemMap

struct	RCM_MemMap

struct	RFSYS_MemMap

struct	RFVBAT_MemMap

struct	RNG_MemMap

struct	RTC_MemMap

struct	SCB_MemMap

struct	SDHC_MemMap

struct	SIM_MemMap

struct	SMC_MemMap

struct	SPI_MemMap

struct	SysTick_MemMap

struct	TPIU_MemMap

struct	TSI_MemMap

struct	UART_MemMap

struct	USB_MemMap

struct	USBDCD_MemMap

struct	USBHS_MemMap

struct	VREF_MemMap

struct	WDOG_MemMap

Macros
#define	MCU_MK70F12

#define	MCU_MK70F15

#define	MCU_ACTIVE

#define	MCU_MEM_MAP_VERSION 0x0100u

#define	MCU_MEM_MAP_VERSION_MINOR 0x000Cu

#define	BITBAND_REGADDR(Reg, Bit) (0x42000000u + (32u((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u((uint32_t)(Bit))))
	Macro to calculate address of an aliased word in the peripheral bitband area for a peripheral register and bit (bit band region 0x40000000 to 0x400FFFFF). More...

#define	BITBAND_REG32(Reg, Bit) (((uint32_t volatile)(BITBAND_REGADDR(Reg,Bit))))
	Macro to access a single bit of a peripheral register (bit band region 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can be used for peripherals with 32bit access allowed. More...

#define	BITBAND_REG(Reg, Bit) (BITBAND_REG32(Reg,Bit))

#define	BITBAND_REG16(Reg, Bit) (((uint16_t volatile)(BITBAND_REGADDR(Reg,Bit))))
	Macro to access a single bit of a peripheral register (bit band region 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can be used for peripherals with 16bit access allowed. More...

#define	BITBAND_REG8(Reg, Bit) (((uint8_t volatile)(BITBAND_REGADDR(Reg,Bit))))
	Macro to access a single bit of a peripheral register (bit band region 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can be used for peripherals with 8bit access allowed. More...

#define	ADC_SC1_REG(base, index) ((base)->SC1[index])

#define	ADC_CFG1_REG(base) ((base)->CFG1)

#define	ADC_CFG2_REG(base) ((base)->CFG2)

#define	ADC_R_REG(base, index) ((base)->R[index])

#define	ADC_CV1_REG(base) ((base)->CV1)

#define	ADC_CV2_REG(base) ((base)->CV2)

#define	ADC_SC2_REG(base) ((base)->SC2)

#define	ADC_SC3_REG(base) ((base)->SC3)

#define	ADC_OFS_REG(base) ((base)->OFS)

#define	ADC_PG_REG(base) ((base)->PG)

#define	ADC_MG_REG(base) ((base)->MG)

#define	ADC_CLPD_REG(base) ((base)->CLPD)

#define	ADC_CLPS_REG(base) ((base)->CLPS)

#define	ADC_CLP4_REG(base) ((base)->CLP4)

#define	ADC_CLP3_REG(base) ((base)->CLP3)

#define	ADC_CLP2_REG(base) ((base)->CLP2)

#define	ADC_CLP1_REG(base) ((base)->CLP1)

#define	ADC_CLP0_REG(base) ((base)->CLP0)

#define	ADC_PGA_REG(base) ((base)->PGA)

#define	ADC_CLMD_REG(base) ((base)->CLMD)

#define	ADC_CLMS_REG(base) ((base)->CLMS)

#define	ADC_CLM4_REG(base) ((base)->CLM4)

#define	ADC_CLM3_REG(base) ((base)->CLM3)

#define	ADC_CLM2_REG(base) ((base)->CLM2)

#define	ADC_CLM1_REG(base) ((base)->CLM1)

#define	ADC_CLM0_REG(base) ((base)->CLM0)

#define	ADC_SC1_ADCH_MASK 0x1Fu

#define	ADC_SC1_ADCH_SHIFT 0

#define	ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)

#define	ADC_SC1_DIFF_MASK 0x20u

#define	ADC_SC1_DIFF_SHIFT 5

#define	ADC_SC1_AIEN_MASK 0x40u

#define	ADC_SC1_AIEN_SHIFT 6

#define	ADC_SC1_COCO_MASK 0x80u

#define	ADC_SC1_COCO_SHIFT 7

#define	ADC_CFG1_ADICLK_MASK 0x3u

#define	ADC_CFG1_ADICLK_SHIFT 0

#define	ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)

#define	ADC_CFG1_MODE_MASK 0xCu

#define	ADC_CFG1_MODE_SHIFT 2

#define	ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)

#define	ADC_CFG1_ADLSMP_MASK 0x10u

#define	ADC_CFG1_ADLSMP_SHIFT 4

#define	ADC_CFG1_ADIV_MASK 0x60u

#define	ADC_CFG1_ADIV_SHIFT 5

#define	ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)

#define	ADC_CFG1_ADLPC_MASK 0x80u

#define	ADC_CFG1_ADLPC_SHIFT 7

#define	ADC_CFG2_ADLSTS_MASK 0x3u

#define	ADC_CFG2_ADLSTS_SHIFT 0

#define	ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)

#define	ADC_CFG2_ADHSC_MASK 0x4u

#define	ADC_CFG2_ADHSC_SHIFT 2

#define	ADC_CFG2_ADACKEN_MASK 0x8u

#define	ADC_CFG2_ADACKEN_SHIFT 3

#define	ADC_CFG2_MUXSEL_MASK 0x10u

#define	ADC_CFG2_MUXSEL_SHIFT 4

#define	ADC_R_D_MASK 0xFFFFu

#define	ADC_R_D_SHIFT 0

#define	ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)

#define	ADC_CV1_CV_MASK 0xFFFFu

#define	ADC_CV1_CV_SHIFT 0

#define	ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)

#define	ADC_CV2_CV_MASK 0xFFFFu

#define	ADC_CV2_CV_SHIFT 0

#define	ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)

#define	ADC_SC2_REFSEL_MASK 0x3u

#define	ADC_SC2_REFSEL_SHIFT 0

#define	ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)

#define	ADC_SC2_DMAEN_MASK 0x4u

#define	ADC_SC2_DMAEN_SHIFT 2

#define	ADC_SC2_ACREN_MASK 0x8u

#define	ADC_SC2_ACREN_SHIFT 3

#define	ADC_SC2_ACFGT_MASK 0x10u

#define	ADC_SC2_ACFGT_SHIFT 4

#define	ADC_SC2_ACFE_MASK 0x20u

#define	ADC_SC2_ACFE_SHIFT 5

#define	ADC_SC2_ADTRG_MASK 0x40u

#define	ADC_SC2_ADTRG_SHIFT 6

#define	ADC_SC2_ADACT_MASK 0x80u

#define	ADC_SC2_ADACT_SHIFT 7

#define	ADC_SC3_AVGS_MASK 0x3u

#define	ADC_SC3_AVGS_SHIFT 0

#define	ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)

#define	ADC_SC3_AVGE_MASK 0x4u

#define	ADC_SC3_AVGE_SHIFT 2

#define	ADC_SC3_ADCO_MASK 0x8u

#define	ADC_SC3_ADCO_SHIFT 3

#define	ADC_SC3_CALF_MASK 0x40u

#define	ADC_SC3_CALF_SHIFT 6

#define	ADC_SC3_CAL_MASK 0x80u

#define	ADC_SC3_CAL_SHIFT 7

#define	ADC_OFS_OFS_MASK 0xFFFFu

#define	ADC_OFS_OFS_SHIFT 0

#define	ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)

#define	ADC_PG_PG_MASK 0xFFFFu

#define	ADC_PG_PG_SHIFT 0

#define	ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)

#define	ADC_MG_MG_MASK 0xFFFFu

#define	ADC_MG_MG_SHIFT 0

#define	ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)

#define	ADC_CLPD_CLPD_MASK 0x3Fu

#define	ADC_CLPD_CLPD_SHIFT 0

#define	ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)

#define	ADC_CLPS_CLPS_MASK 0x3Fu

#define	ADC_CLPS_CLPS_SHIFT 0

#define	ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)

#define	ADC_CLP4_CLP4_MASK 0x3FFu

#define	ADC_CLP4_CLP4_SHIFT 0

#define	ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)

#define	ADC_CLP3_CLP3_MASK 0x1FFu

#define	ADC_CLP3_CLP3_SHIFT 0

#define	ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)

#define	ADC_CLP2_CLP2_MASK 0xFFu

#define	ADC_CLP2_CLP2_SHIFT 0

#define	ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)

#define	ADC_CLP1_CLP1_MASK 0x7Fu

#define	ADC_CLP1_CLP1_SHIFT 0

#define	ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)

#define	ADC_CLP0_CLP0_MASK 0x3Fu

#define	ADC_CLP0_CLP0_SHIFT 0

#define	ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)

#define	ADC_PGA_PGAOFSM_MASK 0x4000u

#define	ADC_PGA_PGAOFSM_SHIFT 14

#define	ADC_PGA_PGAG_MASK 0xF0000u

#define	ADC_PGA_PGAG_SHIFT 16

#define	ADC_PGA_PGAG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PGA_PGAG_SHIFT))&ADC_PGA_PGAG_MASK)

#define	ADC_PGA_PGALPb_MASK 0x100000u

#define	ADC_PGA_PGALPb_SHIFT 20

#define	ADC_PGA_PGACHPb_MASK 0x200000u

#define	ADC_PGA_PGACHPb_SHIFT 21

#define	ADC_PGA_PGAEN_MASK 0x800000u

#define	ADC_PGA_PGAEN_SHIFT 23

#define	ADC_CLMD_CLMD_MASK 0x3Fu

#define	ADC_CLMD_CLMD_SHIFT 0

#define	ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)

#define	ADC_CLMS_CLMS_MASK 0x3Fu

#define	ADC_CLMS_CLMS_SHIFT 0

#define	ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)

#define	ADC_CLM4_CLM4_MASK 0x3FFu

#define	ADC_CLM4_CLM4_SHIFT 0

#define	ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)

#define	ADC_CLM3_CLM3_MASK 0x1FFu

#define	ADC_CLM3_CLM3_SHIFT 0

#define	ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)

#define	ADC_CLM2_CLM2_MASK 0xFFu

#define	ADC_CLM2_CLM2_SHIFT 0

#define	ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)

#define	ADC_CLM1_CLM1_MASK 0x7Fu

#define	ADC_CLM1_CLM1_SHIFT 0

#define	ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)

#define	ADC_CLM0_CLM0_MASK 0x3Fu

#define	ADC_CLM0_CLM0_SHIFT 0

#define	ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)

#define	ADC0_BASE_PTR ((ADC_MemMapPtr)0x4003B000u)

#define	ADC1_BASE_PTR ((ADC_MemMapPtr)0x400BB000u)

#define	ADC2_BASE_PTR ((ADC_MemMapPtr)0x4003C000u)

#define	ADC3_BASE_PTR ((ADC_MemMapPtr)0x400BC000u)

#define	ADC_BASE_PTRS { ADC0_BASE_PTR, ADC1_BASE_PTR, ADC2_BASE_PTR, ADC3_BASE_PTR }

#define	ADC0_SC1A ADC_SC1_REG(ADC0_BASE_PTR,0)

#define	ADC0_SC1B ADC_SC1_REG(ADC0_BASE_PTR,1)

#define	ADC0_CFG1 ADC_CFG1_REG(ADC0_BASE_PTR)

#define	ADC0_CFG2 ADC_CFG2_REG(ADC0_BASE_PTR)

#define	ADC0_RA ADC_R_REG(ADC0_BASE_PTR,0)

#define	ADC0_RB ADC_R_REG(ADC0_BASE_PTR,1)

#define	ADC0_CV1 ADC_CV1_REG(ADC0_BASE_PTR)

#define	ADC0_CV2 ADC_CV2_REG(ADC0_BASE_PTR)

#define	ADC0_SC2 ADC_SC2_REG(ADC0_BASE_PTR)

#define	ADC0_SC3 ADC_SC3_REG(ADC0_BASE_PTR)

#define	ADC0_OFS ADC_OFS_REG(ADC0_BASE_PTR)

#define	ADC0_PG ADC_PG_REG(ADC0_BASE_PTR)

#define	ADC0_MG ADC_MG_REG(ADC0_BASE_PTR)

#define	ADC0_CLPD ADC_CLPD_REG(ADC0_BASE_PTR)

#define	ADC0_CLPS ADC_CLPS_REG(ADC0_BASE_PTR)

#define	ADC0_CLP4 ADC_CLP4_REG(ADC0_BASE_PTR)

#define	ADC0_CLP3 ADC_CLP3_REG(ADC0_BASE_PTR)

#define	ADC0_CLP2 ADC_CLP2_REG(ADC0_BASE_PTR)

#define	ADC0_CLP1 ADC_CLP1_REG(ADC0_BASE_PTR)

#define	ADC0_CLP0 ADC_CLP0_REG(ADC0_BASE_PTR)

#define	ADC0_PGA ADC_PGA_REG(ADC0_BASE_PTR)

#define	ADC0_CLMD ADC_CLMD_REG(ADC0_BASE_PTR)

#define	ADC0_CLMS ADC_CLMS_REG(ADC0_BASE_PTR)

#define	ADC0_CLM4 ADC_CLM4_REG(ADC0_BASE_PTR)

#define	ADC0_CLM3 ADC_CLM3_REG(ADC0_BASE_PTR)

#define	ADC0_CLM2 ADC_CLM2_REG(ADC0_BASE_PTR)

#define	ADC0_CLM1 ADC_CLM1_REG(ADC0_BASE_PTR)

#define	ADC0_CLM0 ADC_CLM0_REG(ADC0_BASE_PTR)

#define	ADC1_SC1A ADC_SC1_REG(ADC1_BASE_PTR,0)

#define	ADC1_SC1B ADC_SC1_REG(ADC1_BASE_PTR,1)

#define	ADC1_CFG1 ADC_CFG1_REG(ADC1_BASE_PTR)

#define	ADC1_CFG2 ADC_CFG2_REG(ADC1_BASE_PTR)

#define	ADC1_RA ADC_R_REG(ADC1_BASE_PTR,0)

#define	ADC1_RB ADC_R_REG(ADC1_BASE_PTR,1)

#define	ADC1_CV1 ADC_CV1_REG(ADC1_BASE_PTR)

#define	ADC1_CV2 ADC_CV2_REG(ADC1_BASE_PTR)

#define	ADC1_SC2 ADC_SC2_REG(ADC1_BASE_PTR)

#define	ADC1_SC3 ADC_SC3_REG(ADC1_BASE_PTR)

#define	ADC1_OFS ADC_OFS_REG(ADC1_BASE_PTR)

#define	ADC1_PG ADC_PG_REG(ADC1_BASE_PTR)

#define	ADC1_MG ADC_MG_REG(ADC1_BASE_PTR)

#define	ADC1_CLPD ADC_CLPD_REG(ADC1_BASE_PTR)

#define	ADC1_CLPS ADC_CLPS_REG(ADC1_BASE_PTR)

#define	ADC1_CLP4 ADC_CLP4_REG(ADC1_BASE_PTR)

#define	ADC1_CLP3 ADC_CLP3_REG(ADC1_BASE_PTR)

#define	ADC1_CLP2 ADC_CLP2_REG(ADC1_BASE_PTR)

#define	ADC1_CLP1 ADC_CLP1_REG(ADC1_BASE_PTR)

#define	ADC1_CLP0 ADC_CLP0_REG(ADC1_BASE_PTR)

#define	ADC1_PGA ADC_PGA_REG(ADC1_BASE_PTR)

#define	ADC1_CLMD ADC_CLMD_REG(ADC1_BASE_PTR)

#define	ADC1_CLMS ADC_CLMS_REG(ADC1_BASE_PTR)

#define	ADC1_CLM4 ADC_CLM4_REG(ADC1_BASE_PTR)

#define	ADC1_CLM3 ADC_CLM3_REG(ADC1_BASE_PTR)

#define	ADC1_CLM2 ADC_CLM2_REG(ADC1_BASE_PTR)

#define	ADC1_CLM1 ADC_CLM1_REG(ADC1_BASE_PTR)

#define	ADC1_CLM0 ADC_CLM0_REG(ADC1_BASE_PTR)

#define	ADC2_SC1A ADC_SC1_REG(ADC2_BASE_PTR,0)

#define	ADC2_SC1B ADC_SC1_REG(ADC2_BASE_PTR,1)

#define	ADC2_CFG1 ADC_CFG1_REG(ADC2_BASE_PTR)

#define	ADC2_CFG2 ADC_CFG2_REG(ADC2_BASE_PTR)

#define	ADC2_RA ADC_R_REG(ADC2_BASE_PTR,0)

#define	ADC2_RB ADC_R_REG(ADC2_BASE_PTR,1)

#define	ADC2_CV1 ADC_CV1_REG(ADC2_BASE_PTR)

#define	ADC2_CV2 ADC_CV2_REG(ADC2_BASE_PTR)

#define	ADC2_SC2 ADC_SC2_REG(ADC2_BASE_PTR)

#define	ADC2_SC3 ADC_SC3_REG(ADC2_BASE_PTR)

#define	ADC2_OFS ADC_OFS_REG(ADC2_BASE_PTR)

#define	ADC2_PG ADC_PG_REG(ADC2_BASE_PTR)

#define	ADC2_MG ADC_MG_REG(ADC2_BASE_PTR)

#define	ADC2_CLPD ADC_CLPD_REG(ADC2_BASE_PTR)

#define	ADC2_CLPS ADC_CLPS_REG(ADC2_BASE_PTR)

#define	ADC2_CLP4 ADC_CLP4_REG(ADC2_BASE_PTR)

#define	ADC2_CLP3 ADC_CLP3_REG(ADC2_BASE_PTR)

#define	ADC2_CLP2 ADC_CLP2_REG(ADC2_BASE_PTR)

#define	ADC2_CLP1 ADC_CLP1_REG(ADC2_BASE_PTR)

#define	ADC2_CLP0 ADC_CLP0_REG(ADC2_BASE_PTR)

#define	ADC2_PGA ADC_PGA_REG(ADC2_BASE_PTR)

#define	ADC2_CLMD ADC_CLMD_REG(ADC2_BASE_PTR)

#define	ADC2_CLMS ADC_CLMS_REG(ADC2_BASE_PTR)

#define	ADC2_CLM4 ADC_CLM4_REG(ADC2_BASE_PTR)

#define	ADC2_CLM3 ADC_CLM3_REG(ADC2_BASE_PTR)

#define	ADC2_CLM2 ADC_CLM2_REG(ADC2_BASE_PTR)

#define	ADC2_CLM1 ADC_CLM1_REG(ADC2_BASE_PTR)

#define	ADC2_CLM0 ADC_CLM0_REG(ADC2_BASE_PTR)

#define	ADC3_SC1A ADC_SC1_REG(ADC3_BASE_PTR,0)

#define	ADC3_SC1B ADC_SC1_REG(ADC3_BASE_PTR,1)

#define	ADC3_CFG1 ADC_CFG1_REG(ADC3_BASE_PTR)

#define	ADC3_CFG2 ADC_CFG2_REG(ADC3_BASE_PTR)

#define	ADC3_RA ADC_R_REG(ADC3_BASE_PTR,0)

#define	ADC3_RB ADC_R_REG(ADC3_BASE_PTR,1)

#define	ADC3_CV1 ADC_CV1_REG(ADC3_BASE_PTR)

#define	ADC3_CV2 ADC_CV2_REG(ADC3_BASE_PTR)

#define	ADC3_SC2 ADC_SC2_REG(ADC3_BASE_PTR)

#define	ADC3_SC3 ADC_SC3_REG(ADC3_BASE_PTR)

#define	ADC3_OFS ADC_OFS_REG(ADC3_BASE_PTR)

#define	ADC3_PG ADC_PG_REG(ADC3_BASE_PTR)

#define	ADC3_MG ADC_MG_REG(ADC3_BASE_PTR)

#define	ADC3_CLPD ADC_CLPD_REG(ADC3_BASE_PTR)

#define	ADC3_CLPS ADC_CLPS_REG(ADC3_BASE_PTR)

#define	ADC3_CLP4 ADC_CLP4_REG(ADC3_BASE_PTR)

#define	ADC3_CLP3 ADC_CLP3_REG(ADC3_BASE_PTR)

#define	ADC3_CLP2 ADC_CLP2_REG(ADC3_BASE_PTR)

#define	ADC3_CLP1 ADC_CLP1_REG(ADC3_BASE_PTR)

#define	ADC3_CLP0 ADC_CLP0_REG(ADC3_BASE_PTR)

#define	ADC3_PGA ADC_PGA_REG(ADC3_BASE_PTR)

#define	ADC3_CLMD ADC_CLMD_REG(ADC3_BASE_PTR)

#define	ADC3_CLMS ADC_CLMS_REG(ADC3_BASE_PTR)

#define	ADC3_CLM4 ADC_CLM4_REG(ADC3_BASE_PTR)

#define	ADC3_CLM3 ADC_CLM3_REG(ADC3_BASE_PTR)

#define	ADC3_CLM2 ADC_CLM2_REG(ADC3_BASE_PTR)

#define	ADC3_CLM1 ADC_CLM1_REG(ADC3_BASE_PTR)

#define	ADC3_CLM0 ADC_CLM0_REG(ADC3_BASE_PTR)

#define	ADC0_SC1(index) ADC_SC1_REG(ADC0_BASE_PTR,index)

#define	ADC1_SC1(index) ADC_SC1_REG(ADC1_BASE_PTR,index)

#define	ADC2_SC1(index) ADC_SC1_REG(ADC2_BASE_PTR,index)

#define	ADC3_SC1(index) ADC_SC1_REG(ADC3_BASE_PTR,index)

#define	ADC0_R(index) ADC_R_REG(ADC0_BASE_PTR,index)

#define	ADC1_R(index) ADC_R_REG(ADC1_BASE_PTR,index)

#define	ADC2_R(index) ADC_R_REG(ADC2_BASE_PTR,index)

#define	ADC3_R(index) ADC_R_REG(ADC3_BASE_PTR,index)

#define	AIPS_MPRA_REG(base) ((base)->MPRA)

#define	AIPS_PACRA_REG(base) ((base)->PACRA)

#define	AIPS_PACRB_REG(base) ((base)->PACRB)

#define	AIPS_PACRC_REG(base) ((base)->PACRC)

#define	AIPS_PACRD_REG(base) ((base)->PACRD)

#define	AIPS_PACRE_REG(base) ((base)->PACRE)

#define	AIPS_PACRF_REG(base) ((base)->PACRF)

#define	AIPS_PACRG_REG(base) ((base)->PACRG)

#define	AIPS_PACRH_REG(base) ((base)->PACRH)

#define	AIPS_PACRI_REG(base) ((base)->PACRI)

#define	AIPS_PACRJ_REG(base) ((base)->PACRJ)

#define	AIPS_PACRK_REG(base) ((base)->PACRK)

#define	AIPS_PACRL_REG(base) ((base)->PACRL)

#define	AIPS_PACRM_REG(base) ((base)->PACRM)

#define	AIPS_PACRN_REG(base) ((base)->PACRN)

#define	AIPS_PACRO_REG(base) ((base)->PACRO)

#define	AIPS_PACRP_REG(base) ((base)->PACRP)

#define	AIPS_MPRA_MPL7_MASK 0x1u

#define	AIPS_MPRA_MPL7_SHIFT 0

#define	AIPS_MPRA_MTW7_MASK 0x2u

#define	AIPS_MPRA_MTW7_SHIFT 1

#define	AIPS_MPRA_MTR7_MASK 0x4u

#define	AIPS_MPRA_MTR7_SHIFT 2

#define	AIPS_MPRA_MPL6_MASK 0x10u

#define	AIPS_MPRA_MPL6_SHIFT 4

#define	AIPS_MPRA_MTW6_MASK 0x20u

#define	AIPS_MPRA_MTW6_SHIFT 5

#define	AIPS_MPRA_MTR6_MASK 0x40u

#define	AIPS_MPRA_MTR6_SHIFT 6

#define	AIPS_MPRA_MPL5_MASK 0x100u

#define	AIPS_MPRA_MPL5_SHIFT 8

#define	AIPS_MPRA_MTW5_MASK 0x200u

#define	AIPS_MPRA_MTW5_SHIFT 9

#define	AIPS_MPRA_MTR5_MASK 0x400u

#define	AIPS_MPRA_MTR5_SHIFT 10

#define	AIPS_MPRA_MPL4_MASK 0x1000u

#define	AIPS_MPRA_MPL4_SHIFT 12

#define	AIPS_MPRA_MTW4_MASK 0x2000u

#define	AIPS_MPRA_MTW4_SHIFT 13

#define	AIPS_MPRA_MTR4_MASK 0x4000u

#define	AIPS_MPRA_MTR4_SHIFT 14

#define	AIPS_MPRA_MPL3_MASK 0x10000u

#define	AIPS_MPRA_MPL3_SHIFT 16

#define	AIPS_MPRA_MTW3_MASK 0x20000u

#define	AIPS_MPRA_MTW3_SHIFT 17

#define	AIPS_MPRA_MTR3_MASK 0x40000u

#define	AIPS_MPRA_MTR3_SHIFT 18

#define	AIPS_MPRA_MPL2_MASK 0x100000u

#define	AIPS_MPRA_MPL2_SHIFT 20

#define	AIPS_MPRA_MTW2_MASK 0x200000u

#define	AIPS_MPRA_MTW2_SHIFT 21

#define	AIPS_MPRA_MTR2_MASK 0x400000u

#define	AIPS_MPRA_MTR2_SHIFT 22

#define	AIPS_MPRA_MPL1_MASK 0x1000000u

#define	AIPS_MPRA_MPL1_SHIFT 24

#define	AIPS_MPRA_MTW1_MASK 0x2000000u

#define	AIPS_MPRA_MTW1_SHIFT 25

#define	AIPS_MPRA_MTR1_MASK 0x4000000u

#define	AIPS_MPRA_MTR1_SHIFT 26

#define	AIPS_MPRA_MPL0_MASK 0x10000000u

#define	AIPS_MPRA_MPL0_SHIFT 28

#define	AIPS_MPRA_MTW0_MASK 0x20000000u

#define	AIPS_MPRA_MTW0_SHIFT 29

#define	AIPS_MPRA_MTR0_MASK 0x40000000u

#define	AIPS_MPRA_MTR0_SHIFT 30

#define	AIPS_PACRA_TP7_MASK 0x1u

#define	AIPS_PACRA_TP7_SHIFT 0

#define	AIPS_PACRA_WP7_MASK 0x2u

#define	AIPS_PACRA_WP7_SHIFT 1

#define	AIPS_PACRA_SP7_MASK 0x4u

#define	AIPS_PACRA_SP7_SHIFT 2

#define	AIPS_PACRA_TP6_MASK 0x10u

#define	AIPS_PACRA_TP6_SHIFT 4

#define	AIPS_PACRA_WP6_MASK 0x20u

#define	AIPS_PACRA_WP6_SHIFT 5

#define	AIPS_PACRA_SP6_MASK 0x40u

#define	AIPS_PACRA_SP6_SHIFT 6

#define	AIPS_PACRA_TP5_MASK 0x100u

#define	AIPS_PACRA_TP5_SHIFT 8

#define	AIPS_PACRA_WP5_MASK 0x200u

#define	AIPS_PACRA_WP5_SHIFT 9

#define	AIPS_PACRA_SP5_MASK 0x400u

#define	AIPS_PACRA_SP5_SHIFT 10

#define	AIPS_PACRA_TP4_MASK 0x1000u

#define	AIPS_PACRA_TP4_SHIFT 12

#define	AIPS_PACRA_WP4_MASK 0x2000u

#define	AIPS_PACRA_WP4_SHIFT 13

#define	AIPS_PACRA_SP4_MASK 0x4000u

#define	AIPS_PACRA_SP4_SHIFT 14

#define	AIPS_PACRA_TP3_MASK 0x10000u

#define	AIPS_PACRA_TP3_SHIFT 16

#define	AIPS_PACRA_WP3_MASK 0x20000u

#define	AIPS_PACRA_WP3_SHIFT 17

#define	AIPS_PACRA_SP3_MASK 0x40000u

#define	AIPS_PACRA_SP3_SHIFT 18

#define	AIPS_PACRA_TP2_MASK 0x100000u

#define	AIPS_PACRA_TP2_SHIFT 20

#define	AIPS_PACRA_WP2_MASK 0x200000u

#define	AIPS_PACRA_WP2_SHIFT 21

#define	AIPS_PACRA_SP2_MASK 0x400000u

#define	AIPS_PACRA_SP2_SHIFT 22

#define	AIPS_PACRA_TP1_MASK 0x1000000u

#define	AIPS_PACRA_TP1_SHIFT 24

#define	AIPS_PACRA_WP1_MASK 0x2000000u

#define	AIPS_PACRA_WP1_SHIFT 25

#define	AIPS_PACRA_SP1_MASK 0x4000000u

#define	AIPS_PACRA_SP1_SHIFT 26

#define	AIPS_PACRA_TP0_MASK 0x10000000u

#define	AIPS_PACRA_TP0_SHIFT 28

#define	AIPS_PACRA_WP0_MASK 0x20000000u

#define	AIPS_PACRA_WP0_SHIFT 29

#define	AIPS_PACRA_SP0_MASK 0x40000000u

#define	AIPS_PACRA_SP0_SHIFT 30

#define	AIPS_PACRB_TP7_MASK 0x1u

#define	AIPS_PACRB_TP7_SHIFT 0

#define	AIPS_PACRB_WP7_MASK 0x2u

#define	AIPS_PACRB_WP7_SHIFT 1

#define	AIPS_PACRB_SP7_MASK 0x4u

#define	AIPS_PACRB_SP7_SHIFT 2

#define	AIPS_PACRB_TP6_MASK 0x10u

#define	AIPS_PACRB_TP6_SHIFT 4

#define	AIPS_PACRB_WP6_MASK 0x20u

#define	AIPS_PACRB_WP6_SHIFT 5

#define	AIPS_PACRB_SP6_MASK 0x40u

#define	AIPS_PACRB_SP6_SHIFT 6

#define	AIPS_PACRB_TP5_MASK 0x100u

#define	AIPS_PACRB_TP5_SHIFT 8

#define	AIPS_PACRB_WP5_MASK 0x200u

#define	AIPS_PACRB_WP5_SHIFT 9

#define	AIPS_PACRB_SP5_MASK 0x400u

#define	AIPS_PACRB_SP5_SHIFT 10

#define	AIPS_PACRB_TP4_MASK 0x1000u

#define	AIPS_PACRB_TP4_SHIFT 12

#define	AIPS_PACRB_WP4_MASK 0x2000u

#define	AIPS_PACRB_WP4_SHIFT 13

#define	AIPS_PACRB_SP4_MASK 0x4000u

#define	AIPS_PACRB_SP4_SHIFT 14

#define	AIPS_PACRB_TP3_MASK 0x10000u

#define	AIPS_PACRB_TP3_SHIFT 16

#define	AIPS_PACRB_WP3_MASK 0x20000u

#define	AIPS_PACRB_WP3_SHIFT 17

#define	AIPS_PACRB_SP3_MASK 0x40000u

#define	AIPS_PACRB_SP3_SHIFT 18

#define	AIPS_PACRB_TP2_MASK 0x100000u

#define	AIPS_PACRB_TP2_SHIFT 20

#define	AIPS_PACRB_WP2_MASK 0x200000u

#define	AIPS_PACRB_WP2_SHIFT 21

#define	AIPS_PACRB_SP2_MASK 0x400000u

#define	AIPS_PACRB_SP2_SHIFT 22

#define	AIPS_PACRB_TP1_MASK 0x1000000u

#define	AIPS_PACRB_TP1_SHIFT 24

#define	AIPS_PACRB_WP1_MASK 0x2000000u

#define	AIPS_PACRB_WP1_SHIFT 25

#define	AIPS_PACRB_SP1_MASK 0x4000000u

#define	AIPS_PACRB_SP1_SHIFT 26

#define	AIPS_PACRB_TP0_MASK 0x10000000u

#define	AIPS_PACRB_TP0_SHIFT 28

#define	AIPS_PACRB_WP0_MASK 0x20000000u

#define	AIPS_PACRB_WP0_SHIFT 29

#define	AIPS_PACRB_SP0_MASK 0x40000000u

#define	AIPS_PACRB_SP0_SHIFT 30

#define	AIPS_PACRC_TP7_MASK 0x1u

#define	AIPS_PACRC_TP7_SHIFT 0

#define	AIPS_PACRC_WP7_MASK 0x2u

#define	AIPS_PACRC_WP7_SHIFT 1

#define	AIPS_PACRC_SP7_MASK 0x4u

#define	AIPS_PACRC_SP7_SHIFT 2

#define	AIPS_PACRC_TP6_MASK 0x10u

#define	AIPS_PACRC_TP6_SHIFT 4

#define	AIPS_PACRC_WP6_MASK 0x20u

#define	AIPS_PACRC_WP6_SHIFT 5

#define	AIPS_PACRC_SP6_MASK 0x40u

#define	AIPS_PACRC_SP6_SHIFT 6

#define	AIPS_PACRC_TP5_MASK 0x100u

#define	AIPS_PACRC_TP5_SHIFT 8

#define	AIPS_PACRC_WP5_MASK 0x200u

#define	AIPS_PACRC_WP5_SHIFT 9

#define	AIPS_PACRC_SP5_MASK 0x400u

#define	AIPS_PACRC_SP5_SHIFT 10

#define	AIPS_PACRC_TP4_MASK 0x1000u

#define	AIPS_PACRC_TP4_SHIFT 12

#define	AIPS_PACRC_WP4_MASK 0x2000u

#define	AIPS_PACRC_WP4_SHIFT 13

#define	AIPS_PACRC_SP4_MASK 0x4000u

#define	AIPS_PACRC_SP4_SHIFT 14

#define	AIPS_PACRC_TP3_MASK 0x10000u

#define	AIPS_PACRC_TP3_SHIFT 16

#define	AIPS_PACRC_WP3_MASK 0x20000u

#define	AIPS_PACRC_WP3_SHIFT 17

#define	AIPS_PACRC_SP3_MASK 0x40000u

#define	AIPS_PACRC_SP3_SHIFT 18

#define	AIPS_PACRC_TP2_MASK 0x100000u

#define	AIPS_PACRC_TP2_SHIFT 20

#define	AIPS_PACRC_WP2_MASK 0x200000u

#define	AIPS_PACRC_WP2_SHIFT 21

#define	AIPS_PACRC_SP2_MASK 0x400000u

#define	AIPS_PACRC_SP2_SHIFT 22

#define	AIPS_PACRC_TP1_MASK 0x1000000u

#define	AIPS_PACRC_TP1_SHIFT 24

#define	AIPS_PACRC_WP1_MASK 0x2000000u

#define	AIPS_PACRC_WP1_SHIFT 25

#define	AIPS_PACRC_SP1_MASK 0x4000000u

#define	AIPS_PACRC_SP1_SHIFT 26

#define	AIPS_PACRC_TP0_MASK 0x10000000u

#define	AIPS_PACRC_TP0_SHIFT 28

#define	AIPS_PACRC_WP0_MASK 0x20000000u

#define	AIPS_PACRC_WP0_SHIFT 29

#define	AIPS_PACRC_SP0_MASK 0x40000000u

#define	AIPS_PACRC_SP0_SHIFT 30

#define	AIPS_PACRD_TP7_MASK 0x1u

#define	AIPS_PACRD_TP7_SHIFT 0

#define	AIPS_PACRD_WP7_MASK 0x2u

#define	AIPS_PACRD_WP7_SHIFT 1

#define	AIPS_PACRD_SP7_MASK 0x4u

#define	AIPS_PACRD_SP7_SHIFT 2

#define	AIPS_PACRD_TP6_MASK 0x10u

#define	AIPS_PACRD_TP6_SHIFT 4

#define	AIPS_PACRD_WP6_MASK 0x20u

#define	AIPS_PACRD_WP6_SHIFT 5

#define	AIPS_PACRD_SP6_MASK 0x40u

#define	AIPS_PACRD_SP6_SHIFT 6

#define	AIPS_PACRD_TP5_MASK 0x100u

#define	AIPS_PACRD_TP5_SHIFT 8

#define	AIPS_PACRD_WP5_MASK 0x200u

#define	AIPS_PACRD_WP5_SHIFT 9

#define	AIPS_PACRD_SP5_MASK 0x400u

#define	AIPS_PACRD_SP5_SHIFT 10

#define	AIPS_PACRD_TP4_MASK 0x1000u

#define	AIPS_PACRD_TP4_SHIFT 12

#define	AIPS_PACRD_WP4_MASK 0x2000u

#define	AIPS_PACRD_WP4_SHIFT 13

#define	AIPS_PACRD_SP4_MASK 0x4000u

#define	AIPS_PACRD_SP4_SHIFT 14

#define	AIPS_PACRD_TP3_MASK 0x10000u

#define	AIPS_PACRD_TP3_SHIFT 16

#define	AIPS_PACRD_WP3_MASK 0x20000u

#define	AIPS_PACRD_WP3_SHIFT 17

#define	AIPS_PACRD_SP3_MASK 0x40000u

#define	AIPS_PACRD_SP3_SHIFT 18

#define	AIPS_PACRD_TP2_MASK 0x100000u

#define	AIPS_PACRD_TP2_SHIFT 20

#define	AIPS_PACRD_WP2_MASK 0x200000u

#define	AIPS_PACRD_WP2_SHIFT 21

#define	AIPS_PACRD_SP2_MASK 0x400000u

#define	AIPS_PACRD_SP2_SHIFT 22

#define	AIPS_PACRD_TP1_MASK 0x1000000u

#define	AIPS_PACRD_TP1_SHIFT 24

#define	AIPS_PACRD_WP1_MASK 0x2000000u

#define	AIPS_PACRD_WP1_SHIFT 25

#define	AIPS_PACRD_SP1_MASK 0x4000000u

#define	AIPS_PACRD_SP1_SHIFT 26

#define	AIPS_PACRD_TP0_MASK 0x10000000u

#define	AIPS_PACRD_TP0_SHIFT 28

#define	AIPS_PACRD_WP0_MASK 0x20000000u

#define	AIPS_PACRD_WP0_SHIFT 29

#define	AIPS_PACRD_SP0_MASK 0x40000000u

#define	AIPS_PACRD_SP0_SHIFT 30

#define	AIPS_PACRE_TP7_MASK 0x1u

#define	AIPS_PACRE_TP7_SHIFT 0

#define	AIPS_PACRE_WP7_MASK 0x2u

#define	AIPS_PACRE_WP7_SHIFT 1

#define	AIPS_PACRE_SP7_MASK 0x4u

#define	AIPS_PACRE_SP7_SHIFT 2

#define	AIPS_PACRE_TP6_MASK 0x10u

#define	AIPS_PACRE_TP6_SHIFT 4

#define	AIPS_PACRE_WP6_MASK 0x20u

#define	AIPS_PACRE_WP6_SHIFT 5

#define	AIPS_PACRE_SP6_MASK 0x40u

#define	AIPS_PACRE_SP6_SHIFT 6

#define	AIPS_PACRE_TP5_MASK 0x100u

#define	AIPS_PACRE_TP5_SHIFT 8

#define	AIPS_PACRE_WP5_MASK 0x200u

#define	AIPS_PACRE_WP5_SHIFT 9

#define	AIPS_PACRE_SP5_MASK 0x400u

#define	AIPS_PACRE_SP5_SHIFT 10

#define	AIPS_PACRE_TP4_MASK 0x1000u

#define	AIPS_PACRE_TP4_SHIFT 12

#define	AIPS_PACRE_WP4_MASK 0x2000u

#define	AIPS_PACRE_WP4_SHIFT 13

#define	AIPS_PACRE_SP4_MASK 0x4000u

#define	AIPS_PACRE_SP4_SHIFT 14

#define	AIPS_PACRE_TP3_MASK 0x10000u

#define	AIPS_PACRE_TP3_SHIFT 16

#define	AIPS_PACRE_WP3_MASK 0x20000u

#define	AIPS_PACRE_WP3_SHIFT 17

#define	AIPS_PACRE_SP3_MASK 0x40000u

#define	AIPS_PACRE_SP3_SHIFT 18

#define	AIPS_PACRE_TP2_MASK 0x100000u

#define	AIPS_PACRE_TP2_SHIFT 20

#define	AIPS_PACRE_WP2_MASK 0x200000u

#define	AIPS_PACRE_WP2_SHIFT 21

#define	AIPS_PACRE_SP2_MASK 0x400000u

#define	AIPS_PACRE_SP2_SHIFT 22

#define	AIPS_PACRE_TP1_MASK 0x1000000u

#define	AIPS_PACRE_TP1_SHIFT 24

#define	AIPS_PACRE_WP1_MASK 0x2000000u

#define	AIPS_PACRE_WP1_SHIFT 25

#define	AIPS_PACRE_SP1_MASK 0x4000000u

#define	AIPS_PACRE_SP1_SHIFT 26

#define	AIPS_PACRE_TP0_MASK 0x10000000u

#define	AIPS_PACRE_TP0_SHIFT 28

#define	AIPS_PACRE_WP0_MASK 0x20000000u

#define	AIPS_PACRE_WP0_SHIFT 29

#define	AIPS_PACRE_SP0_MASK 0x40000000u

#define	AIPS_PACRE_SP0_SHIFT 30

#define	AIPS_PACRF_TP7_MASK 0x1u

#define	AIPS_PACRF_TP7_SHIFT 0

#define	AIPS_PACRF_WP7_MASK 0x2u

#define	AIPS_PACRF_WP7_SHIFT 1

#define	AIPS_PACRF_SP7_MASK 0x4u

#define	AIPS_PACRF_SP7_SHIFT 2

#define	AIPS_PACRF_TP6_MASK 0x10u

#define	AIPS_PACRF_TP6_SHIFT 4

#define	AIPS_PACRF_WP6_MASK 0x20u

#define	AIPS_PACRF_WP6_SHIFT 5

#define	AIPS_PACRF_SP6_MASK 0x40u

#define	AIPS_PACRF_SP6_SHIFT 6

#define	AIPS_PACRF_TP5_MASK 0x100u

#define	AIPS_PACRF_TP5_SHIFT 8

#define	AIPS_PACRF_WP5_MASK 0x200u

#define	AIPS_PACRF_WP5_SHIFT 9

#define	AIPS_PACRF_SP5_MASK 0x400u

#define	AIPS_PACRF_SP5_SHIFT 10

#define	AIPS_PACRF_TP4_MASK 0x1000u

#define	AIPS_PACRF_TP4_SHIFT 12

#define	AIPS_PACRF_WP4_MASK 0x2000u

#define	AIPS_PACRF_WP4_SHIFT 13

#define	AIPS_PACRF_SP4_MASK 0x4000u

#define	AIPS_PACRF_SP4_SHIFT 14

#define	AIPS_PACRF_TP3_MASK 0x10000u

#define	AIPS_PACRF_TP3_SHIFT 16

#define	AIPS_PACRF_WP3_MASK 0x20000u

#define	AIPS_PACRF_WP3_SHIFT 17

#define	AIPS_PACRF_SP3_MASK 0x40000u

#define	AIPS_PACRF_SP3_SHIFT 18

#define	AIPS_PACRF_TP2_MASK 0x100000u

#define	AIPS_PACRF_TP2_SHIFT 20

#define	AIPS_PACRF_WP2_MASK 0x200000u

#define	AIPS_PACRF_WP2_SHIFT 21

#define	AIPS_PACRF_SP2_MASK 0x400000u

#define	AIPS_PACRF_SP2_SHIFT 22

#define	AIPS_PACRF_TP1_MASK 0x1000000u

#define	AIPS_PACRF_TP1_SHIFT 24

#define	AIPS_PACRF_WP1_MASK 0x2000000u

#define	AIPS_PACRF_WP1_SHIFT 25

#define	AIPS_PACRF_SP1_MASK 0x4000000u

#define	AIPS_PACRF_SP1_SHIFT 26

#define	AIPS_PACRF_TP0_MASK 0x10000000u

#define	AIPS_PACRF_TP0_SHIFT 28

#define	AIPS_PACRF_WP0_MASK 0x20000000u

#define	AIPS_PACRF_WP0_SHIFT 29

#define	AIPS_PACRF_SP0_MASK 0x40000000u

#define	AIPS_PACRF_SP0_SHIFT 30

#define	AIPS_PACRG_TP7_MASK 0x1u

#define	AIPS_PACRG_TP7_SHIFT 0

#define	AIPS_PACRG_WP7_MASK 0x2u

#define	AIPS_PACRG_WP7_SHIFT 1

#define	AIPS_PACRG_SP7_MASK 0x4u

#define	AIPS_PACRG_SP7_SHIFT 2

#define	AIPS_PACRG_TP6_MASK 0x10u

#define	AIPS_PACRG_TP6_SHIFT 4

#define	AIPS_PACRG_WP6_MASK 0x20u

#define	AIPS_PACRG_WP6_SHIFT 5

#define	AIPS_PACRG_SP6_MASK 0x40u

#define	AIPS_PACRG_SP6_SHIFT 6

#define	AIPS_PACRG_TP5_MASK 0x100u

#define	AIPS_PACRG_TP5_SHIFT 8

#define	AIPS_PACRG_WP5_MASK 0x200u

#define	AIPS_PACRG_WP5_SHIFT 9

#define	AIPS_PACRG_SP5_MASK 0x400u

#define	AIPS_PACRG_SP5_SHIFT 10

#define	AIPS_PACRG_TP4_MASK 0x1000u

#define	AIPS_PACRG_TP4_SHIFT 12

#define	AIPS_PACRG_WP4_MASK 0x2000u

#define	AIPS_PACRG_WP4_SHIFT 13

#define	AIPS_PACRG_SP4_MASK 0x4000u

#define	AIPS_PACRG_SP4_SHIFT 14

#define	AIPS_PACRG_TP3_MASK 0x10000u

#define	AIPS_PACRG_TP3_SHIFT 16

#define	AIPS_PACRG_WP3_MASK 0x20000u

#define	AIPS_PACRG_WP3_SHIFT 17

#define	AIPS_PACRG_SP3_MASK 0x40000u

#define	AIPS_PACRG_SP3_SHIFT 18

#define	AIPS_PACRG_TP2_MASK 0x100000u

#define	AIPS_PACRG_TP2_SHIFT 20

#define	AIPS_PACRG_WP2_MASK 0x200000u

#define	AIPS_PACRG_WP2_SHIFT 21

#define	AIPS_PACRG_SP2_MASK 0x400000u

#define	AIPS_PACRG_SP2_SHIFT 22

#define	AIPS_PACRG_TP1_MASK 0x1000000u

#define	AIPS_PACRG_TP1_SHIFT 24

#define	AIPS_PACRG_WP1_MASK 0x2000000u

#define	AIPS_PACRG_WP1_SHIFT 25

#define	AIPS_PACRG_SP1_MASK 0x4000000u

#define	AIPS_PACRG_SP1_SHIFT 26

#define	AIPS_PACRG_TP0_MASK 0x10000000u

#define	AIPS_PACRG_TP0_SHIFT 28

#define	AIPS_PACRG_WP0_MASK 0x20000000u

#define	AIPS_PACRG_WP0_SHIFT 29

#define	AIPS_PACRG_SP0_MASK 0x40000000u

#define	AIPS_PACRG_SP0_SHIFT 30

#define	AIPS_PACRH_TP7_MASK 0x1u

#define	AIPS_PACRH_TP7_SHIFT 0

#define	AIPS_PACRH_WP7_MASK 0x2u

#define	AIPS_PACRH_WP7_SHIFT 1

#define	AIPS_PACRH_SP7_MASK 0x4u

#define	AIPS_PACRH_SP7_SHIFT 2

#define	AIPS_PACRH_TP6_MASK 0x10u

#define	AIPS_PACRH_TP6_SHIFT 4

#define	AIPS_PACRH_WP6_MASK 0x20u

#define	AIPS_PACRH_WP6_SHIFT 5

#define	AIPS_PACRH_SP6_MASK 0x40u

#define	AIPS_PACRH_SP6_SHIFT 6

#define	AIPS_PACRH_TP5_MASK 0x100u

#define	AIPS_PACRH_TP5_SHIFT 8

#define	AIPS_PACRH_WP5_MASK 0x200u

#define	AIPS_PACRH_WP5_SHIFT 9

#define	AIPS_PACRH_SP5_MASK 0x400u

#define	AIPS_PACRH_SP5_SHIFT 10

#define	AIPS_PACRH_TP4_MASK 0x1000u

#define	AIPS_PACRH_TP4_SHIFT 12

#define	AIPS_PACRH_WP4_MASK 0x2000u

#define	AIPS_PACRH_WP4_SHIFT 13

#define	AIPS_PACRH_SP4_MASK 0x4000u

#define	AIPS_PACRH_SP4_SHIFT 14

#define	AIPS_PACRH_TP3_MASK 0x10000u

#define	AIPS_PACRH_TP3_SHIFT 16

#define	AIPS_PACRH_WP3_MASK 0x20000u

#define	AIPS_PACRH_WP3_SHIFT 17

#define	AIPS_PACRH_SP3_MASK 0x40000u

#define	AIPS_PACRH_SP3_SHIFT 18

#define	AIPS_PACRH_TP2_MASK 0x100000u

#define	AIPS_PACRH_TP2_SHIFT 20

#define	AIPS_PACRH_WP2_MASK 0x200000u

#define	AIPS_PACRH_WP2_SHIFT 21

#define	AIPS_PACRH_SP2_MASK 0x400000u

#define	AIPS_PACRH_SP2_SHIFT 22

#define	AIPS_PACRH_TP1_MASK 0x1000000u

#define	AIPS_PACRH_TP1_SHIFT 24

#define	AIPS_PACRH_WP1_MASK 0x2000000u

#define	AIPS_PACRH_WP1_SHIFT 25

#define	AIPS_PACRH_SP1_MASK 0x4000000u

#define	AIPS_PACRH_SP1_SHIFT 26

#define	AIPS_PACRH_TP0_MASK 0x10000000u

#define	AIPS_PACRH_TP0_SHIFT 28

#define	AIPS_PACRH_WP0_MASK 0x20000000u

#define	AIPS_PACRH_WP0_SHIFT 29

#define	AIPS_PACRH_SP0_MASK 0x40000000u

#define	AIPS_PACRH_SP0_SHIFT 30

#define	AIPS_PACRI_TP7_MASK 0x1u

#define	AIPS_PACRI_TP7_SHIFT 0

#define	AIPS_PACRI_WP7_MASK 0x2u

#define	AIPS_PACRI_WP7_SHIFT 1

#define	AIPS_PACRI_SP7_MASK 0x4u

#define	AIPS_PACRI_SP7_SHIFT 2

#define	AIPS_PACRI_TP6_MASK 0x10u

#define	AIPS_PACRI_TP6_SHIFT 4

#define	AIPS_PACRI_WP6_MASK 0x20u

#define	AIPS_PACRI_WP6_SHIFT 5

#define	AIPS_PACRI_SP6_MASK 0x40u

#define	AIPS_PACRI_SP6_SHIFT 6

#define	AIPS_PACRI_TP5_MASK 0x100u

#define	AIPS_PACRI_TP5_SHIFT 8

#define	AIPS_PACRI_WP5_MASK 0x200u

#define	AIPS_PACRI_WP5_SHIFT 9

#define	AIPS_PACRI_SP5_MASK 0x400u

#define	AIPS_PACRI_SP5_SHIFT 10

#define	AIPS_PACRI_TP4_MASK 0x1000u

#define	AIPS_PACRI_TP4_SHIFT 12

#define	AIPS_PACRI_WP4_MASK 0x2000u

#define	AIPS_PACRI_WP4_SHIFT 13

#define	AIPS_PACRI_SP4_MASK 0x4000u

#define	AIPS_PACRI_SP4_SHIFT 14

#define	AIPS_PACRI_TP3_MASK 0x10000u

#define	AIPS_PACRI_TP3_SHIFT 16

#define	AIPS_PACRI_WP3_MASK 0x20000u

#define	AIPS_PACRI_WP3_SHIFT 17

#define	AIPS_PACRI_SP3_MASK 0x40000u

#define	AIPS_PACRI_SP3_SHIFT 18

#define	AIPS_PACRI_TP2_MASK 0x100000u

#define	AIPS_PACRI_TP2_SHIFT 20

#define	AIPS_PACRI_WP2_MASK 0x200000u

#define	AIPS_PACRI_WP2_SHIFT 21

#define	AIPS_PACRI_SP2_MASK 0x400000u

#define	AIPS_PACRI_SP2_SHIFT 22

#define	AIPS_PACRI_TP1_MASK 0x1000000u

#define	AIPS_PACRI_TP1_SHIFT 24

#define	AIPS_PACRI_WP1_MASK 0x2000000u

#define	AIPS_PACRI_WP1_SHIFT 25

#define	AIPS_PACRI_SP1_MASK 0x4000000u

#define	AIPS_PACRI_SP1_SHIFT 26

#define	AIPS_PACRI_TP0_MASK 0x10000000u

#define	AIPS_PACRI_TP0_SHIFT 28

#define	AIPS_PACRI_WP0_MASK 0x20000000u

#define	AIPS_PACRI_WP0_SHIFT 29

#define	AIPS_PACRI_SP0_MASK 0x40000000u

#define	AIPS_PACRI_SP0_SHIFT 30

#define	AIPS_PACRJ_TP7_MASK 0x1u

#define	AIPS_PACRJ_TP7_SHIFT 0

#define	AIPS_PACRJ_WP7_MASK 0x2u

#define	AIPS_PACRJ_WP7_SHIFT 1

#define	AIPS_PACRJ_SP7_MASK 0x4u

#define	AIPS_PACRJ_SP7_SHIFT 2

#define	AIPS_PACRJ_TP6_MASK 0x10u

#define	AIPS_PACRJ_TP6_SHIFT 4

#define	AIPS_PACRJ_WP6_MASK 0x20u

#define	AIPS_PACRJ_WP6_SHIFT 5

#define	AIPS_PACRJ_SP6_MASK 0x40u

#define	AIPS_PACRJ_SP6_SHIFT 6

#define	AIPS_PACRJ_TP5_MASK 0x100u

#define	AIPS_PACRJ_TP5_SHIFT 8

#define	AIPS_PACRJ_WP5_MASK 0x200u

#define	AIPS_PACRJ_WP5_SHIFT 9

#define	AIPS_PACRJ_SP5_MASK 0x400u

#define	AIPS_PACRJ_SP5_SHIFT 10

#define	AIPS_PACRJ_TP4_MASK 0x1000u

#define	AIPS_PACRJ_TP4_SHIFT 12

#define	AIPS_PACRJ_WP4_MASK 0x2000u

#define	AIPS_PACRJ_WP4_SHIFT 13

#define	AIPS_PACRJ_SP4_MASK 0x4000u

#define	AIPS_PACRJ_SP4_SHIFT 14

#define	AIPS_PACRJ_TP3_MASK 0x10000u

#define	AIPS_PACRJ_TP3_SHIFT 16

#define	AIPS_PACRJ_WP3_MASK 0x20000u

#define	AIPS_PACRJ_WP3_SHIFT 17

#define	AIPS_PACRJ_SP3_MASK 0x40000u

#define	AIPS_PACRJ_SP3_SHIFT 18

#define	AIPS_PACRJ_TP2_MASK 0x100000u

#define	AIPS_PACRJ_TP2_SHIFT 20

#define	AIPS_PACRJ_WP2_MASK 0x200000u

#define	AIPS_PACRJ_WP2_SHIFT 21

#define	AIPS_PACRJ_SP2_MASK 0x400000u

#define	AIPS_PACRJ_SP2_SHIFT 22

#define	AIPS_PACRJ_TP1_MASK 0x1000000u

#define	AIPS_PACRJ_TP1_SHIFT 24

#define	AIPS_PACRJ_WP1_MASK 0x2000000u

#define	AIPS_PACRJ_WP1_SHIFT 25

#define	AIPS_PACRJ_SP1_MASK 0x4000000u

#define	AIPS_PACRJ_SP1_SHIFT 26

#define	AIPS_PACRJ_TP0_MASK 0x10000000u

#define	AIPS_PACRJ_TP0_SHIFT 28

#define	AIPS_PACRJ_WP0_MASK 0x20000000u

#define	AIPS_PACRJ_WP0_SHIFT 29

#define	AIPS_PACRJ_SP0_MASK 0x40000000u

#define	AIPS_PACRJ_SP0_SHIFT 30

#define	AIPS_PACRK_TP7_MASK 0x1u

#define	AIPS_PACRK_TP7_SHIFT 0

#define	AIPS_PACRK_WP7_MASK 0x2u

#define	AIPS_PACRK_WP7_SHIFT 1

#define	AIPS_PACRK_SP7_MASK 0x4u

#define	AIPS_PACRK_SP7_SHIFT 2

#define	AIPS_PACRK_TP6_MASK 0x10u

#define	AIPS_PACRK_TP6_SHIFT 4

#define	AIPS_PACRK_WP6_MASK 0x20u

#define	AIPS_PACRK_WP6_SHIFT 5

#define	AIPS_PACRK_SP6_MASK 0x40u

#define	AIPS_PACRK_SP6_SHIFT 6

#define	AIPS_PACRK_TP5_MASK 0x100u

#define	AIPS_PACRK_TP5_SHIFT 8

#define	AIPS_PACRK_WP5_MASK 0x200u

#define	AIPS_PACRK_WP5_SHIFT 9

#define	AIPS_PACRK_SP5_MASK 0x400u

#define	AIPS_PACRK_SP5_SHIFT 10

#define	AIPS_PACRK_TP4_MASK 0x1000u

#define	AIPS_PACRK_TP4_SHIFT 12

#define	AIPS_PACRK_WP4_MASK 0x2000u

#define	AIPS_PACRK_WP4_SHIFT 13

#define	AIPS_PACRK_SP4_MASK 0x4000u

#define	AIPS_PACRK_SP4_SHIFT 14

#define	AIPS_PACRK_TP3_MASK 0x10000u

#define	AIPS_PACRK_TP3_SHIFT 16

#define	AIPS_PACRK_WP3_MASK 0x20000u

#define	AIPS_PACRK_WP3_SHIFT 17

#define	AIPS_PACRK_SP3_MASK 0x40000u

#define	AIPS_PACRK_SP3_SHIFT 18

#define	AIPS_PACRK_TP2_MASK 0x100000u

#define	AIPS_PACRK_TP2_SHIFT 20

#define	AIPS_PACRK_WP2_MASK 0x200000u

#define	AIPS_PACRK_WP2_SHIFT 21

#define	AIPS_PACRK_SP2_MASK 0x400000u

#define	AIPS_PACRK_SP2_SHIFT 22

#define	AIPS_PACRK_TP1_MASK 0x1000000u

#define	AIPS_PACRK_TP1_SHIFT 24

#define	AIPS_PACRK_WP1_MASK 0x2000000u

#define	AIPS_PACRK_WP1_SHIFT 25

#define	AIPS_PACRK_SP1_MASK 0x4000000u

#define	AIPS_PACRK_SP1_SHIFT 26

#define	AIPS_PACRK_TP0_MASK 0x10000000u

#define	AIPS_PACRK_TP0_SHIFT 28

#define	AIPS_PACRK_WP0_MASK 0x20000000u

#define	AIPS_PACRK_WP0_SHIFT 29

#define	AIPS_PACRK_SP0_MASK 0x40000000u

#define	AIPS_PACRK_SP0_SHIFT 30

#define	AIPS_PACRL_TP7_MASK 0x1u

#define	AIPS_PACRL_TP7_SHIFT 0

#define	AIPS_PACRL_WP7_MASK 0x2u

#define	AIPS_PACRL_WP7_SHIFT 1

#define	AIPS_PACRL_SP7_MASK 0x4u

#define	AIPS_PACRL_SP7_SHIFT 2

#define	AIPS_PACRL_TP6_MASK 0x10u

#define	AIPS_PACRL_TP6_SHIFT 4

#define	AIPS_PACRL_WP6_MASK 0x20u

#define	AIPS_PACRL_WP6_SHIFT 5

#define	AIPS_PACRL_SP6_MASK 0x40u

#define	AIPS_PACRL_SP6_SHIFT 6

#define	AIPS_PACRL_TP5_MASK 0x100u

#define	AIPS_PACRL_TP5_SHIFT 8

#define	AIPS_PACRL_WP5_MASK 0x200u

#define	AIPS_PACRL_WP5_SHIFT 9

#define	AIPS_PACRL_SP5_MASK 0x400u

#define	AIPS_PACRL_SP5_SHIFT 10

#define	AIPS_PACRL_TP4_MASK 0x1000u

#define	AIPS_PACRL_TP4_SHIFT 12

#define	AIPS_PACRL_WP4_MASK 0x2000u

#define	AIPS_PACRL_WP4_SHIFT 13

#define	AIPS_PACRL_SP4_MASK 0x4000u

#define	AIPS_PACRL_SP4_SHIFT 14

#define	AIPS_PACRL_TP3_MASK 0x10000u

#define	AIPS_PACRL_TP3_SHIFT 16

#define	AIPS_PACRL_WP3_MASK 0x20000u

#define	AIPS_PACRL_WP3_SHIFT 17

#define	AIPS_PACRL_SP3_MASK 0x40000u

#define	AIPS_PACRL_SP3_SHIFT 18

#define	AIPS_PACRL_TP2_MASK 0x100000u

#define	AIPS_PACRL_TP2_SHIFT 20

#define	AIPS_PACRL_WP2_MASK 0x200000u

#define	AIPS_PACRL_WP2_SHIFT 21

#define	AIPS_PACRL_SP2_MASK 0x400000u

#define	AIPS_PACRL_SP2_SHIFT 22

#define	AIPS_PACRL_TP1_MASK 0x1000000u

#define	AIPS_PACRL_TP1_SHIFT 24

#define	AIPS_PACRL_WP1_MASK 0x2000000u

#define	AIPS_PACRL_WP1_SHIFT 25

#define	AIPS_PACRL_SP1_MASK 0x4000000u

#define	AIPS_PACRL_SP1_SHIFT 26

#define	AIPS_PACRL_TP0_MASK 0x10000000u

#define	AIPS_PACRL_TP0_SHIFT 28

#define	AIPS_PACRL_WP0_MASK 0x20000000u

#define	AIPS_PACRL_WP0_SHIFT 29

#define	AIPS_PACRL_SP0_MASK 0x40000000u

#define	AIPS_PACRL_SP0_SHIFT 30

#define	AIPS_PACRM_TP7_MASK 0x1u

#define	AIPS_PACRM_TP7_SHIFT 0

#define	AIPS_PACRM_WP7_MASK 0x2u

#define	AIPS_PACRM_WP7_SHIFT 1

#define	AIPS_PACRM_SP7_MASK 0x4u

#define	AIPS_PACRM_SP7_SHIFT 2

#define	AIPS_PACRM_TP6_MASK 0x10u

#define	AIPS_PACRM_TP6_SHIFT 4

#define	AIPS_PACRM_WP6_MASK 0x20u

#define	AIPS_PACRM_WP6_SHIFT 5

#define	AIPS_PACRM_SP6_MASK 0x40u

#define	AIPS_PACRM_SP6_SHIFT 6

#define	AIPS_PACRM_TP5_MASK 0x100u

#define	AIPS_PACRM_TP5_SHIFT 8

#define	AIPS_PACRM_WP5_MASK 0x200u

#define	AIPS_PACRM_WP5_SHIFT 9

#define	AIPS_PACRM_SP5_MASK 0x400u

#define	AIPS_PACRM_SP5_SHIFT 10

#define	AIPS_PACRM_TP4_MASK 0x1000u

#define	AIPS_PACRM_TP4_SHIFT 12

#define	AIPS_PACRM_WP4_MASK 0x2000u

#define	AIPS_PACRM_WP4_SHIFT 13

#define	AIPS_PACRM_SP4_MASK 0x4000u

#define	AIPS_PACRM_SP4_SHIFT 14

#define	AIPS_PACRM_TP3_MASK 0x10000u

#define	AIPS_PACRM_TP3_SHIFT 16

#define	AIPS_PACRM_WP3_MASK 0x20000u

#define	AIPS_PACRM_WP3_SHIFT 17

#define	AIPS_PACRM_SP3_MASK 0x40000u

#define	AIPS_PACRM_SP3_SHIFT 18

#define	AIPS_PACRM_TP2_MASK 0x100000u

#define	AIPS_PACRM_TP2_SHIFT 20

#define	AIPS_PACRM_WP2_MASK 0x200000u

#define	AIPS_PACRM_WP2_SHIFT 21

#define	AIPS_PACRM_SP2_MASK 0x400000u

#define	AIPS_PACRM_SP2_SHIFT 22

#define	AIPS_PACRM_TP1_MASK 0x1000000u

#define	AIPS_PACRM_TP1_SHIFT 24

#define	AIPS_PACRM_WP1_MASK 0x2000000u

#define	AIPS_PACRM_WP1_SHIFT 25

#define	AIPS_PACRM_SP1_MASK 0x4000000u

#define	AIPS_PACRM_SP1_SHIFT 26

#define	AIPS_PACRM_TP0_MASK 0x10000000u

#define	AIPS_PACRM_TP0_SHIFT 28

#define	AIPS_PACRM_WP0_MASK 0x20000000u

#define	AIPS_PACRM_WP0_SHIFT 29

#define	AIPS_PACRM_SP0_MASK 0x40000000u

#define	AIPS_PACRM_SP0_SHIFT 30

#define	AIPS_PACRN_TP7_MASK 0x1u

#define	AIPS_PACRN_TP7_SHIFT 0

#define	AIPS_PACRN_WP7_MASK 0x2u

#define	AIPS_PACRN_WP7_SHIFT 1

#define	AIPS_PACRN_SP7_MASK 0x4u

#define	AIPS_PACRN_SP7_SHIFT 2

#define	AIPS_PACRN_TP6_MASK 0x10u

#define	AIPS_PACRN_TP6_SHIFT 4

#define	AIPS_PACRN_WP6_MASK 0x20u

#define	AIPS_PACRN_WP6_SHIFT 5

#define	AIPS_PACRN_SP6_MASK 0x40u

#define	AIPS_PACRN_SP6_SHIFT 6

#define	AIPS_PACRN_TP5_MASK 0x100u

#define	AIPS_PACRN_TP5_SHIFT 8

#define	AIPS_PACRN_WP5_MASK 0x200u

#define	AIPS_PACRN_WP5_SHIFT 9

#define	AIPS_PACRN_SP5_MASK 0x400u

#define	AIPS_PACRN_SP5_SHIFT 10

#define	AIPS_PACRN_TP4_MASK 0x1000u

#define	AIPS_PACRN_TP4_SHIFT 12

#define	AIPS_PACRN_WP4_MASK 0x2000u

#define	AIPS_PACRN_WP4_SHIFT 13

#define	AIPS_PACRN_SP4_MASK 0x4000u

#define	AIPS_PACRN_SP4_SHIFT 14

#define	AIPS_PACRN_TP3_MASK 0x10000u

#define	AIPS_PACRN_TP3_SHIFT 16

#define	AIPS_PACRN_WP3_MASK 0x20000u

#define	AIPS_PACRN_WP3_SHIFT 17

#define	AIPS_PACRN_SP3_MASK 0x40000u

#define	AIPS_PACRN_SP3_SHIFT 18

#define	AIPS_PACRN_TP2_MASK 0x100000u

#define	AIPS_PACRN_TP2_SHIFT 20

#define	AIPS_PACRN_WP2_MASK 0x200000u

#define	AIPS_PACRN_WP2_SHIFT 21

#define	AIPS_PACRN_SP2_MASK 0x400000u

#define	AIPS_PACRN_SP2_SHIFT 22

#define	AIPS_PACRN_TP1_MASK 0x1000000u

#define	AIPS_PACRN_TP1_SHIFT 24

#define	AIPS_PACRN_WP1_MASK 0x2000000u

#define	AIPS_PACRN_WP1_SHIFT 25

#define	AIPS_PACRN_SP1_MASK 0x4000000u

#define	AIPS_PACRN_SP1_SHIFT 26

#define	AIPS_PACRN_TP0_MASK 0x10000000u

#define	AIPS_PACRN_TP0_SHIFT 28

#define	AIPS_PACRN_WP0_MASK 0x20000000u

#define	AIPS_PACRN_WP0_SHIFT 29

#define	AIPS_PACRN_SP0_MASK 0x40000000u

#define	AIPS_PACRN_SP0_SHIFT 30

#define	AIPS_PACRO_TP7_MASK 0x1u

#define	AIPS_PACRO_TP7_SHIFT 0

#define	AIPS_PACRO_WP7_MASK 0x2u

#define	AIPS_PACRO_WP7_SHIFT 1

#define	AIPS_PACRO_SP7_MASK 0x4u

#define	AIPS_PACRO_SP7_SHIFT 2

#define	AIPS_PACRO_TP6_MASK 0x10u

#define	AIPS_PACRO_TP6_SHIFT 4

#define	AIPS_PACRO_WP6_MASK 0x20u

#define	AIPS_PACRO_WP6_SHIFT 5

#define	AIPS_PACRO_SP6_MASK 0x40u

#define	AIPS_PACRO_SP6_SHIFT 6

#define	AIPS_PACRO_TP5_MASK 0x100u

#define	AIPS_PACRO_TP5_SHIFT 8

#define	AIPS_PACRO_WP5_MASK 0x200u

#define	AIPS_PACRO_WP5_SHIFT 9

#define	AIPS_PACRO_SP5_MASK 0x400u

#define	AIPS_PACRO_SP5_SHIFT 10

#define	AIPS_PACRO_TP4_MASK 0x1000u

#define	AIPS_PACRO_TP4_SHIFT 12

#define	AIPS_PACRO_WP4_MASK 0x2000u

#define	AIPS_PACRO_WP4_SHIFT 13

#define	AIPS_PACRO_SP4_MASK 0x4000u

#define	AIPS_PACRO_SP4_SHIFT 14

#define	AIPS_PACRO_TP3_MASK 0x10000u

#define	AIPS_PACRO_TP3_SHIFT 16

#define	AIPS_PACRO_WP3_MASK 0x20000u

#define	AIPS_PACRO_WP3_SHIFT 17

#define	AIPS_PACRO_SP3_MASK 0x40000u

#define	AIPS_PACRO_SP3_SHIFT 18

#define	AIPS_PACRO_TP2_MASK 0x100000u

#define	AIPS_PACRO_TP2_SHIFT 20

#define	AIPS_PACRO_WP2_MASK 0x200000u

#define	AIPS_PACRO_WP2_SHIFT 21

#define	AIPS_PACRO_SP2_MASK 0x400000u

#define	AIPS_PACRO_SP2_SHIFT 22

#define	AIPS_PACRO_TP1_MASK 0x1000000u

#define	AIPS_PACRO_TP1_SHIFT 24

#define	AIPS_PACRO_WP1_MASK 0x2000000u

#define	AIPS_PACRO_WP1_SHIFT 25

#define	AIPS_PACRO_SP1_MASK 0x4000000u

#define	AIPS_PACRO_SP1_SHIFT 26

#define	AIPS_PACRO_TP0_MASK 0x10000000u

#define	AIPS_PACRO_TP0_SHIFT 28

#define	AIPS_PACRO_WP0_MASK 0x20000000u

#define	AIPS_PACRO_WP0_SHIFT 29

#define	AIPS_PACRO_SP0_MASK 0x40000000u

#define	AIPS_PACRO_SP0_SHIFT 30

#define	AIPS_PACRP_TP7_MASK 0x1u

#define	AIPS_PACRP_TP7_SHIFT 0

#define	AIPS_PACRP_WP7_MASK 0x2u

#define	AIPS_PACRP_WP7_SHIFT 1

#define	AIPS_PACRP_SP7_MASK 0x4u

#define	AIPS_PACRP_SP7_SHIFT 2

#define	AIPS_PACRP_TP6_MASK 0x10u

#define	AIPS_PACRP_TP6_SHIFT 4

#define	AIPS_PACRP_WP6_MASK 0x20u

#define	AIPS_PACRP_WP6_SHIFT 5

#define	AIPS_PACRP_SP6_MASK 0x40u

#define	AIPS_PACRP_SP6_SHIFT 6

#define	AIPS_PACRP_TP5_MASK 0x100u

#define	AIPS_PACRP_TP5_SHIFT 8

#define	AIPS_PACRP_WP5_MASK 0x200u

#define	AIPS_PACRP_WP5_SHIFT 9

#define	AIPS_PACRP_SP5_MASK 0x400u

#define	AIPS_PACRP_SP5_SHIFT 10

#define	AIPS_PACRP_TP4_MASK 0x1000u

#define	AIPS_PACRP_TP4_SHIFT 12

#define	AIPS_PACRP_WP4_MASK 0x2000u

#define	AIPS_PACRP_WP4_SHIFT 13

#define	AIPS_PACRP_SP4_MASK 0x4000u

#define	AIPS_PACRP_SP4_SHIFT 14

#define	AIPS_PACRP_TP3_MASK 0x10000u

#define	AIPS_PACRP_TP3_SHIFT 16

#define	AIPS_PACRP_WP3_MASK 0x20000u

#define	AIPS_PACRP_WP3_SHIFT 17

#define	AIPS_PACRP_SP3_MASK 0x40000u

#define	AIPS_PACRP_SP3_SHIFT 18

#define	AIPS_PACRP_TP2_MASK 0x100000u

#define	AIPS_PACRP_TP2_SHIFT 20

#define	AIPS_PACRP_WP2_MASK 0x200000u

#define	AIPS_PACRP_WP2_SHIFT 21

#define	AIPS_PACRP_SP2_MASK 0x400000u

#define	AIPS_PACRP_SP2_SHIFT 22

#define	AIPS_PACRP_TP1_MASK 0x1000000u

#define	AIPS_PACRP_TP1_SHIFT 24

#define	AIPS_PACRP_WP1_MASK 0x2000000u

#define	AIPS_PACRP_WP1_SHIFT 25

#define	AIPS_PACRP_SP1_MASK 0x4000000u

#define	AIPS_PACRP_SP1_SHIFT 26

#define	AIPS_PACRP_TP0_MASK 0x10000000u

#define	AIPS_PACRP_TP0_SHIFT 28

#define	AIPS_PACRP_WP0_MASK 0x20000000u

#define	AIPS_PACRP_WP0_SHIFT 29

#define	AIPS_PACRP_SP0_MASK 0x40000000u

#define	AIPS_PACRP_SP0_SHIFT 30

#define	AIPS0_BASE_PTR ((AIPS_MemMapPtr)0x40000000u)

#define	AIPS1_BASE_PTR ((AIPS_MemMapPtr)0x40080000u)

#define	AIPS_BASE_PTRS { AIPS0_BASE_PTR, AIPS1_BASE_PTR }

#define	AIPS0_MPRA AIPS_MPRA_REG(AIPS0_BASE_PTR)

#define	AIPS0_PACRA AIPS_PACRA_REG(AIPS0_BASE_PTR)

#define	AIPS0_PACRB AIPS_PACRB_REG(AIPS0_BASE_PTR)

#define	AIPS0_PACRC AIPS_PACRC_REG(AIPS0_BASE_PTR)

#define	AIPS0_PACRD AIPS_PACRD_REG(AIPS0_BASE_PTR)

#define	AIPS0_PACRE AIPS_PACRE_REG(AIPS0_BASE_PTR)

#define	AIPS0_PACRF AIPS_PACRF_REG(AIPS0_BASE_PTR)

#define	AIPS0_PACRG AIPS_PACRG_REG(AIPS0_BASE_PTR)

#define	AIPS0_PACRH AIPS_PACRH_REG(AIPS0_BASE_PTR)

#define	AIPS0_PACRI AIPS_PACRI_REG(AIPS0_BASE_PTR)

#define	AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0_BASE_PTR)

#define	AIPS0_PACRK AIPS_PACRK_REG(AIPS0_BASE_PTR)

#define	AIPS0_PACRL AIPS_PACRL_REG(AIPS0_BASE_PTR)

#define	AIPS0_PACRM AIPS_PACRM_REG(AIPS0_BASE_PTR)

#define	AIPS0_PACRN AIPS_PACRN_REG(AIPS0_BASE_PTR)

#define	AIPS0_PACRO AIPS_PACRO_REG(AIPS0_BASE_PTR)

#define	AIPS0_PACRP AIPS_PACRP_REG(AIPS0_BASE_PTR)

#define	AIPS1_MPRA AIPS_MPRA_REG(AIPS1_BASE_PTR)

#define	AIPS1_PACRA AIPS_PACRA_REG(AIPS1_BASE_PTR)

#define	AIPS1_PACRB AIPS_PACRB_REG(AIPS1_BASE_PTR)

#define	AIPS1_PACRC AIPS_PACRC_REG(AIPS1_BASE_PTR)

#define	AIPS1_PACRD AIPS_PACRD_REG(AIPS1_BASE_PTR)

#define	AIPS1_PACRE AIPS_PACRE_REG(AIPS1_BASE_PTR)

#define	AIPS1_PACRF AIPS_PACRF_REG(AIPS1_BASE_PTR)

#define	AIPS1_PACRG AIPS_PACRG_REG(AIPS1_BASE_PTR)

#define	AIPS1_PACRH AIPS_PACRH_REG(AIPS1_BASE_PTR)

#define	AIPS1_PACRI AIPS_PACRI_REG(AIPS1_BASE_PTR)

#define	AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1_BASE_PTR)

#define	AIPS1_PACRK AIPS_PACRK_REG(AIPS1_BASE_PTR)

#define	AIPS1_PACRL AIPS_PACRL_REG(AIPS1_BASE_PTR)

#define	AIPS1_PACRM AIPS_PACRM_REG(AIPS1_BASE_PTR)

#define	AIPS1_PACRN AIPS_PACRN_REG(AIPS1_BASE_PTR)

#define	AIPS1_PACRO AIPS_PACRO_REG(AIPS1_BASE_PTR)

#define	AIPS1_PACRP AIPS_PACRP_REG(AIPS1_BASE_PTR)

#define	AXBS_PRS_REG(base, index) ((base)->SLAVE[index].PRS)

#define	AXBS_CRS_REG(base, index) ((base)->SLAVE[index].CRS)

#define	AXBS_MGPCR0_REG(base) ((base)->MGPCR0)

#define	AXBS_MGPCR1_REG(base) ((base)->MGPCR1)

#define	AXBS_MGPCR2_REG(base) ((base)->MGPCR2)

#define	AXBS_MGPCR3_REG(base) ((base)->MGPCR3)

#define	AXBS_MGPCR4_REG(base) ((base)->MGPCR4)

#define	AXBS_MGPCR5_REG(base) ((base)->MGPCR5)

#define	AXBS_MGPCR6_REG(base) ((base)->MGPCR6)

#define	AXBS_MGPCR7_REG(base) ((base)->MGPCR7)

#define	AXBS_PRS_M0_MASK 0x7u

#define	AXBS_PRS_M0_SHIFT 0

#define	AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)

#define	AXBS_PRS_M1_MASK 0x70u

#define	AXBS_PRS_M1_SHIFT 4

#define	AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)

#define	AXBS_PRS_M2_MASK 0x700u

#define	AXBS_PRS_M2_SHIFT 8

#define	AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)

#define	AXBS_PRS_M3_MASK 0x7000u

#define	AXBS_PRS_M3_SHIFT 12

#define	AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)

#define	AXBS_PRS_M4_MASK 0x70000u

#define	AXBS_PRS_M4_SHIFT 16

#define	AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)

#define	AXBS_PRS_M5_MASK 0x700000u

#define	AXBS_PRS_M5_SHIFT 20

#define	AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)

#define	AXBS_PRS_M6_MASK 0x7000000u

#define	AXBS_PRS_M6_SHIFT 24

#define	AXBS_PRS_M6(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M6_SHIFT))&AXBS_PRS_M6_MASK)

#define	AXBS_PRS_M7_MASK 0x70000000u

#define	AXBS_PRS_M7_SHIFT 28

#define	AXBS_PRS_M7(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M7_SHIFT))&AXBS_PRS_M7_MASK)

#define	AXBS_CRS_PARK_MASK 0x7u

#define	AXBS_CRS_PARK_SHIFT 0

#define	AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)

#define	AXBS_CRS_PCTL_MASK 0x30u

#define	AXBS_CRS_PCTL_SHIFT 4

#define	AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)

#define	AXBS_CRS_ARB_MASK 0x300u

#define	AXBS_CRS_ARB_SHIFT 8

#define	AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)

#define	AXBS_CRS_HLP_MASK 0x40000000u

#define	AXBS_CRS_HLP_SHIFT 30

#define	AXBS_CRS_RO_MASK 0x80000000u

#define	AXBS_CRS_RO_SHIFT 31

#define	AXBS_MGPCR0_AULB_MASK 0x7u

#define	AXBS_MGPCR0_AULB_SHIFT 0

#define	AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)

#define	AXBS_MGPCR1_AULB_MASK 0x7u

#define	AXBS_MGPCR1_AULB_SHIFT 0

#define	AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)

#define	AXBS_MGPCR2_AULB_MASK 0x7u

#define	AXBS_MGPCR2_AULB_SHIFT 0

#define	AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)

#define	AXBS_MGPCR3_AULB_MASK 0x7u

#define	AXBS_MGPCR3_AULB_SHIFT 0

#define	AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)

#define	AXBS_MGPCR4_AULB_MASK 0x7u

#define	AXBS_MGPCR4_AULB_SHIFT 0

#define	AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)

#define	AXBS_MGPCR5_AULB_MASK 0x7u

#define	AXBS_MGPCR5_AULB_SHIFT 0

#define	AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)

#define	AXBS_MGPCR6_AULB_MASK 0x7u

#define	AXBS_MGPCR6_AULB_SHIFT 0

#define	AXBS_MGPCR6_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR6_AULB_SHIFT))&AXBS_MGPCR6_AULB_MASK)

#define	AXBS_MGPCR7_AULB_MASK 0x7u

#define	AXBS_MGPCR7_AULB_SHIFT 0

#define	AXBS_MGPCR7_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR7_AULB_SHIFT))&AXBS_MGPCR7_AULB_MASK)

#define	AXBS_BASE_PTR ((AXBS_MemMapPtr)0x40004000u)

#define	AXBS_BASE_PTRS { AXBS_BASE_PTR }

#define	AXBS_PRS0 AXBS_PRS_REG(AXBS_BASE_PTR,0)

#define	AXBS_CRS0 AXBS_CRS_REG(AXBS_BASE_PTR,0)

#define	AXBS_PRS1 AXBS_PRS_REG(AXBS_BASE_PTR,1)

#define	AXBS_CRS1 AXBS_CRS_REG(AXBS_BASE_PTR,1)

#define	AXBS_PRS2 AXBS_PRS_REG(AXBS_BASE_PTR,2)

#define	AXBS_CRS2 AXBS_CRS_REG(AXBS_BASE_PTR,2)

#define	AXBS_PRS3 AXBS_PRS_REG(AXBS_BASE_PTR,3)

#define	AXBS_CRS3 AXBS_CRS_REG(AXBS_BASE_PTR,3)

#define	AXBS_PRS4 AXBS_PRS_REG(AXBS_BASE_PTR,4)

#define	AXBS_CRS4 AXBS_CRS_REG(AXBS_BASE_PTR,4)

#define	AXBS_PRS5 AXBS_PRS_REG(AXBS_BASE_PTR,5)

#define	AXBS_CRS5 AXBS_CRS_REG(AXBS_BASE_PTR,5)

#define	AXBS_PRS6 AXBS_PRS_REG(AXBS_BASE_PTR,6)

#define	AXBS_CRS6 AXBS_CRS_REG(AXBS_BASE_PTR,6)

#define	AXBS_PRS7 AXBS_PRS_REG(AXBS_BASE_PTR,7)

#define	AXBS_CRS7 AXBS_CRS_REG(AXBS_BASE_PTR,7)

#define	AXBS_MGPCR0 AXBS_MGPCR0_REG(AXBS_BASE_PTR)

#define	AXBS_MGPCR1 AXBS_MGPCR1_REG(AXBS_BASE_PTR)

#define	AXBS_MGPCR2 AXBS_MGPCR2_REG(AXBS_BASE_PTR)

#define	AXBS_MGPCR3 AXBS_MGPCR3_REG(AXBS_BASE_PTR)

#define	AXBS_MGPCR4 AXBS_MGPCR4_REG(AXBS_BASE_PTR)

#define	AXBS_MGPCR5 AXBS_MGPCR5_REG(AXBS_BASE_PTR)

#define	AXBS_MGPCR6 AXBS_MGPCR6_REG(AXBS_BASE_PTR)

#define	AXBS_MGPCR7 AXBS_MGPCR7_REG(AXBS_BASE_PTR)

#define	AXBS_PRS(index) AXBS_PRS_REG(AXBS_BASE_PTR,index)

#define	AXBS_CRS(index) AXBS_CRS_REG(AXBS_BASE_PTR,index)

#define	CAN_MCR_REG(base) ((base)->MCR)

#define	CAN_CTRL1_REG(base) ((base)->CTRL1)

#define	CAN_TIMER_REG(base) ((base)->TIMER)

#define	CAN_RXMGMASK_REG(base) ((base)->RXMGMASK)

#define	CAN_RX14MASK_REG(base) ((base)->RX14MASK)

#define	CAN_RX15MASK_REG(base) ((base)->RX15MASK)

#define	CAN_ECR_REG(base) ((base)->ECR)

#define	CAN_ESR1_REG(base) ((base)->ESR1)

#define	CAN_IMASK2_REG(base) ((base)->IMASK2)

#define	CAN_IMASK1_REG(base) ((base)->IMASK1)

#define	CAN_IFLAG2_REG(base) ((base)->IFLAG2)

#define	CAN_IFLAG1_REG(base) ((base)->IFLAG1)

#define	CAN_CTRL2_REG(base) ((base)->CTRL2)

#define	CAN_ESR2_REG(base) ((base)->ESR2)

#define	CAN_CRCR_REG(base) ((base)->CRCR)

#define	CAN_RXFGMASK_REG(base) ((base)->RXFGMASK)

#define	CAN_RXFIR_REG(base) ((base)->RXFIR)

#define	CAN_CS_REG(base, index) ((base)->MB[index].CS)

#define	CAN_ID_REG(base, index) ((base)->MB[index].ID)

#define	CAN_WORD0_REG(base, index) ((base)->MB[index].WORD0)

#define	CAN_WORD1_REG(base, index) ((base)->MB[index].WORD1)

#define	CAN_RXIMR_REG(base, index) ((base)->RXIMR[index])

#define	CAN_MCR_MAXMB_MASK 0x7Fu

#define	CAN_MCR_MAXMB_SHIFT 0

#define	CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)

#define	CAN_MCR_IDAM_MASK 0x300u

#define	CAN_MCR_IDAM_SHIFT 8

#define	CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)

#define	CAN_MCR_AEN_MASK 0x1000u

#define	CAN_MCR_AEN_SHIFT 12

#define	CAN_MCR_LPRIOEN_MASK 0x2000u

#define	CAN_MCR_LPRIOEN_SHIFT 13

#define	CAN_MCR_IRMQ_MASK 0x10000u

#define	CAN_MCR_IRMQ_SHIFT 16

#define	CAN_MCR_SRXDIS_MASK 0x20000u

#define	CAN_MCR_SRXDIS_SHIFT 17

#define	CAN_MCR_LPMACK_MASK 0x100000u

#define	CAN_MCR_LPMACK_SHIFT 20

#define	CAN_MCR_WRNEN_MASK 0x200000u

#define	CAN_MCR_WRNEN_SHIFT 21

#define	CAN_MCR_SLFWAK_MASK 0x400000u

#define	CAN_MCR_SLFWAK_SHIFT 22

#define	CAN_MCR_SUPV_MASK 0x800000u

#define	CAN_MCR_SUPV_SHIFT 23

#define	CAN_MCR_FRZACK_MASK 0x1000000u

#define	CAN_MCR_FRZACK_SHIFT 24

#define	CAN_MCR_SOFTRST_MASK 0x2000000u

#define	CAN_MCR_SOFTRST_SHIFT 25

#define	CAN_MCR_WAKMSK_MASK 0x4000000u

#define	CAN_MCR_WAKMSK_SHIFT 26

#define	CAN_MCR_NOTRDY_MASK 0x8000000u

#define	CAN_MCR_NOTRDY_SHIFT 27

#define	CAN_MCR_HALT_MASK 0x10000000u

#define	CAN_MCR_HALT_SHIFT 28

#define	CAN_MCR_RFEN_MASK 0x20000000u

#define	CAN_MCR_RFEN_SHIFT 29

#define	CAN_MCR_FRZ_MASK 0x40000000u

#define	CAN_MCR_FRZ_SHIFT 30

#define	CAN_MCR_MDIS_MASK 0x80000000u

#define	CAN_MCR_MDIS_SHIFT 31

#define	CAN_CTRL1_PROPSEG_MASK 0x7u

#define	CAN_CTRL1_PROPSEG_SHIFT 0

#define	CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)

#define	CAN_CTRL1_LOM_MASK 0x8u

#define	CAN_CTRL1_LOM_SHIFT 3

#define	CAN_CTRL1_LBUF_MASK 0x10u

#define	CAN_CTRL1_LBUF_SHIFT 4

#define	CAN_CTRL1_TSYN_MASK 0x20u

#define	CAN_CTRL1_TSYN_SHIFT 5

#define	CAN_CTRL1_BOFFREC_MASK 0x40u

#define	CAN_CTRL1_BOFFREC_SHIFT 6

#define	CAN_CTRL1_SMP_MASK 0x80u

#define	CAN_CTRL1_SMP_SHIFT 7

#define	CAN_CTRL1_RWRNMSK_MASK 0x400u

#define	CAN_CTRL1_RWRNMSK_SHIFT 10

#define	CAN_CTRL1_TWRNMSK_MASK 0x800u

#define	CAN_CTRL1_TWRNMSK_SHIFT 11

#define	CAN_CTRL1_LPB_MASK 0x1000u

#define	CAN_CTRL1_LPB_SHIFT 12

#define	CAN_CTRL1_CLKSRC_MASK 0x2000u

#define	CAN_CTRL1_CLKSRC_SHIFT 13

#define	CAN_CTRL1_ERRMSK_MASK 0x4000u

#define	CAN_CTRL1_ERRMSK_SHIFT 14

#define	CAN_CTRL1_BOFFMSK_MASK 0x8000u

#define	CAN_CTRL1_BOFFMSK_SHIFT 15

#define	CAN_CTRL1_PSEG2_MASK 0x70000u

#define	CAN_CTRL1_PSEG2_SHIFT 16

#define	CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)

#define	CAN_CTRL1_PSEG1_MASK 0x380000u

#define	CAN_CTRL1_PSEG1_SHIFT 19

#define	CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)

#define	CAN_CTRL1_RJW_MASK 0xC00000u

#define	CAN_CTRL1_RJW_SHIFT 22

#define	CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)

#define	CAN_CTRL1_PRESDIV_MASK 0xFF000000u

#define	CAN_CTRL1_PRESDIV_SHIFT 24

#define	CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)

#define	CAN_TIMER_TIMER_MASK 0xFFFFu

#define	CAN_TIMER_TIMER_SHIFT 0

#define	CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)

#define	CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu

#define	CAN_RXMGMASK_MG_SHIFT 0

#define	CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)

#define	CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu

#define	CAN_RX14MASK_RX14M_SHIFT 0

#define	CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)

#define	CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu

#define	CAN_RX15MASK_RX15M_SHIFT 0

#define	CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)

#define	CAN_ECR_TXERRCNT_MASK 0xFFu

#define	CAN_ECR_TXERRCNT_SHIFT 0

#define	CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)

#define	CAN_ECR_RXERRCNT_MASK 0xFF00u

#define	CAN_ECR_RXERRCNT_SHIFT 8

#define	CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)

#define	CAN_ESR1_WAKINT_MASK 0x1u

#define	CAN_ESR1_WAKINT_SHIFT 0

#define	CAN_ESR1_ERRINT_MASK 0x2u

#define	CAN_ESR1_ERRINT_SHIFT 1

#define	CAN_ESR1_BOFFINT_MASK 0x4u

#define	CAN_ESR1_BOFFINT_SHIFT 2

#define	CAN_ESR1_RX_MASK 0x8u

#define	CAN_ESR1_RX_SHIFT 3

#define	CAN_ESR1_FLTCONF_MASK 0x30u

#define	CAN_ESR1_FLTCONF_SHIFT 4

#define	CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)

#define	CAN_ESR1_TX_MASK 0x40u

#define	CAN_ESR1_TX_SHIFT 6

#define	CAN_ESR1_IDLE_MASK 0x80u

#define	CAN_ESR1_IDLE_SHIFT 7

#define	CAN_ESR1_RXWRN_MASK 0x100u

#define	CAN_ESR1_RXWRN_SHIFT 8

#define	CAN_ESR1_TXWRN_MASK 0x200u

#define	CAN_ESR1_TXWRN_SHIFT 9

#define	CAN_ESR1_STFERR_MASK 0x400u

#define	CAN_ESR1_STFERR_SHIFT 10

#define	CAN_ESR1_FRMERR_MASK 0x800u

#define	CAN_ESR1_FRMERR_SHIFT 11

#define	CAN_ESR1_CRCERR_MASK 0x1000u

#define	CAN_ESR1_CRCERR_SHIFT 12

#define	CAN_ESR1_ACKERR_MASK 0x2000u

#define	CAN_ESR1_ACKERR_SHIFT 13

#define	CAN_ESR1_BIT0ERR_MASK 0x4000u

#define	CAN_ESR1_BIT0ERR_SHIFT 14

#define	CAN_ESR1_BIT1ERR_MASK 0x8000u

#define	CAN_ESR1_BIT1ERR_SHIFT 15

#define	CAN_ESR1_RWRNINT_MASK 0x10000u

#define	CAN_ESR1_RWRNINT_SHIFT 16

#define	CAN_ESR1_TWRNINT_MASK 0x20000u

#define	CAN_ESR1_TWRNINT_SHIFT 17

#define	CAN_ESR1_SYNCH_MASK 0x40000u

#define	CAN_ESR1_SYNCH_SHIFT 18

#define	CAN_IMASK2_BUFHM_MASK 0xFFFFFFFFu

#define	CAN_IMASK2_BUFHM_SHIFT 0

#define	CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK2_BUFHM_SHIFT))&CAN_IMASK2_BUFHM_MASK)

#define	CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu

#define	CAN_IMASK1_BUFLM_SHIFT 0

#define	CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)

#define	CAN_IFLAG2_BUFHI_MASK 0xFFFFFFFFu

#define	CAN_IFLAG2_BUFHI_SHIFT 0

#define	CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG2_BUFHI_SHIFT))&CAN_IFLAG2_BUFHI_MASK)

#define	CAN_IFLAG1_BUF4TO0I_MASK 0x1Fu

#define	CAN_IFLAG1_BUF4TO0I_SHIFT 0

#define	CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO0I_SHIFT))&CAN_IFLAG1_BUF4TO0I_MASK)

#define	CAN_IFLAG1_BUF5I_MASK 0x20u

#define	CAN_IFLAG1_BUF5I_SHIFT 5

#define	CAN_IFLAG1_BUF6I_MASK 0x40u

#define	CAN_IFLAG1_BUF6I_SHIFT 6

#define	CAN_IFLAG1_BUF7I_MASK 0x80u

#define	CAN_IFLAG1_BUF7I_SHIFT 7

#define	CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u

#define	CAN_IFLAG1_BUF31TO8I_SHIFT 8

#define	CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)

#define	CAN_CTRL2_EACEN_MASK 0x10000u

#define	CAN_CTRL2_EACEN_SHIFT 16

#define	CAN_CTRL2_RRS_MASK 0x20000u

#define	CAN_CTRL2_RRS_SHIFT 17

#define	CAN_CTRL2_MRP_MASK 0x40000u

#define	CAN_CTRL2_MRP_SHIFT 18

#define	CAN_CTRL2_TASD_MASK 0xF80000u

#define	CAN_CTRL2_TASD_SHIFT 19

#define	CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)

#define	CAN_CTRL2_RFFN_MASK 0xF000000u

#define	CAN_CTRL2_RFFN_SHIFT 24

#define	CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)

#define	CAN_CTRL2_WRMFRZ_MASK 0x10000000u

#define	CAN_CTRL2_WRMFRZ_SHIFT 28

#define	CAN_ESR2_IMB_MASK 0x2000u

#define	CAN_ESR2_IMB_SHIFT 13

#define	CAN_ESR2_VPS_MASK 0x4000u

#define	CAN_ESR2_VPS_SHIFT 14

#define	CAN_ESR2_LPTM_MASK 0x7F0000u

#define	CAN_ESR2_LPTM_SHIFT 16

#define	CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)

#define	CAN_CRCR_TXCRC_MASK 0x7FFFu

#define	CAN_CRCR_TXCRC_SHIFT 0

#define	CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)

#define	CAN_CRCR_MBCRC_MASK 0x7F0000u

#define	CAN_CRCR_MBCRC_SHIFT 16

#define	CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)

#define	CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu

#define	CAN_RXFGMASK_FGM_SHIFT 0

#define	CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)

#define	CAN_RXFIR_IDHIT_MASK 0x1FFu

#define	CAN_RXFIR_IDHIT_SHIFT 0

#define	CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)

#define	CAN_CS_TIME_STAMP_MASK 0xFFFFu

#define	CAN_CS_TIME_STAMP_SHIFT 0

#define	CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)

#define	CAN_CS_DLC_MASK 0xF0000u

#define	CAN_CS_DLC_SHIFT 16

#define	CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)

#define	CAN_CS_RTR_MASK 0x100000u

#define	CAN_CS_RTR_SHIFT 20

#define	CAN_CS_IDE_MASK 0x200000u

#define	CAN_CS_IDE_SHIFT 21

#define	CAN_CS_SRR_MASK 0x400000u

#define	CAN_CS_SRR_SHIFT 22

#define	CAN_CS_CODE_MASK 0xF000000u

#define	CAN_CS_CODE_SHIFT 24

#define	CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)

#define	CAN_ID_EXT_MASK 0x3FFFFu

#define	CAN_ID_EXT_SHIFT 0

#define	CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)

#define	CAN_ID_STD_MASK 0x1FFC0000u

#define	CAN_ID_STD_SHIFT 18

#define	CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)

#define	CAN_ID_PRIO_MASK 0xE0000000u

#define	CAN_ID_PRIO_SHIFT 29

#define	CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)

#define	CAN_WORD0_DATA_BYTE_3_MASK 0xFFu

#define	CAN_WORD0_DATA_BYTE_3_SHIFT 0

#define	CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)

#define	CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u

#define	CAN_WORD0_DATA_BYTE_2_SHIFT 8

#define	CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)

#define	CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u

#define	CAN_WORD0_DATA_BYTE_1_SHIFT 16

#define	CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)

#define	CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u

#define	CAN_WORD0_DATA_BYTE_0_SHIFT 24

#define	CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)

#define	CAN_WORD1_DATA_BYTE_7_MASK 0xFFu

#define	CAN_WORD1_DATA_BYTE_7_SHIFT 0

#define	CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)

#define	CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u

#define	CAN_WORD1_DATA_BYTE_6_SHIFT 8

#define	CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)

#define	CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u

#define	CAN_WORD1_DATA_BYTE_5_SHIFT 16

#define	CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)

#define	CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u

#define	CAN_WORD1_DATA_BYTE_4_SHIFT 24

#define	CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)

#define	CAN_RXIMR_MI_MASK 0xFFFFFFFFu

#define	CAN_RXIMR_MI_SHIFT 0

#define	CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)

#define	CAN0_BASE_PTR ((CAN_MemMapPtr)0x40024000u)

#define	CAN1_BASE_PTR ((CAN_MemMapPtr)0x400A4000u)

#define	CAN_BASE_PTRS { CAN0_BASE_PTR, CAN1_BASE_PTR }

#define	CAN0_MCR CAN_MCR_REG(CAN0_BASE_PTR)

#define	CAN0_CTRL1 CAN_CTRL1_REG(CAN0_BASE_PTR)

#define	CAN0_TIMER CAN_TIMER_REG(CAN0_BASE_PTR)

#define	CAN0_RXMGMASK CAN_RXMGMASK_REG(CAN0_BASE_PTR)

#define	CAN0_RX14MASK CAN_RX14MASK_REG(CAN0_BASE_PTR)

#define	CAN0_RX15MASK CAN_RX15MASK_REG(CAN0_BASE_PTR)

#define	CAN0_ECR CAN_ECR_REG(CAN0_BASE_PTR)

#define	CAN0_ESR1 CAN_ESR1_REG(CAN0_BASE_PTR)

#define	CAN0_IMASK2 CAN_IMASK2_REG(CAN0_BASE_PTR)

#define	CAN0_IMASK1 CAN_IMASK1_REG(CAN0_BASE_PTR)

#define	CAN0_IFLAG2 CAN_IFLAG2_REG(CAN0_BASE_PTR)

#define	CAN0_IFLAG1 CAN_IFLAG1_REG(CAN0_BASE_PTR)

#define	CAN0_CTRL2 CAN_CTRL2_REG(CAN0_BASE_PTR)

#define	CAN0_ESR2 CAN_ESR2_REG(CAN0_BASE_PTR)

#define	CAN0_CRCR CAN_CRCR_REG(CAN0_BASE_PTR)

#define	CAN0_RXFGMASK CAN_RXFGMASK_REG(CAN0_BASE_PTR)

#define	CAN0_RXFIR CAN_RXFIR_REG(CAN0_BASE_PTR)

#define	CAN0_CS0 CAN_CS_REG(CAN0_BASE_PTR,0)

#define	CAN0_ID0 CAN_ID_REG(CAN0_BASE_PTR,0)

#define	CAN0_WORD00 CAN_WORD0_REG(CAN0_BASE_PTR,0)

#define	CAN0_WORD10 CAN_WORD1_REG(CAN0_BASE_PTR,0)

#define	CAN0_CS1 CAN_CS_REG(CAN0_BASE_PTR,1)

#define	CAN0_ID1 CAN_ID_REG(CAN0_BASE_PTR,1)

#define	CAN0_WORD01 CAN_WORD0_REG(CAN0_BASE_PTR,1)

#define	CAN0_WORD11 CAN_WORD1_REG(CAN0_BASE_PTR,1)

#define	CAN0_CS2 CAN_CS_REG(CAN0_BASE_PTR,2)

#define	CAN0_ID2 CAN_ID_REG(CAN0_BASE_PTR,2)

#define	CAN0_WORD02 CAN_WORD0_REG(CAN0_BASE_PTR,2)

#define	CAN0_WORD12 CAN_WORD1_REG(CAN0_BASE_PTR,2)

#define	CAN0_CS3 CAN_CS_REG(CAN0_BASE_PTR,3)

#define	CAN0_ID3 CAN_ID_REG(CAN0_BASE_PTR,3)

#define	CAN0_WORD03 CAN_WORD0_REG(CAN0_BASE_PTR,3)

#define	CAN0_WORD13 CAN_WORD1_REG(CAN0_BASE_PTR,3)

#define	CAN0_CS4 CAN_CS_REG(CAN0_BASE_PTR,4)

#define	CAN0_ID4 CAN_ID_REG(CAN0_BASE_PTR,4)

#define	CAN0_WORD04 CAN_WORD0_REG(CAN0_BASE_PTR,4)

#define	CAN0_WORD14 CAN_WORD1_REG(CAN0_BASE_PTR,4)

#define	CAN0_CS5 CAN_CS_REG(CAN0_BASE_PTR,5)

#define	CAN0_ID5 CAN_ID_REG(CAN0_BASE_PTR,5)

#define	CAN0_WORD05 CAN_WORD0_REG(CAN0_BASE_PTR,5)

#define	CAN0_WORD15 CAN_WORD1_REG(CAN0_BASE_PTR,5)

#define	CAN0_CS6 CAN_CS_REG(CAN0_BASE_PTR,6)

#define	CAN0_ID6 CAN_ID_REG(CAN0_BASE_PTR,6)

#define	CAN0_WORD06 CAN_WORD0_REG(CAN0_BASE_PTR,6)

#define	CAN0_WORD16 CAN_WORD1_REG(CAN0_BASE_PTR,6)

#define	CAN0_CS7 CAN_CS_REG(CAN0_BASE_PTR,7)

#define	CAN0_ID7 CAN_ID_REG(CAN0_BASE_PTR,7)

#define	CAN0_WORD07 CAN_WORD0_REG(CAN0_BASE_PTR,7)

#define	CAN0_WORD17 CAN_WORD1_REG(CAN0_BASE_PTR,7)

#define	CAN0_CS8 CAN_CS_REG(CAN0_BASE_PTR,8)

#define	CAN0_ID8 CAN_ID_REG(CAN0_BASE_PTR,8)

#define	CAN0_WORD08 CAN_WORD0_REG(CAN0_BASE_PTR,8)

#define	CAN0_WORD18 CAN_WORD1_REG(CAN0_BASE_PTR,8)

#define	CAN0_CS9 CAN_CS_REG(CAN0_BASE_PTR,9)

#define	CAN0_ID9 CAN_ID_REG(CAN0_BASE_PTR,9)

#define	CAN0_WORD09 CAN_WORD0_REG(CAN0_BASE_PTR,9)

#define	CAN0_WORD19 CAN_WORD1_REG(CAN0_BASE_PTR,9)

#define	CAN0_CS10 CAN_CS_REG(CAN0_BASE_PTR,10)

#define	CAN0_ID10 CAN_ID_REG(CAN0_BASE_PTR,10)

#define	CAN0_WORD010 CAN_WORD0_REG(CAN0_BASE_PTR,10)

#define	CAN0_WORD110 CAN_WORD1_REG(CAN0_BASE_PTR,10)

#define	CAN0_CS11 CAN_CS_REG(CAN0_BASE_PTR,11)

#define	CAN0_ID11 CAN_ID_REG(CAN0_BASE_PTR,11)

#define	CAN0_WORD011 CAN_WORD0_REG(CAN0_BASE_PTR,11)

#define	CAN0_WORD111 CAN_WORD1_REG(CAN0_BASE_PTR,11)

#define	CAN0_CS12 CAN_CS_REG(CAN0_BASE_PTR,12)

#define	CAN0_ID12 CAN_ID_REG(CAN0_BASE_PTR,12)

#define	CAN0_WORD012 CAN_WORD0_REG(CAN0_BASE_PTR,12)

#define	CAN0_WORD112 CAN_WORD1_REG(CAN0_BASE_PTR,12)

#define	CAN0_CS13 CAN_CS_REG(CAN0_BASE_PTR,13)

#define	CAN0_ID13 CAN_ID_REG(CAN0_BASE_PTR,13)

#define	CAN0_WORD013 CAN_WORD0_REG(CAN0_BASE_PTR,13)

#define	CAN0_WORD113 CAN_WORD1_REG(CAN0_BASE_PTR,13)

#define	CAN0_CS14 CAN_CS_REG(CAN0_BASE_PTR,14)

#define	CAN0_ID14 CAN_ID_REG(CAN0_BASE_PTR,14)

#define	CAN0_WORD014 CAN_WORD0_REG(CAN0_BASE_PTR,14)

#define	CAN0_WORD114 CAN_WORD1_REG(CAN0_BASE_PTR,14)

#define	CAN0_CS15 CAN_CS_REG(CAN0_BASE_PTR,15)

#define	CAN0_ID15 CAN_ID_REG(CAN0_BASE_PTR,15)

#define	CAN0_WORD015 CAN_WORD0_REG(CAN0_BASE_PTR,15)

#define	CAN0_WORD115 CAN_WORD1_REG(CAN0_BASE_PTR,15)

#define	CAN0_RXIMR0 CAN_RXIMR_REG(CAN0_BASE_PTR,0)

#define	CAN0_RXIMR1 CAN_RXIMR_REG(CAN0_BASE_PTR,1)

#define	CAN0_RXIMR2 CAN_RXIMR_REG(CAN0_BASE_PTR,2)

#define	CAN0_RXIMR3 CAN_RXIMR_REG(CAN0_BASE_PTR,3)

#define	CAN0_RXIMR4 CAN_RXIMR_REG(CAN0_BASE_PTR,4)

#define	CAN0_RXIMR5 CAN_RXIMR_REG(CAN0_BASE_PTR,5)

#define	CAN0_RXIMR6 CAN_RXIMR_REG(CAN0_BASE_PTR,6)

#define	CAN0_RXIMR7 CAN_RXIMR_REG(CAN0_BASE_PTR,7)

#define	CAN0_RXIMR8 CAN_RXIMR_REG(CAN0_BASE_PTR,8)

#define	CAN0_RXIMR9 CAN_RXIMR_REG(CAN0_BASE_PTR,9)

#define	CAN0_RXIMR10 CAN_RXIMR_REG(CAN0_BASE_PTR,10)

#define	CAN0_RXIMR11 CAN_RXIMR_REG(CAN0_BASE_PTR,11)

#define	CAN0_RXIMR12 CAN_RXIMR_REG(CAN0_BASE_PTR,12)

#define	CAN0_RXIMR13 CAN_RXIMR_REG(CAN0_BASE_PTR,13)

#define	CAN0_RXIMR14 CAN_RXIMR_REG(CAN0_BASE_PTR,14)

#define	CAN0_RXIMR15 CAN_RXIMR_REG(CAN0_BASE_PTR,15)

#define	CAN1_MCR CAN_MCR_REG(CAN1_BASE_PTR)

#define	CAN1_CTRL1 CAN_CTRL1_REG(CAN1_BASE_PTR)

#define	CAN1_TIMER CAN_TIMER_REG(CAN1_BASE_PTR)

#define	CAN1_RXMGMASK CAN_RXMGMASK_REG(CAN1_BASE_PTR)

#define	CAN1_RX14MASK CAN_RX14MASK_REG(CAN1_BASE_PTR)

#define	CAN1_RX15MASK CAN_RX15MASK_REG(CAN1_BASE_PTR)

#define	CAN1_ECR CAN_ECR_REG(CAN1_BASE_PTR)

#define	CAN1_ESR1 CAN_ESR1_REG(CAN1_BASE_PTR)

#define	CAN1_IMASK2 CAN_IMASK2_REG(CAN1_BASE_PTR)

#define	CAN1_IMASK1 CAN_IMASK1_REG(CAN1_BASE_PTR)

#define	CAN1_IFLAG2 CAN_IFLAG2_REG(CAN1_BASE_PTR)

#define	CAN1_IFLAG1 CAN_IFLAG1_REG(CAN1_BASE_PTR)

#define	CAN1_CTRL2 CAN_CTRL2_REG(CAN1_BASE_PTR)

#define	CAN1_ESR2 CAN_ESR2_REG(CAN1_BASE_PTR)

#define	CAN1_CRCR CAN_CRCR_REG(CAN1_BASE_PTR)

#define	CAN1_RXFGMASK CAN_RXFGMASK_REG(CAN1_BASE_PTR)

#define	CAN1_RXFIR CAN_RXFIR_REG(CAN1_BASE_PTR)

#define	CAN1_CS0 CAN_CS_REG(CAN1_BASE_PTR,0)

#define	CAN1_ID0 CAN_ID_REG(CAN1_BASE_PTR,0)

#define	CAN1_WORD00 CAN_WORD0_REG(CAN1_BASE_PTR,0)

#define	CAN1_WORD10 CAN_WORD1_REG(CAN1_BASE_PTR,0)

#define	CAN1_CS1 CAN_CS_REG(CAN1_BASE_PTR,1)

#define	CAN1_ID1 CAN_ID_REG(CAN1_BASE_PTR,1)

#define	CAN1_WORD01 CAN_WORD0_REG(CAN1_BASE_PTR,1)

#define	CAN1_WORD11 CAN_WORD1_REG(CAN1_BASE_PTR,1)

#define	CAN1_CS2 CAN_CS_REG(CAN1_BASE_PTR,2)

#define	CAN1_ID2 CAN_ID_REG(CAN1_BASE_PTR,2)

#define	CAN1_WORD02 CAN_WORD0_REG(CAN1_BASE_PTR,2)

#define	CAN1_WORD12 CAN_WORD1_REG(CAN1_BASE_PTR,2)

#define	CAN1_CS3 CAN_CS_REG(CAN1_BASE_PTR,3)

#define	CAN1_ID3 CAN_ID_REG(CAN1_BASE_PTR,3)

#define	CAN1_WORD03 CAN_WORD0_REG(CAN1_BASE_PTR,3)

#define	CAN1_WORD13 CAN_WORD1_REG(CAN1_BASE_PTR,3)

#define	CAN1_CS4 CAN_CS_REG(CAN1_BASE_PTR,4)

#define	CAN1_ID4 CAN_ID_REG(CAN1_BASE_PTR,4)

#define	CAN1_WORD04 CAN_WORD0_REG(CAN1_BASE_PTR,4)

#define	CAN1_WORD14 CAN_WORD1_REG(CAN1_BASE_PTR,4)

#define	CAN1_CS5 CAN_CS_REG(CAN1_BASE_PTR,5)

#define	CAN1_ID5 CAN_ID_REG(CAN1_BASE_PTR,5)

#define	CAN1_WORD05 CAN_WORD0_REG(CAN1_BASE_PTR,5)

#define	CAN1_WORD15 CAN_WORD1_REG(CAN1_BASE_PTR,5)

#define	CAN1_CS6 CAN_CS_REG(CAN1_BASE_PTR,6)

#define	CAN1_ID6 CAN_ID_REG(CAN1_BASE_PTR,6)

#define	CAN1_WORD06 CAN_WORD0_REG(CAN1_BASE_PTR,6)

#define	CAN1_WORD16 CAN_WORD1_REG(CAN1_BASE_PTR,6)

#define	CAN1_CS7 CAN_CS_REG(CAN1_BASE_PTR,7)

#define	CAN1_ID7 CAN_ID_REG(CAN1_BASE_PTR,7)

#define	CAN1_WORD07 CAN_WORD0_REG(CAN1_BASE_PTR,7)

#define	CAN1_WORD17 CAN_WORD1_REG(CAN1_BASE_PTR,7)

#define	CAN1_CS8 CAN_CS_REG(CAN1_BASE_PTR,8)

#define	CAN1_ID8 CAN_ID_REG(CAN1_BASE_PTR,8)

#define	CAN1_WORD08 CAN_WORD0_REG(CAN1_BASE_PTR,8)

#define	CAN1_WORD18 CAN_WORD1_REG(CAN1_BASE_PTR,8)

#define	CAN1_CS9 CAN_CS_REG(CAN1_BASE_PTR,9)

#define	CAN1_ID9 CAN_ID_REG(CAN1_BASE_PTR,9)

#define	CAN1_WORD09 CAN_WORD0_REG(CAN1_BASE_PTR,9)

#define	CAN1_WORD19 CAN_WORD1_REG(CAN1_BASE_PTR,9)

#define	CAN1_CS10 CAN_CS_REG(CAN1_BASE_PTR,10)

#define	CAN1_ID10 CAN_ID_REG(CAN1_BASE_PTR,10)

#define	CAN1_WORD010 CAN_WORD0_REG(CAN1_BASE_PTR,10)

#define	CAN1_WORD110 CAN_WORD1_REG(CAN1_BASE_PTR,10)

#define	CAN1_CS11 CAN_CS_REG(CAN1_BASE_PTR,11)

#define	CAN1_ID11 CAN_ID_REG(CAN1_BASE_PTR,11)

#define	CAN1_WORD011 CAN_WORD0_REG(CAN1_BASE_PTR,11)

#define	CAN1_WORD111 CAN_WORD1_REG(CAN1_BASE_PTR,11)

#define	CAN1_CS12 CAN_CS_REG(CAN1_BASE_PTR,12)

#define	CAN1_ID12 CAN_ID_REG(CAN1_BASE_PTR,12)

#define	CAN1_WORD012 CAN_WORD0_REG(CAN1_BASE_PTR,12)

#define	CAN1_WORD112 CAN_WORD1_REG(CAN1_BASE_PTR,12)

#define	CAN1_CS13 CAN_CS_REG(CAN1_BASE_PTR,13)

#define	CAN1_ID13 CAN_ID_REG(CAN1_BASE_PTR,13)

#define	CAN1_WORD013 CAN_WORD0_REG(CAN1_BASE_PTR,13)

#define	CAN1_WORD113 CAN_WORD1_REG(CAN1_BASE_PTR,13)

#define	CAN1_CS14 CAN_CS_REG(CAN1_BASE_PTR,14)

#define	CAN1_ID14 CAN_ID_REG(CAN1_BASE_PTR,14)

#define	CAN1_WORD014 CAN_WORD0_REG(CAN1_BASE_PTR,14)

#define	CAN1_WORD114 CAN_WORD1_REG(CAN1_BASE_PTR,14)

#define	CAN1_CS15 CAN_CS_REG(CAN1_BASE_PTR,15)

#define	CAN1_ID15 CAN_ID_REG(CAN1_BASE_PTR,15)

#define	CAN1_WORD015 CAN_WORD0_REG(CAN1_BASE_PTR,15)

#define	CAN1_WORD115 CAN_WORD1_REG(CAN1_BASE_PTR,15)

#define	CAN1_RXIMR0 CAN_RXIMR_REG(CAN1_BASE_PTR,0)

#define	CAN1_RXIMR1 CAN_RXIMR_REG(CAN1_BASE_PTR,1)

#define	CAN1_RXIMR2 CAN_RXIMR_REG(CAN1_BASE_PTR,2)

#define	CAN1_RXIMR3 CAN_RXIMR_REG(CAN1_BASE_PTR,3)

#define	CAN1_RXIMR4 CAN_RXIMR_REG(CAN1_BASE_PTR,4)

#define	CAN1_RXIMR5 CAN_RXIMR_REG(CAN1_BASE_PTR,5)

#define	CAN1_RXIMR6 CAN_RXIMR_REG(CAN1_BASE_PTR,6)

#define	CAN1_RXIMR7 CAN_RXIMR_REG(CAN1_BASE_PTR,7)

#define	CAN1_RXIMR8 CAN_RXIMR_REG(CAN1_BASE_PTR,8)

#define	CAN1_RXIMR9 CAN_RXIMR_REG(CAN1_BASE_PTR,9)

#define	CAN1_RXIMR10 CAN_RXIMR_REG(CAN1_BASE_PTR,10)

#define	CAN1_RXIMR11 CAN_RXIMR_REG(CAN1_BASE_PTR,11)

#define	CAN1_RXIMR12 CAN_RXIMR_REG(CAN1_BASE_PTR,12)

#define	CAN1_RXIMR13 CAN_RXIMR_REG(CAN1_BASE_PTR,13)

#define	CAN1_RXIMR14 CAN_RXIMR_REG(CAN1_BASE_PTR,14)

#define	CAN1_RXIMR15 CAN_RXIMR_REG(CAN1_BASE_PTR,15)

#define	CAN0_CS(index) CAN_CS_REG(CAN0_BASE_PTR,index)

#define	CAN1_CS(index) CAN_CS_REG(CAN1_BASE_PTR,index)

#define	CAN0_ID(index) CAN_ID_REG(CAN0_BASE_PTR,index)

#define	CAN1_ID(index) CAN_ID_REG(CAN1_BASE_PTR,index)

#define	CAN0_WORD0(index) CAN_WORD0_REG(CAN0_BASE_PTR,index)

#define	CAN1_WORD0(index) CAN_WORD0_REG(CAN1_BASE_PTR,index)

#define	CAN0_WORD1(index) CAN_WORD1_REG(CAN0_BASE_PTR,index)

#define	CAN1_WORD1(index) CAN_WORD1_REG(CAN1_BASE_PTR,index)

#define	CAN0_RXIMR(index) CAN_RXIMR_REG(CAN0_BASE_PTR,index)

#define	CAN1_RXIMR(index) CAN_RXIMR_REG(CAN1_BASE_PTR,index)

#define	CAU_DIRECT_REG(base, index) ((base)->DIRECT[index])

#define	CAU_LDR_CASR_REG(base) ((base)->LDR_CASR)

#define	CAU_LDR_CAA_REG(base) ((base)->LDR_CAA)

#define	CAU_LDR_CA_REG(base, index) ((base)->LDR_CA[index])

#define	CAU_STR_CASR_REG(base) ((base)->STR_CASR)

#define	CAU_STR_CAA_REG(base) ((base)->STR_CAA)

#define	CAU_STR_CA_REG(base, index) ((base)->STR_CA[index])

#define	CAU_ADR_CASR_REG(base) ((base)->ADR_CASR)

#define	CAU_ADR_CAA_REG(base) ((base)->ADR_CAA)

#define	CAU_ADR_CA_REG(base, index) ((base)->ADR_CA[index])

#define	CAU_RADR_CASR_REG(base) ((base)->RADR_CASR)

#define	CAU_RADR_CAA_REG(base) ((base)->RADR_CAA)

#define	CAU_RADR_CA_REG(base, index) ((base)->RADR_CA[index])

#define	CAU_XOR_CASR_REG(base) ((base)->XOR_CASR)

#define	CAU_XOR_CAA_REG(base) ((base)->XOR_CAA)

#define	CAU_XOR_CA_REG(base, index) ((base)->XOR_CA[index])

#define	CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR)

#define	CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA)

#define	CAU_ROTL_CA_REG(base, index) ((base)->ROTL_CA[index])

#define	CAU_AESC_CASR_REG(base) ((base)->AESC_CASR)

#define	CAU_AESC_CAA_REG(base) ((base)->AESC_CAA)

#define	CAU_AESC_CA_REG(base, index) ((base)->AESC_CA[index])

#define	CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR)

#define	CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA)

#define	CAU_AESIC_CA_REG(base, index) ((base)->AESIC_CA[index])

#define	CAU_DIRECT_CAU_DIRECT0_MASK 0xFFFFFFFFu

#define	CAU_DIRECT_CAU_DIRECT0_SHIFT 0

#define	CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT0_SHIFT))&CAU_DIRECT_CAU_DIRECT0_MASK)

#define	CAU_DIRECT_CAU_DIRECT1_MASK 0xFFFFFFFFu

#define	CAU_DIRECT_CAU_DIRECT1_SHIFT 0

#define	CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT1_SHIFT))&CAU_DIRECT_CAU_DIRECT1_MASK)

#define	CAU_DIRECT_CAU_DIRECT2_MASK 0xFFFFFFFFu

#define	CAU_DIRECT_CAU_DIRECT2_SHIFT 0

#define	CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT2_SHIFT))&CAU_DIRECT_CAU_DIRECT2_MASK)

#define	CAU_DIRECT_CAU_DIRECT3_MASK 0xFFFFFFFFu

#define	CAU_DIRECT_CAU_DIRECT3_SHIFT 0

#define	CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT3_SHIFT))&CAU_DIRECT_CAU_DIRECT3_MASK)

#define	CAU_DIRECT_CAU_DIRECT4_MASK 0xFFFFFFFFu

#define	CAU_DIRECT_CAU_DIRECT4_SHIFT 0

#define	CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT4_SHIFT))&CAU_DIRECT_CAU_DIRECT4_MASK)

#define	CAU_DIRECT_CAU_DIRECT5_MASK 0xFFFFFFFFu

#define	CAU_DIRECT_CAU_DIRECT5_SHIFT 0

#define	CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT5_SHIFT))&CAU_DIRECT_CAU_DIRECT5_MASK)

#define	CAU_DIRECT_CAU_DIRECT6_MASK 0xFFFFFFFFu

#define	CAU_DIRECT_CAU_DIRECT6_SHIFT 0

#define	CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT6_SHIFT))&CAU_DIRECT_CAU_DIRECT6_MASK)

#define	CAU_DIRECT_CAU_DIRECT7_MASK 0xFFFFFFFFu

#define	CAU_DIRECT_CAU_DIRECT7_SHIFT 0

#define	CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT7_SHIFT))&CAU_DIRECT_CAU_DIRECT7_MASK)

#define	CAU_DIRECT_CAU_DIRECT8_MASK 0xFFFFFFFFu

#define	CAU_DIRECT_CAU_DIRECT8_SHIFT 0

#define	CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT8_SHIFT))&CAU_DIRECT_CAU_DIRECT8_MASK)

#define	CAU_DIRECT_CAU_DIRECT9_MASK 0xFFFFFFFFu

#define	CAU_DIRECT_CAU_DIRECT9_SHIFT 0

#define	CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT9_SHIFT))&CAU_DIRECT_CAU_DIRECT9_MASK)

#define	CAU_DIRECT_CAU_DIRECT10_MASK 0xFFFFFFFFu

#define	CAU_DIRECT_CAU_DIRECT10_SHIFT 0

#define	CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT10_SHIFT))&CAU_DIRECT_CAU_DIRECT10_MASK)

#define	CAU_DIRECT_CAU_DIRECT11_MASK 0xFFFFFFFFu

#define	CAU_DIRECT_CAU_DIRECT11_SHIFT 0

#define	CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT11_SHIFT))&CAU_DIRECT_CAU_DIRECT11_MASK)

#define	CAU_DIRECT_CAU_DIRECT12_MASK 0xFFFFFFFFu

#define	CAU_DIRECT_CAU_DIRECT12_SHIFT 0

#define	CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT12_SHIFT))&CAU_DIRECT_CAU_DIRECT12_MASK)

#define	CAU_DIRECT_CAU_DIRECT13_MASK 0xFFFFFFFFu

#define	CAU_DIRECT_CAU_DIRECT13_SHIFT 0

#define	CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT13_SHIFT))&CAU_DIRECT_CAU_DIRECT13_MASK)

#define	CAU_DIRECT_CAU_DIRECT14_MASK 0xFFFFFFFFu

#define	CAU_DIRECT_CAU_DIRECT14_SHIFT 0

#define	CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT14_SHIFT))&CAU_DIRECT_CAU_DIRECT14_MASK)

#define	CAU_DIRECT_CAU_DIRECT15_MASK 0xFFFFFFFFu

#define	CAU_DIRECT_CAU_DIRECT15_SHIFT 0

#define	CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT15_SHIFT))&CAU_DIRECT_CAU_DIRECT15_MASK)

#define	CAU_LDR_CASR_IC_MASK 0x1u

#define	CAU_LDR_CASR_IC_SHIFT 0

#define	CAU_LDR_CASR_DPE_MASK 0x2u

#define	CAU_LDR_CASR_DPE_SHIFT 1

#define	CAU_LDR_CASR_VER_MASK 0xF0000000u

#define	CAU_LDR_CASR_VER_SHIFT 28

#define	CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)

#define	CAU_LDR_CAA_ACC_MASK 0xFFFFFFFFu

#define	CAU_LDR_CAA_ACC_SHIFT 0

#define	CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CAA_ACC_SHIFT))&CAU_LDR_CAA_ACC_MASK)

#define	CAU_LDR_CA_CA0_MASK 0xFFFFFFFFu

#define	CAU_LDR_CA_CA0_SHIFT 0

#define	CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA0_SHIFT))&CAU_LDR_CA_CA0_MASK)

#define	CAU_LDR_CA_CA1_MASK 0xFFFFFFFFu

#define	CAU_LDR_CA_CA1_SHIFT 0

#define	CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA1_SHIFT))&CAU_LDR_CA_CA1_MASK)

#define	CAU_LDR_CA_CA2_MASK 0xFFFFFFFFu

#define	CAU_LDR_CA_CA2_SHIFT 0

#define	CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA2_SHIFT))&CAU_LDR_CA_CA2_MASK)

#define	CAU_LDR_CA_CA3_MASK 0xFFFFFFFFu

#define	CAU_LDR_CA_CA3_SHIFT 0

#define	CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA3_SHIFT))&CAU_LDR_CA_CA3_MASK)

#define	CAU_LDR_CA_CA4_MASK 0xFFFFFFFFu

#define	CAU_LDR_CA_CA4_SHIFT 0

#define	CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA4_SHIFT))&CAU_LDR_CA_CA4_MASK)

#define	CAU_LDR_CA_CA5_MASK 0xFFFFFFFFu

#define	CAU_LDR_CA_CA5_SHIFT 0

#define	CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA5_SHIFT))&CAU_LDR_CA_CA5_MASK)

#define	CAU_LDR_CA_CA6_MASK 0xFFFFFFFFu

#define	CAU_LDR_CA_CA6_SHIFT 0

#define	CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA6_SHIFT))&CAU_LDR_CA_CA6_MASK)

#define	CAU_LDR_CA_CA7_MASK 0xFFFFFFFFu

#define	CAU_LDR_CA_CA7_SHIFT 0

#define	CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA7_SHIFT))&CAU_LDR_CA_CA7_MASK)

#define	CAU_LDR_CA_CA8_MASK 0xFFFFFFFFu

#define	CAU_LDR_CA_CA8_SHIFT 0

#define	CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA8_SHIFT))&CAU_LDR_CA_CA8_MASK)

#define	CAU_STR_CASR_IC_MASK 0x1u

#define	CAU_STR_CASR_IC_SHIFT 0

#define	CAU_STR_CASR_DPE_MASK 0x2u

#define	CAU_STR_CASR_DPE_SHIFT 1

#define	CAU_STR_CASR_VER_MASK 0xF0000000u

#define	CAU_STR_CASR_VER_SHIFT 28

#define	CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)

#define	CAU_STR_CAA_ACC_MASK 0xFFFFFFFFu

#define	CAU_STR_CAA_ACC_SHIFT 0

#define	CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CAA_ACC_SHIFT))&CAU_STR_CAA_ACC_MASK)

#define	CAU_STR_CA_CA0_MASK 0xFFFFFFFFu

#define	CAU_STR_CA_CA0_SHIFT 0

#define	CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA0_SHIFT))&CAU_STR_CA_CA0_MASK)

#define	CAU_STR_CA_CA1_MASK 0xFFFFFFFFu

#define	CAU_STR_CA_CA1_SHIFT 0

#define	CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA1_SHIFT))&CAU_STR_CA_CA1_MASK)

#define	CAU_STR_CA_CA2_MASK 0xFFFFFFFFu

#define	CAU_STR_CA_CA2_SHIFT 0

#define	CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA2_SHIFT))&CAU_STR_CA_CA2_MASK)

#define	CAU_STR_CA_CA3_MASK 0xFFFFFFFFu

#define	CAU_STR_CA_CA3_SHIFT 0

#define	CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA3_SHIFT))&CAU_STR_CA_CA3_MASK)

#define	CAU_STR_CA_CA4_MASK 0xFFFFFFFFu

#define	CAU_STR_CA_CA4_SHIFT 0

#define	CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA4_SHIFT))&CAU_STR_CA_CA4_MASK)

#define	CAU_STR_CA_CA5_MASK 0xFFFFFFFFu

#define	CAU_STR_CA_CA5_SHIFT 0

#define	CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA5_SHIFT))&CAU_STR_CA_CA5_MASK)

#define	CAU_STR_CA_CA6_MASK 0xFFFFFFFFu

#define	CAU_STR_CA_CA6_SHIFT 0

#define	CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA6_SHIFT))&CAU_STR_CA_CA6_MASK)

#define	CAU_STR_CA_CA7_MASK 0xFFFFFFFFu

#define	CAU_STR_CA_CA7_SHIFT 0

#define	CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA7_SHIFT))&CAU_STR_CA_CA7_MASK)

#define	CAU_STR_CA_CA8_MASK 0xFFFFFFFFu

#define	CAU_STR_CA_CA8_SHIFT 0

#define	CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA8_SHIFT))&CAU_STR_CA_CA8_MASK)

#define	CAU_ADR_CASR_IC_MASK 0x1u

#define	CAU_ADR_CASR_IC_SHIFT 0

#define	CAU_ADR_CASR_DPE_MASK 0x2u

#define	CAU_ADR_CASR_DPE_SHIFT 1

#define	CAU_ADR_CASR_VER_MASK 0xF0000000u

#define	CAU_ADR_CASR_VER_SHIFT 28

#define	CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)

#define	CAU_ADR_CAA_ACC_MASK 0xFFFFFFFFu

#define	CAU_ADR_CAA_ACC_SHIFT 0

#define	CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CAA_ACC_SHIFT))&CAU_ADR_CAA_ACC_MASK)

#define	CAU_ADR_CA_CA0_MASK 0xFFFFFFFFu

#define	CAU_ADR_CA_CA0_SHIFT 0

#define	CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA0_SHIFT))&CAU_ADR_CA_CA0_MASK)

#define	CAU_ADR_CA_CA1_MASK 0xFFFFFFFFu

#define	CAU_ADR_CA_CA1_SHIFT 0

#define	CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA1_SHIFT))&CAU_ADR_CA_CA1_MASK)

#define	CAU_ADR_CA_CA2_MASK 0xFFFFFFFFu

#define	CAU_ADR_CA_CA2_SHIFT 0

#define	CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA2_SHIFT))&CAU_ADR_CA_CA2_MASK)

#define	CAU_ADR_CA_CA3_MASK 0xFFFFFFFFu

#define	CAU_ADR_CA_CA3_SHIFT 0

#define	CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA3_SHIFT))&CAU_ADR_CA_CA3_MASK)

#define	CAU_ADR_CA_CA4_MASK 0xFFFFFFFFu

#define	CAU_ADR_CA_CA4_SHIFT 0

#define	CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA4_SHIFT))&CAU_ADR_CA_CA4_MASK)

#define	CAU_ADR_CA_CA5_MASK 0xFFFFFFFFu

#define	CAU_ADR_CA_CA5_SHIFT 0

#define	CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA5_SHIFT))&CAU_ADR_CA_CA5_MASK)

#define	CAU_ADR_CA_CA6_MASK 0xFFFFFFFFu

#define	CAU_ADR_CA_CA6_SHIFT 0

#define	CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA6_SHIFT))&CAU_ADR_CA_CA6_MASK)

#define	CAU_ADR_CA_CA7_MASK 0xFFFFFFFFu

#define	CAU_ADR_CA_CA7_SHIFT 0

#define	CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA7_SHIFT))&CAU_ADR_CA_CA7_MASK)

#define	CAU_ADR_CA_CA8_MASK 0xFFFFFFFFu

#define	CAU_ADR_CA_CA8_SHIFT 0

#define	CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA8_SHIFT))&CAU_ADR_CA_CA8_MASK)

#define	CAU_RADR_CASR_IC_MASK 0x1u

#define	CAU_RADR_CASR_IC_SHIFT 0

#define	CAU_RADR_CASR_DPE_MASK 0x2u

#define	CAU_RADR_CASR_DPE_SHIFT 1

#define	CAU_RADR_CASR_VER_MASK 0xF0000000u

#define	CAU_RADR_CASR_VER_SHIFT 28

#define	CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)

#define	CAU_RADR_CAA_ACC_MASK 0xFFFFFFFFu

#define	CAU_RADR_CAA_ACC_SHIFT 0

#define	CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CAA_ACC_SHIFT))&CAU_RADR_CAA_ACC_MASK)

#define	CAU_RADR_CA_CA0_MASK 0xFFFFFFFFu

#define	CAU_RADR_CA_CA0_SHIFT 0

#define	CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA0_SHIFT))&CAU_RADR_CA_CA0_MASK)

#define	CAU_RADR_CA_CA1_MASK 0xFFFFFFFFu

#define	CAU_RADR_CA_CA1_SHIFT 0

#define	CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA1_SHIFT))&CAU_RADR_CA_CA1_MASK)

#define	CAU_RADR_CA_CA2_MASK 0xFFFFFFFFu

#define	CAU_RADR_CA_CA2_SHIFT 0

#define	CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA2_SHIFT))&CAU_RADR_CA_CA2_MASK)

#define	CAU_RADR_CA_CA3_MASK 0xFFFFFFFFu

#define	CAU_RADR_CA_CA3_SHIFT 0

#define	CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA3_SHIFT))&CAU_RADR_CA_CA3_MASK)

#define	CAU_RADR_CA_CA4_MASK 0xFFFFFFFFu

#define	CAU_RADR_CA_CA4_SHIFT 0

#define	CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA4_SHIFT))&CAU_RADR_CA_CA4_MASK)

#define	CAU_RADR_CA_CA5_MASK 0xFFFFFFFFu

#define	CAU_RADR_CA_CA5_SHIFT 0

#define	CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA5_SHIFT))&CAU_RADR_CA_CA5_MASK)

#define	CAU_RADR_CA_CA6_MASK 0xFFFFFFFFu

#define	CAU_RADR_CA_CA6_SHIFT 0

#define	CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA6_SHIFT))&CAU_RADR_CA_CA6_MASK)

#define	CAU_RADR_CA_CA7_MASK 0xFFFFFFFFu

#define	CAU_RADR_CA_CA7_SHIFT 0

#define	CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA7_SHIFT))&CAU_RADR_CA_CA7_MASK)

#define	CAU_RADR_CA_CA8_MASK 0xFFFFFFFFu

#define	CAU_RADR_CA_CA8_SHIFT 0

#define	CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA8_SHIFT))&CAU_RADR_CA_CA8_MASK)

#define	CAU_XOR_CASR_IC_MASK 0x1u

#define	CAU_XOR_CASR_IC_SHIFT 0

#define	CAU_XOR_CASR_DPE_MASK 0x2u

#define	CAU_XOR_CASR_DPE_SHIFT 1

#define	CAU_XOR_CASR_VER_MASK 0xF0000000u

#define	CAU_XOR_CASR_VER_SHIFT 28

#define	CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)

#define	CAU_XOR_CAA_ACC_MASK 0xFFFFFFFFu

#define	CAU_XOR_CAA_ACC_SHIFT 0

#define	CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CAA_ACC_SHIFT))&CAU_XOR_CAA_ACC_MASK)

#define	CAU_XOR_CA_CA0_MASK 0xFFFFFFFFu

#define	CAU_XOR_CA_CA0_SHIFT 0

#define	CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA0_SHIFT))&CAU_XOR_CA_CA0_MASK)

#define	CAU_XOR_CA_CA1_MASK 0xFFFFFFFFu

#define	CAU_XOR_CA_CA1_SHIFT 0

#define	CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA1_SHIFT))&CAU_XOR_CA_CA1_MASK)

#define	CAU_XOR_CA_CA2_MASK 0xFFFFFFFFu

#define	CAU_XOR_CA_CA2_SHIFT 0

#define	CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA2_SHIFT))&CAU_XOR_CA_CA2_MASK)

#define	CAU_XOR_CA_CA3_MASK 0xFFFFFFFFu

#define	CAU_XOR_CA_CA3_SHIFT 0

#define	CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA3_SHIFT))&CAU_XOR_CA_CA3_MASK)

#define	CAU_XOR_CA_CA4_MASK 0xFFFFFFFFu

#define	CAU_XOR_CA_CA4_SHIFT 0

#define	CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA4_SHIFT))&CAU_XOR_CA_CA4_MASK)

#define	CAU_XOR_CA_CA5_MASK 0xFFFFFFFFu

#define	CAU_XOR_CA_CA5_SHIFT 0

#define	CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA5_SHIFT))&CAU_XOR_CA_CA5_MASK)

#define	CAU_XOR_CA_CA6_MASK 0xFFFFFFFFu

#define	CAU_XOR_CA_CA6_SHIFT 0

#define	CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA6_SHIFT))&CAU_XOR_CA_CA6_MASK)

#define	CAU_XOR_CA_CA7_MASK 0xFFFFFFFFu

#define	CAU_XOR_CA_CA7_SHIFT 0

#define	CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA7_SHIFT))&CAU_XOR_CA_CA7_MASK)

#define	CAU_XOR_CA_CA8_MASK 0xFFFFFFFFu

#define	CAU_XOR_CA_CA8_SHIFT 0

#define	CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA8_SHIFT))&CAU_XOR_CA_CA8_MASK)

#define	CAU_ROTL_CASR_IC_MASK 0x1u

#define	CAU_ROTL_CASR_IC_SHIFT 0

#define	CAU_ROTL_CASR_DPE_MASK 0x2u

#define	CAU_ROTL_CASR_DPE_SHIFT 1

#define	CAU_ROTL_CASR_VER_MASK 0xF0000000u

#define	CAU_ROTL_CASR_VER_SHIFT 28

#define	CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)

#define	CAU_ROTL_CAA_ACC_MASK 0xFFFFFFFFu

#define	CAU_ROTL_CAA_ACC_SHIFT 0

#define	CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CAA_ACC_SHIFT))&CAU_ROTL_CAA_ACC_MASK)

#define	CAU_ROTL_CA_CA0_MASK 0xFFFFFFFFu

#define	CAU_ROTL_CA_CA0_SHIFT 0

#define	CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA0_SHIFT))&CAU_ROTL_CA_CA0_MASK)

#define	CAU_ROTL_CA_CA1_MASK 0xFFFFFFFFu

#define	CAU_ROTL_CA_CA1_SHIFT 0

#define	CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA1_SHIFT))&CAU_ROTL_CA_CA1_MASK)

#define	CAU_ROTL_CA_CA2_MASK 0xFFFFFFFFu

#define	CAU_ROTL_CA_CA2_SHIFT 0

#define	CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA2_SHIFT))&CAU_ROTL_CA_CA2_MASK)

#define	CAU_ROTL_CA_CA3_MASK 0xFFFFFFFFu

#define	CAU_ROTL_CA_CA3_SHIFT 0

#define	CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA3_SHIFT))&CAU_ROTL_CA_CA3_MASK)

#define	CAU_ROTL_CA_CA4_MASK 0xFFFFFFFFu

#define	CAU_ROTL_CA_CA4_SHIFT 0

#define	CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA4_SHIFT))&CAU_ROTL_CA_CA4_MASK)

#define	CAU_ROTL_CA_CA5_MASK 0xFFFFFFFFu

#define	CAU_ROTL_CA_CA5_SHIFT 0

#define	CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA5_SHIFT))&CAU_ROTL_CA_CA5_MASK)

#define	CAU_ROTL_CA_CA6_MASK 0xFFFFFFFFu

#define	CAU_ROTL_CA_CA6_SHIFT 0

#define	CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA6_SHIFT))&CAU_ROTL_CA_CA6_MASK)

#define	CAU_ROTL_CA_CA7_MASK 0xFFFFFFFFu

#define	CAU_ROTL_CA_CA7_SHIFT 0

#define	CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA7_SHIFT))&CAU_ROTL_CA_CA7_MASK)

#define	CAU_ROTL_CA_CA8_MASK 0xFFFFFFFFu

#define	CAU_ROTL_CA_CA8_SHIFT 0

#define	CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA8_SHIFT))&CAU_ROTL_CA_CA8_MASK)

#define	CAU_AESC_CASR_IC_MASK 0x1u

#define	CAU_AESC_CASR_IC_SHIFT 0

#define	CAU_AESC_CASR_DPE_MASK 0x2u

#define	CAU_AESC_CASR_DPE_SHIFT 1

#define	CAU_AESC_CASR_VER_MASK 0xF0000000u

#define	CAU_AESC_CASR_VER_SHIFT 28

#define	CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)

#define	CAU_AESC_CAA_ACC_MASK 0xFFFFFFFFu

#define	CAU_AESC_CAA_ACC_SHIFT 0

#define	CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CAA_ACC_SHIFT))&CAU_AESC_CAA_ACC_MASK)

#define	CAU_AESC_CA_CA0_MASK 0xFFFFFFFFu

#define	CAU_AESC_CA_CA0_SHIFT 0

#define	CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA0_SHIFT))&CAU_AESC_CA_CA0_MASK)

#define	CAU_AESC_CA_CA1_MASK 0xFFFFFFFFu

#define	CAU_AESC_CA_CA1_SHIFT 0

#define	CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA1_SHIFT))&CAU_AESC_CA_CA1_MASK)

#define	CAU_AESC_CA_CA2_MASK 0xFFFFFFFFu

#define	CAU_AESC_CA_CA2_SHIFT 0

#define	CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA2_SHIFT))&CAU_AESC_CA_CA2_MASK)

#define	CAU_AESC_CA_CA3_MASK 0xFFFFFFFFu

#define	CAU_AESC_CA_CA3_SHIFT 0

#define	CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA3_SHIFT))&CAU_AESC_CA_CA3_MASK)

#define	CAU_AESC_CA_CA4_MASK 0xFFFFFFFFu

#define	CAU_AESC_CA_CA4_SHIFT 0

#define	CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA4_SHIFT))&CAU_AESC_CA_CA4_MASK)

#define	CAU_AESC_CA_CA5_MASK 0xFFFFFFFFu

#define	CAU_AESC_CA_CA5_SHIFT 0

#define	CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA5_SHIFT))&CAU_AESC_CA_CA5_MASK)

#define	CAU_AESC_CA_CA6_MASK 0xFFFFFFFFu

#define	CAU_AESC_CA_CA6_SHIFT 0

#define	CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA6_SHIFT))&CAU_AESC_CA_CA6_MASK)

#define	CAU_AESC_CA_CA7_MASK 0xFFFFFFFFu

#define	CAU_AESC_CA_CA7_SHIFT 0

#define	CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA7_SHIFT))&CAU_AESC_CA_CA7_MASK)

#define	CAU_AESC_CA_CA8_MASK 0xFFFFFFFFu

#define	CAU_AESC_CA_CA8_SHIFT 0

#define	CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA8_SHIFT))&CAU_AESC_CA_CA8_MASK)

#define	CAU_AESIC_CASR_IC_MASK 0x1u

#define	CAU_AESIC_CASR_IC_SHIFT 0

#define	CAU_AESIC_CASR_DPE_MASK 0x2u

#define	CAU_AESIC_CASR_DPE_SHIFT 1

#define	CAU_AESIC_CASR_VER_MASK 0xF0000000u

#define	CAU_AESIC_CASR_VER_SHIFT 28

#define	CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)

#define	CAU_AESIC_CAA_ACC_MASK 0xFFFFFFFFu

#define	CAU_AESIC_CAA_ACC_SHIFT 0

#define	CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CAA_ACC_SHIFT))&CAU_AESIC_CAA_ACC_MASK)

#define	CAU_AESIC_CA_CA0_MASK 0xFFFFFFFFu

#define	CAU_AESIC_CA_CA0_SHIFT 0

#define	CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA0_SHIFT))&CAU_AESIC_CA_CA0_MASK)

#define	CAU_AESIC_CA_CA1_MASK 0xFFFFFFFFu

#define	CAU_AESIC_CA_CA1_SHIFT 0

#define	CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA1_SHIFT))&CAU_AESIC_CA_CA1_MASK)

#define	CAU_AESIC_CA_CA2_MASK 0xFFFFFFFFu

#define	CAU_AESIC_CA_CA2_SHIFT 0

#define	CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA2_SHIFT))&CAU_AESIC_CA_CA2_MASK)

#define	CAU_AESIC_CA_CA3_MASK 0xFFFFFFFFu

#define	CAU_AESIC_CA_CA3_SHIFT 0

#define	CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA3_SHIFT))&CAU_AESIC_CA_CA3_MASK)

#define	CAU_AESIC_CA_CA4_MASK 0xFFFFFFFFu

#define	CAU_AESIC_CA_CA4_SHIFT 0

#define	CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA4_SHIFT))&CAU_AESIC_CA_CA4_MASK)

#define	CAU_AESIC_CA_CA5_MASK 0xFFFFFFFFu

#define	CAU_AESIC_CA_CA5_SHIFT 0

#define	CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA5_SHIFT))&CAU_AESIC_CA_CA5_MASK)

#define	CAU_AESIC_CA_CA6_MASK 0xFFFFFFFFu

#define	CAU_AESIC_CA_CA6_SHIFT 0

#define	CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA6_SHIFT))&CAU_AESIC_CA_CA6_MASK)

#define	CAU_AESIC_CA_CA7_MASK 0xFFFFFFFFu

#define	CAU_AESIC_CA_CA7_SHIFT 0

#define	CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA7_SHIFT))&CAU_AESIC_CA_CA7_MASK)

#define	CAU_AESIC_CA_CA8_MASK 0xFFFFFFFFu

#define	CAU_AESIC_CA_CA8_SHIFT 0

#define	CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA8_SHIFT))&CAU_AESIC_CA_CA8_MASK)

#define	CAU_BASE_PTR ((CAU_MemMapPtr)0xE0081000u)

#define	CAU_BASE_PTRS { CAU_BASE_PTR }

#define	CAU_DIRECT0 CAU_DIRECT_REG(CAU_BASE_PTR,0)

#define	CAU_DIRECT1 CAU_DIRECT_REG(CAU_BASE_PTR,1)

#define	CAU_DIRECT2 CAU_DIRECT_REG(CAU_BASE_PTR,2)

#define	CAU_DIRECT3 CAU_DIRECT_REG(CAU_BASE_PTR,3)

#define	CAU_DIRECT4 CAU_DIRECT_REG(CAU_BASE_PTR,4)

#define	CAU_DIRECT5 CAU_DIRECT_REG(CAU_BASE_PTR,5)

#define	CAU_DIRECT6 CAU_DIRECT_REG(CAU_BASE_PTR,6)

#define	CAU_DIRECT7 CAU_DIRECT_REG(CAU_BASE_PTR,7)

#define	CAU_DIRECT8 CAU_DIRECT_REG(CAU_BASE_PTR,8)

#define	CAU_DIRECT9 CAU_DIRECT_REG(CAU_BASE_PTR,9)

#define	CAU_DIRECT10 CAU_DIRECT_REG(CAU_BASE_PTR,10)

#define	CAU_DIRECT11 CAU_DIRECT_REG(CAU_BASE_PTR,11)

#define	CAU_DIRECT12 CAU_DIRECT_REG(CAU_BASE_PTR,12)

#define	CAU_DIRECT13 CAU_DIRECT_REG(CAU_BASE_PTR,13)

#define	CAU_DIRECT14 CAU_DIRECT_REG(CAU_BASE_PTR,14)

#define	CAU_DIRECT15 CAU_DIRECT_REG(CAU_BASE_PTR,15)

#define	CAU_LDR_CASR CAU_LDR_CASR_REG(CAU_BASE_PTR)

#define	CAU_LDR_CAA CAU_LDR_CAA_REG(CAU_BASE_PTR)

#define	CAU_LDR_CA0 CAU_LDR_CA_REG(CAU_BASE_PTR,0)

#define	CAU_LDR_CA1 CAU_LDR_CA_REG(CAU_BASE_PTR,1)

#define	CAU_LDR_CA2 CAU_LDR_CA_REG(CAU_BASE_PTR,2)

#define	CAU_LDR_CA3 CAU_LDR_CA_REG(CAU_BASE_PTR,3)

#define	CAU_LDR_CA4 CAU_LDR_CA_REG(CAU_BASE_PTR,4)

#define	CAU_LDR_CA5 CAU_LDR_CA_REG(CAU_BASE_PTR,5)

#define	CAU_LDR_CA6 CAU_LDR_CA_REG(CAU_BASE_PTR,6)

#define	CAU_LDR_CA7 CAU_LDR_CA_REG(CAU_BASE_PTR,7)

#define	CAU_LDR_CA8 CAU_LDR_CA_REG(CAU_BASE_PTR,8)

#define	CAU_STR_CASR CAU_STR_CASR_REG(CAU_BASE_PTR)

#define	CAU_STR_CAA CAU_STR_CAA_REG(CAU_BASE_PTR)

#define	CAU_STR_CA0 CAU_STR_CA_REG(CAU_BASE_PTR,0)

#define	CAU_STR_CA1 CAU_STR_CA_REG(CAU_BASE_PTR,1)

#define	CAU_STR_CA2 CAU_STR_CA_REG(CAU_BASE_PTR,2)

#define	CAU_STR_CA3 CAU_STR_CA_REG(CAU_BASE_PTR,3)

#define	CAU_STR_CA4 CAU_STR_CA_REG(CAU_BASE_PTR,4)

#define	CAU_STR_CA5 CAU_STR_CA_REG(CAU_BASE_PTR,5)

#define	CAU_STR_CA6 CAU_STR_CA_REG(CAU_BASE_PTR,6)

#define	CAU_STR_CA7 CAU_STR_CA_REG(CAU_BASE_PTR,7)

#define	CAU_STR_CA8 CAU_STR_CA_REG(CAU_BASE_PTR,8)

#define	CAU_ADR_CASR CAU_ADR_CASR_REG(CAU_BASE_PTR)

#define	CAU_ADR_CAA CAU_ADR_CAA_REG(CAU_BASE_PTR)

#define	CAU_ADR_CA0 CAU_ADR_CA_REG(CAU_BASE_PTR,0)

#define	CAU_ADR_CA1 CAU_ADR_CA_REG(CAU_BASE_PTR,1)

#define	CAU_ADR_CA2 CAU_ADR_CA_REG(CAU_BASE_PTR,2)

#define	CAU_ADR_CA3 CAU_ADR_CA_REG(CAU_BASE_PTR,3)

#define	CAU_ADR_CA4 CAU_ADR_CA_REG(CAU_BASE_PTR,4)

#define	CAU_ADR_CA5 CAU_ADR_CA_REG(CAU_BASE_PTR,5)

#define	CAU_ADR_CA6 CAU_ADR_CA_REG(CAU_BASE_PTR,6)

#define	CAU_ADR_CA7 CAU_ADR_CA_REG(CAU_BASE_PTR,7)

#define	CAU_ADR_CA8 CAU_ADR_CA_REG(CAU_BASE_PTR,8)

#define	CAU_RADR_CASR CAU_RADR_CASR_REG(CAU_BASE_PTR)

#define	CAU_RADR_CAA CAU_RADR_CAA_REG(CAU_BASE_PTR)

#define	CAU_RADR_CA0 CAU_RADR_CA_REG(CAU_BASE_PTR,0)

#define	CAU_RADR_CA1 CAU_RADR_CA_REG(CAU_BASE_PTR,1)

#define	CAU_RADR_CA2 CAU_RADR_CA_REG(CAU_BASE_PTR,2)

#define	CAU_RADR_CA3 CAU_RADR_CA_REG(CAU_BASE_PTR,3)

#define	CAU_RADR_CA4 CAU_RADR_CA_REG(CAU_BASE_PTR,4)

#define	CAU_RADR_CA5 CAU_RADR_CA_REG(CAU_BASE_PTR,5)

#define	CAU_RADR_CA6 CAU_RADR_CA_REG(CAU_BASE_PTR,6)

#define	CAU_RADR_CA7 CAU_RADR_CA_REG(CAU_BASE_PTR,7)

#define	CAU_RADR_CA8 CAU_RADR_CA_REG(CAU_BASE_PTR,8)

#define	CAU_XOR_CASR CAU_XOR_CASR_REG(CAU_BASE_PTR)

#define	CAU_XOR_CAA CAU_XOR_CAA_REG(CAU_BASE_PTR)

#define	CAU_XOR_CA0 CAU_XOR_CA_REG(CAU_BASE_PTR,0)

#define	CAU_XOR_CA1 CAU_XOR_CA_REG(CAU_BASE_PTR,1)

#define	CAU_XOR_CA2 CAU_XOR_CA_REG(CAU_BASE_PTR,2)

#define	CAU_XOR_CA3 CAU_XOR_CA_REG(CAU_BASE_PTR,3)

#define	CAU_XOR_CA4 CAU_XOR_CA_REG(CAU_BASE_PTR,4)

#define	CAU_XOR_CA5 CAU_XOR_CA_REG(CAU_BASE_PTR,5)

#define	CAU_XOR_CA6 CAU_XOR_CA_REG(CAU_BASE_PTR,6)

#define	CAU_XOR_CA7 CAU_XOR_CA_REG(CAU_BASE_PTR,7)

#define	CAU_XOR_CA8 CAU_XOR_CA_REG(CAU_BASE_PTR,8)

#define	CAU_ROTL_CASR CAU_ROTL_CASR_REG(CAU_BASE_PTR)

#define	CAU_ROTL_CAA CAU_ROTL_CAA_REG(CAU_BASE_PTR)

#define	CAU_ROTL_CA0 CAU_ROTL_CA_REG(CAU_BASE_PTR,0)

#define	CAU_ROTL_CA1 CAU_ROTL_CA_REG(CAU_BASE_PTR,1)

#define	CAU_ROTL_CA2 CAU_ROTL_CA_REG(CAU_BASE_PTR,2)

#define	CAU_ROTL_CA3 CAU_ROTL_CA_REG(CAU_BASE_PTR,3)

#define	CAU_ROTL_CA4 CAU_ROTL_CA_REG(CAU_BASE_PTR,4)

#define	CAU_ROTL_CA5 CAU_ROTL_CA_REG(CAU_BASE_PTR,5)

#define	CAU_ROTL_CA6 CAU_ROTL_CA_REG(CAU_BASE_PTR,6)

#define	CAU_ROTL_CA7 CAU_ROTL_CA_REG(CAU_BASE_PTR,7)

#define	CAU_ROTL_CA8 CAU_ROTL_CA_REG(CAU_BASE_PTR,8)

#define	CAU_AESC_CASR CAU_AESC_CASR_REG(CAU_BASE_PTR)

#define	CAU_AESC_CAA CAU_AESC_CAA_REG(CAU_BASE_PTR)

#define	CAU_AESC_CA0 CAU_AESC_CA_REG(CAU_BASE_PTR,0)

#define	CAU_AESC_CA1 CAU_AESC_CA_REG(CAU_BASE_PTR,1)

#define	CAU_AESC_CA2 CAU_AESC_CA_REG(CAU_BASE_PTR,2)

#define	CAU_AESC_CA3 CAU_AESC_CA_REG(CAU_BASE_PTR,3)

#define	CAU_AESC_CA4 CAU_AESC_CA_REG(CAU_BASE_PTR,4)

#define	CAU_AESC_CA5 CAU_AESC_CA_REG(CAU_BASE_PTR,5)

#define	CAU_AESC_CA6 CAU_AESC_CA_REG(CAU_BASE_PTR,6)

#define	CAU_AESC_CA7 CAU_AESC_CA_REG(CAU_BASE_PTR,7)

#define	CAU_AESC_CA8 CAU_AESC_CA_REG(CAU_BASE_PTR,8)

#define	CAU_AESIC_CASR CAU_AESIC_CASR_REG(CAU_BASE_PTR)

#define	CAU_AESIC_CAA CAU_AESIC_CAA_REG(CAU_BASE_PTR)

#define	CAU_AESIC_CA0 CAU_AESIC_CA_REG(CAU_BASE_PTR,0)

#define	CAU_AESIC_CA1 CAU_AESIC_CA_REG(CAU_BASE_PTR,1)

#define	CAU_AESIC_CA2 CAU_AESIC_CA_REG(CAU_BASE_PTR,2)

#define	CAU_AESIC_CA3 CAU_AESIC_CA_REG(CAU_BASE_PTR,3)

#define	CAU_AESIC_CA4 CAU_AESIC_CA_REG(CAU_BASE_PTR,4)

#define	CAU_AESIC_CA5 CAU_AESIC_CA_REG(CAU_BASE_PTR,5)

#define	CAU_AESIC_CA6 CAU_AESIC_CA_REG(CAU_BASE_PTR,6)

#define	CAU_AESIC_CA7 CAU_AESIC_CA_REG(CAU_BASE_PTR,7)

#define	CAU_AESIC_CA8 CAU_AESIC_CA_REG(CAU_BASE_PTR,8)

#define	CAU_DIRECT(index) CAU_DIRECT_REG(CAU_BASE_PTR,index)

#define	CAU_LDR_CA(index) CAU_LDR_CA_REG(CAU_BASE_PTR,index)

#define	CAU_STR_CA(index) CAU_STR_CA_REG(CAU_BASE_PTR,index)

#define	CAU_ADR_CA(index) CAU_ADR_CA_REG(CAU_BASE_PTR,index)

#define	CAU_RADR_CA(index) CAU_RADR_CA_REG(CAU_BASE_PTR,index)

#define	CAU_XOR_CA(index) CAU_XOR_CA_REG(CAU_BASE_PTR,index)

#define	CAU_ROTL_CA(index) CAU_ROTL_CA_REG(CAU_BASE_PTR,index)

#define	CAU_AESC_CA(index) CAU_AESC_CA_REG(CAU_BASE_PTR,index)

#define	CAU_AESIC_CA(index) CAU_AESIC_CA_REG(CAU_BASE_PTR,index)

#define	CMP_CR0_REG(base) ((base)->CR0)

#define	CMP_CR1_REG(base) ((base)->CR1)

#define	CMP_FPR_REG(base) ((base)->FPR)

#define	CMP_SCR_REG(base) ((base)->SCR)

#define	CMP_DACCR_REG(base) ((base)->DACCR)

#define	CMP_MUXCR_REG(base) ((base)->MUXCR)

#define	CMP_CR0_HYSTCTR_MASK 0x3u

#define	CMP_CR0_HYSTCTR_SHIFT 0

#define	CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)

#define	CMP_CR0_FILTER_CNT_MASK 0x70u

#define	CMP_CR0_FILTER_CNT_SHIFT 4

#define	CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)

#define	CMP_CR1_EN_MASK 0x1u

#define	CMP_CR1_EN_SHIFT 0

#define	CMP_CR1_OPE_MASK 0x2u

#define	CMP_CR1_OPE_SHIFT 1

#define	CMP_CR1_COS_MASK 0x4u

#define	CMP_CR1_COS_SHIFT 2

#define	CMP_CR1_INV_MASK 0x8u

#define	CMP_CR1_INV_SHIFT 3

#define	CMP_CR1_PMODE_MASK 0x10u

#define	CMP_CR1_PMODE_SHIFT 4

#define	CMP_CR1_WE_MASK 0x40u

#define	CMP_CR1_WE_SHIFT 6

#define	CMP_CR1_SE_MASK 0x80u

#define	CMP_CR1_SE_SHIFT 7

#define	CMP_FPR_FILT_PER_MASK 0xFFu

#define	CMP_FPR_FILT_PER_SHIFT 0

#define	CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)

#define	CMP_SCR_COUT_MASK 0x1u

#define	CMP_SCR_COUT_SHIFT 0

#define	CMP_SCR_CFF_MASK 0x2u

#define	CMP_SCR_CFF_SHIFT 1

#define	CMP_SCR_CFR_MASK 0x4u

#define	CMP_SCR_CFR_SHIFT 2

#define	CMP_SCR_IEF_MASK 0x8u

#define	CMP_SCR_IEF_SHIFT 3

#define	CMP_SCR_IER_MASK 0x10u

#define	CMP_SCR_IER_SHIFT 4

#define	CMP_SCR_DMAEN_MASK 0x40u

#define	CMP_SCR_DMAEN_SHIFT 6

#define	CMP_DACCR_VOSEL_MASK 0x3Fu

#define	CMP_DACCR_VOSEL_SHIFT 0

#define	CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)

#define	CMP_DACCR_VRSEL_MASK 0x40u

#define	CMP_DACCR_VRSEL_SHIFT 6

#define	CMP_DACCR_DACEN_MASK 0x80u

#define	CMP_DACCR_DACEN_SHIFT 7

#define	CMP_MUXCR_MSEL_MASK 0x7u

#define	CMP_MUXCR_MSEL_SHIFT 0

#define	CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)

#define	CMP_MUXCR_PSEL_MASK 0x38u

#define	CMP_MUXCR_PSEL_SHIFT 3

#define	CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)

#define	CMP0_BASE_PTR ((CMP_MemMapPtr)0x40073000u)

#define	CMP1_BASE_PTR ((CMP_MemMapPtr)0x40073008u)

#define	CMP2_BASE_PTR ((CMP_MemMapPtr)0x40073010u)

#define	CMP3_BASE_PTR ((CMP_MemMapPtr)0x40073018u)

#define	CMP_BASE_PTRS { CMP0_BASE_PTR, CMP1_BASE_PTR, CMP2_BASE_PTR, CMP3_BASE_PTR }

#define	CMP0_CR0 CMP_CR0_REG(CMP0_BASE_PTR)

#define	CMP0_CR1 CMP_CR1_REG(CMP0_BASE_PTR)

#define	CMP0_FPR CMP_FPR_REG(CMP0_BASE_PTR)

#define	CMP0_SCR CMP_SCR_REG(CMP0_BASE_PTR)

#define	CMP0_DACCR CMP_DACCR_REG(CMP0_BASE_PTR)

#define	CMP0_MUXCR CMP_MUXCR_REG(CMP0_BASE_PTR)

#define	CMP1_CR0 CMP_CR0_REG(CMP1_BASE_PTR)

#define	CMP1_CR1 CMP_CR1_REG(CMP1_BASE_PTR)

#define	CMP1_FPR CMP_FPR_REG(CMP1_BASE_PTR)

#define	CMP1_SCR CMP_SCR_REG(CMP1_BASE_PTR)

#define	CMP1_DACCR CMP_DACCR_REG(CMP1_BASE_PTR)

#define	CMP1_MUXCR CMP_MUXCR_REG(CMP1_BASE_PTR)

#define	CMP2_CR0 CMP_CR0_REG(CMP2_BASE_PTR)

#define	CMP2_CR1 CMP_CR1_REG(CMP2_BASE_PTR)

#define	CMP2_FPR CMP_FPR_REG(CMP2_BASE_PTR)

#define	CMP2_SCR CMP_SCR_REG(CMP2_BASE_PTR)

#define	CMP2_DACCR CMP_DACCR_REG(CMP2_BASE_PTR)

#define	CMP2_MUXCR CMP_MUXCR_REG(CMP2_BASE_PTR)

#define	CMP3_CR0 CMP_CR0_REG(CMP3_BASE_PTR)

#define	CMP3_CR1 CMP_CR1_REG(CMP3_BASE_PTR)

#define	CMP3_FPR CMP_FPR_REG(CMP3_BASE_PTR)

#define	CMP3_SCR CMP_SCR_REG(CMP3_BASE_PTR)

#define	CMP3_DACCR CMP_DACCR_REG(CMP3_BASE_PTR)

#define	CMP3_MUXCR CMP_MUXCR_REG(CMP3_BASE_PTR)

#define	CMT_CGH1_REG(base) ((base)->CGH1)

#define	CMT_CGL1_REG(base) ((base)->CGL1)

#define	CMT_CGH2_REG(base) ((base)->CGH2)

#define	CMT_CGL2_REG(base) ((base)->CGL2)

#define	CMT_OC_REG(base) ((base)->OC)

#define	CMT_MSC_REG(base) ((base)->MSC)

#define	CMT_CMD1_REG(base) ((base)->CMD1)

#define	CMT_CMD2_REG(base) ((base)->CMD2)

#define	CMT_CMD3_REG(base) ((base)->CMD3)

#define	CMT_CMD4_REG(base) ((base)->CMD4)

#define	CMT_PPS_REG(base) ((base)->PPS)

#define	CMT_DMA_REG(base) ((base)->DMA)

#define	CMT_CGH1_PH_MASK 0xFFu

#define	CMT_CGH1_PH_SHIFT 0

#define	CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)

#define	CMT_CGL1_PL_MASK 0xFFu

#define	CMT_CGL1_PL_SHIFT 0

#define	CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)

#define	CMT_CGH2_SH_MASK 0xFFu

#define	CMT_CGH2_SH_SHIFT 0

#define	CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)

#define	CMT_CGL2_SL_MASK 0xFFu

#define	CMT_CGL2_SL_SHIFT 0

#define	CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)

#define	CMT_OC_IROPEN_MASK 0x20u

#define	CMT_OC_IROPEN_SHIFT 5

#define	CMT_OC_CMTPOL_MASK 0x40u

#define	CMT_OC_CMTPOL_SHIFT 6

#define	CMT_OC_IROL_MASK 0x80u

#define	CMT_OC_IROL_SHIFT 7

#define	CMT_MSC_MCGEN_MASK 0x1u

#define	CMT_MSC_MCGEN_SHIFT 0

#define	CMT_MSC_EOCIE_MASK 0x2u

#define	CMT_MSC_EOCIE_SHIFT 1

#define	CMT_MSC_FSK_MASK 0x4u

#define	CMT_MSC_FSK_SHIFT 2

#define	CMT_MSC_BASE_MASK 0x8u

#define	CMT_MSC_BASE_SHIFT 3

#define	CMT_MSC_EXSPC_MASK 0x10u

#define	CMT_MSC_EXSPC_SHIFT 4

#define	CMT_MSC_CMTDIV_MASK 0x60u

#define	CMT_MSC_CMTDIV_SHIFT 5

#define	CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)

#define	CMT_MSC_EOCF_MASK 0x80u

#define	CMT_MSC_EOCF_SHIFT 7

#define	CMT_CMD1_MB_MASK 0xFFu

#define	CMT_CMD1_MB_SHIFT 0

#define	CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)

#define	CMT_CMD2_MB_MASK 0xFFu

#define	CMT_CMD2_MB_SHIFT 0

#define	CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)

#define	CMT_CMD3_SB_MASK 0xFFu

#define	CMT_CMD3_SB_SHIFT 0

#define	CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)

#define	CMT_CMD4_SB_MASK 0xFFu

#define	CMT_CMD4_SB_SHIFT 0

#define	CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)

#define	CMT_PPS_PPSDIV_MASK 0xFu

#define	CMT_PPS_PPSDIV_SHIFT 0

#define	CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)

#define	CMT_DMA_DMA_MASK 0x1u

#define	CMT_DMA_DMA_SHIFT 0

#define	CMT_BASE_PTR ((CMT_MemMapPtr)0x40062000u)

#define	CMT_BASE_PTRS { CMT_BASE_PTR }

#define	CMT_CGH1 CMT_CGH1_REG(CMT_BASE_PTR)

#define	CMT_CGL1 CMT_CGL1_REG(CMT_BASE_PTR)

#define	CMT_CGH2 CMT_CGH2_REG(CMT_BASE_PTR)

#define	CMT_CGL2 CMT_CGL2_REG(CMT_BASE_PTR)

#define	CMT_OC CMT_OC_REG(CMT_BASE_PTR)

#define	CMT_MSC CMT_MSC_REG(CMT_BASE_PTR)

#define	CMT_CMD1 CMT_CMD1_REG(CMT_BASE_PTR)

#define	CMT_CMD2 CMT_CMD2_REG(CMT_BASE_PTR)

#define	CMT_CMD3 CMT_CMD3_REG(CMT_BASE_PTR)

#define	CMT_CMD4 CMT_CMD4_REG(CMT_BASE_PTR)

#define	CMT_PPS CMT_PPS_REG(CMT_BASE_PTR)

#define	CMT_DMA CMT_DMA_REG(CMT_BASE_PTR)

#define	CRC_CRCL_REG(base) ((base)->ACCESS16BIT.CRCL)

#define	CRC_CRCH_REG(base) ((base)->ACCESS16BIT.CRCH)

#define	CRC_CRC_REG(base) ((base)->CRC)

#define	CRC_CRCLL_REG(base) ((base)->ACCESS8BIT.CRCLL)

#define	CRC_CRCLU_REG(base) ((base)->ACCESS8BIT.CRCLU)

#define	CRC_CRCHL_REG(base) ((base)->ACCESS8BIT.CRCHL)

#define	CRC_CRCHU_REG(base) ((base)->ACCESS8BIT.CRCHU)

#define	CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)

#define	CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)

#define	CRC_GPOLY_REG(base) ((base)->GPOLY)

#define	CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)

#define	CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)

#define	CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)

#define	CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)

#define	CRC_CTRL_REG(base) ((base)->CTRL)

#define	CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)

#define	CRC_CRCL_CRCL_MASK 0xFFFFu

#define	CRC_CRCL_CRCL_SHIFT 0

#define	CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)

#define	CRC_CRCH_CRCH_MASK 0xFFFFu

#define	CRC_CRCH_CRCH_SHIFT 0

#define	CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)

#define	CRC_CRC_LL_MASK 0xFFu

#define	CRC_CRC_LL_SHIFT 0

#define	CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)

#define	CRC_CRC_LU_MASK 0xFF00u

#define	CRC_CRC_LU_SHIFT 8

#define	CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)

#define	CRC_CRC_HL_MASK 0xFF0000u

#define	CRC_CRC_HL_SHIFT 16

#define	CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)

#define	CRC_CRC_HU_MASK 0xFF000000u

#define	CRC_CRC_HU_SHIFT 24

#define	CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)

#define	CRC_CRCLL_CRCLL_MASK 0xFFu

#define	CRC_CRCLL_CRCLL_SHIFT 0

#define	CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)

#define	CRC_CRCLU_CRCLU_MASK 0xFFu

#define	CRC_CRCLU_CRCLU_SHIFT 0

#define	CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)

#define	CRC_CRCHL_CRCHL_MASK 0xFFu

#define	CRC_CRCHL_CRCHL_SHIFT 0

#define	CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)

#define	CRC_CRCHU_CRCHU_MASK 0xFFu

#define	CRC_CRCHU_CRCHU_SHIFT 0

#define	CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)

#define	CRC_GPOLYL_GPOLYL_MASK 0xFFFFu

#define	CRC_GPOLYL_GPOLYL_SHIFT 0

#define	CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)

#define	CRC_GPOLYH_GPOLYH_MASK 0xFFFFu

#define	CRC_GPOLYH_GPOLYH_SHIFT 0

#define	CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)

#define	CRC_GPOLY_LOW_MASK 0xFFFFu

#define	CRC_GPOLY_LOW_SHIFT 0

#define	CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)

#define	CRC_GPOLY_HIGH_MASK 0xFFFF0000u

#define	CRC_GPOLY_HIGH_SHIFT 16

#define	CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)

#define	CRC_GPOLYLL_GPOLYLL_MASK 0xFFu

#define	CRC_GPOLYLL_GPOLYLL_SHIFT 0

#define	CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)

#define	CRC_GPOLYLU_GPOLYLU_MASK 0xFFu

#define	CRC_GPOLYLU_GPOLYLU_SHIFT 0

#define	CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)

#define	CRC_GPOLYHL_GPOLYHL_MASK 0xFFu

#define	CRC_GPOLYHL_GPOLYHL_SHIFT 0

#define	CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)

#define	CRC_GPOLYHU_GPOLYHU_MASK 0xFFu

#define	CRC_GPOLYHU_GPOLYHU_SHIFT 0

#define	CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)

#define	CRC_CTRL_TCRC_MASK 0x1000000u

#define	CRC_CTRL_TCRC_SHIFT 24

#define	CRC_CTRL_WAS_MASK 0x2000000u

#define	CRC_CTRL_WAS_SHIFT 25

#define	CRC_CTRL_FXOR_MASK 0x4000000u

#define	CRC_CTRL_FXOR_SHIFT 26

#define	CRC_CTRL_TOTR_MASK 0x30000000u

#define	CRC_CTRL_TOTR_SHIFT 28

#define	CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)

#define	CRC_CTRL_TOT_MASK 0xC0000000u

#define	CRC_CTRL_TOT_SHIFT 30

#define	CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)

#define	CRC_CTRLHU_TCRC_MASK 0x1u

#define	CRC_CTRLHU_TCRC_SHIFT 0

#define	CRC_CTRLHU_WAS_MASK 0x2u

#define	CRC_CTRLHU_WAS_SHIFT 1

#define	CRC_CTRLHU_FXOR_MASK 0x4u

#define	CRC_CTRLHU_FXOR_SHIFT 2

#define	CRC_CTRLHU_TOTR_MASK 0x30u

#define	CRC_CTRLHU_TOTR_SHIFT 4

#define	CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)

#define	CRC_CTRLHU_TOT_MASK 0xC0u

#define	CRC_CTRLHU_TOT_SHIFT 6

#define	CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)

#define	CRC_BASE_PTR ((CRC_MemMapPtr)0x40032000u)

#define	CRC_BASE_PTRS { CRC_BASE_PTR }

#define	CRC_CRC CRC_CRC_REG(CRC_BASE_PTR)

#define	CRC_CRCL CRC_CRCL_REG(CRC_BASE_PTR)

#define	CRC_CRCLL CRC_CRCLL_REG(CRC_BASE_PTR)

#define	CRC_CRCLU CRC_CRCLU_REG(CRC_BASE_PTR)

#define	CRC_CRCH CRC_CRCH_REG(CRC_BASE_PTR)

#define	CRC_CRCHL CRC_CRCHL_REG(CRC_BASE_PTR)

#define	CRC_CRCHU CRC_CRCHU_REG(CRC_BASE_PTR)

#define	CRC_GPOLY CRC_GPOLY_REG(CRC_BASE_PTR)

#define	CRC_GPOLYL CRC_GPOLYL_REG(CRC_BASE_PTR)

#define	CRC_GPOLYLL CRC_GPOLYLL_REG(CRC_BASE_PTR)

#define	CRC_GPOLYLU CRC_GPOLYLU_REG(CRC_BASE_PTR)

#define	CRC_GPOLYH CRC_GPOLYH_REG(CRC_BASE_PTR)

#define	CRC_GPOLYHL CRC_GPOLYHL_REG(CRC_BASE_PTR)

#define	CRC_GPOLYHU CRC_GPOLYHU_REG(CRC_BASE_PTR)

#define	CRC_CTRL CRC_CTRL_REG(CRC_BASE_PTR)

#define	CRC_CTRLHU CRC_CTRLHU_REG(CRC_BASE_PTR)

#define	CoreDebug_base_DHCSR_Read_REG(base) ((base)->base_DHCSR_Read)

#define	CoreDebug_base_DHCSR_Write_REG(base) ((base)->base_DHCSR_Write)

#define	CoreDebug_base_DCRSR_REG(base) ((base)->base_DCRSR)

#define	CoreDebug_base_DCRDR_REG(base) ((base)->base_DCRDR)

#define	CoreDebug_base_DEMCR_REG(base) ((base)->base_DEMCR)

#define	CoreDebug_BASE_PTR ((CoreDebug_MemMapPtr)0xE000EDF0u)

#define	CoreDebug_BASE_PTRS { CoreDebug_BASE_PTR }

#define	DHCSR_Read CoreDebug_base_DHCSR_Read_REG(CoreDebug_BASE_PTR)

#define	DHCSR_Write CoreDebug_base_DHCSR_Write_REG(CoreDebug_BASE_PTR)

#define	DCRSR CoreDebug_base_DCRSR_REG(CoreDebug_BASE_PTR)

#define	DCRDR CoreDebug_base_DCRDR_REG(CoreDebug_BASE_PTR)

#define	DEMCR CoreDebug_base_DEMCR_REG(CoreDebug_BASE_PTR)

#define	DAC_DATL_REG(base, index) ((base)->DAT[index].DATL)

#define	DAC_DATH_REG(base, index) ((base)->DAT[index].DATH)

#define	DAC_SR_REG(base) ((base)->SR)

#define	DAC_C0_REG(base) ((base)->C0)

#define	DAC_C1_REG(base) ((base)->C1)

#define	DAC_C2_REG(base) ((base)->C2)

#define	DAC_DATL_DATA_MASK 0xFFu

#define	DAC_DATL_DATA_SHIFT 0

#define	DAC_DATL_DATA(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA_SHIFT))&DAC_DATL_DATA_MASK)

#define	DAC_DATH_DATA_MASK 0xFu

#define	DAC_DATH_DATA_SHIFT 0

#define	DAC_DATH_DATA(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA_SHIFT))&DAC_DATH_DATA_MASK)

#define	DAC_SR_DACBFRPBF_MASK 0x1u

#define	DAC_SR_DACBFRPBF_SHIFT 0

#define	DAC_SR_DACBFRPTF_MASK 0x2u

#define	DAC_SR_DACBFRPTF_SHIFT 1

#define	DAC_SR_DACBFWMF_MASK 0x4u

#define	DAC_SR_DACBFWMF_SHIFT 2

#define	DAC_C0_DACBBIEN_MASK 0x1u

#define	DAC_C0_DACBBIEN_SHIFT 0

#define	DAC_C0_DACBTIEN_MASK 0x2u

#define	DAC_C0_DACBTIEN_SHIFT 1

#define	DAC_C0_DACBWIEN_MASK 0x4u

#define	DAC_C0_DACBWIEN_SHIFT 2

#define	DAC_C0_LPEN_MASK 0x8u

#define	DAC_C0_LPEN_SHIFT 3

#define	DAC_C0_DACSWTRG_MASK 0x10u

#define	DAC_C0_DACSWTRG_SHIFT 4

#define	DAC_C0_DACTRGSEL_MASK 0x20u

#define	DAC_C0_DACTRGSEL_SHIFT 5

#define	DAC_C0_DACRFS_MASK 0x40u

#define	DAC_C0_DACRFS_SHIFT 6

#define	DAC_C0_DACEN_MASK 0x80u

#define	DAC_C0_DACEN_SHIFT 7

#define	DAC_C1_DACBFEN_MASK 0x1u

#define	DAC_C1_DACBFEN_SHIFT 0

#define	DAC_C1_DACBFMD_MASK 0x6u

#define	DAC_C1_DACBFMD_SHIFT 1

#define	DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)

#define	DAC_C1_DACBFWM_MASK 0x18u

#define	DAC_C1_DACBFWM_SHIFT 3

#define	DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)

#define	DAC_C1_DMAEN_MASK 0x80u

#define	DAC_C1_DMAEN_SHIFT 7

#define	DAC_C2_DACBFUP_MASK 0xFu

#define	DAC_C2_DACBFUP_SHIFT 0

#define	DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)

#define	DAC_C2_DACBFRP_MASK 0xF0u

#define	DAC_C2_DACBFRP_SHIFT 4

#define	DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)

#define	DAC0_BASE_PTR ((DAC_MemMapPtr)0x400CC000u)

#define	DAC1_BASE_PTR ((DAC_MemMapPtr)0x400CD000u)

#define	DAC_BASE_PTRS { DAC0_BASE_PTR, DAC1_BASE_PTR }

#define	DAC0_DAT0L DAC_DATL_REG(DAC0_BASE_PTR,0)

#define	DAC0_DAT0H DAC_DATH_REG(DAC0_BASE_PTR,0)

#define	DAC0_DAT1L DAC_DATL_REG(DAC0_BASE_PTR,1)

#define	DAC0_DAT1H DAC_DATH_REG(DAC0_BASE_PTR,1)

#define	DAC0_DAT2L DAC_DATL_REG(DAC0_BASE_PTR,2)

#define	DAC0_DAT2H DAC_DATH_REG(DAC0_BASE_PTR,2)

#define	DAC0_DAT3L DAC_DATL_REG(DAC0_BASE_PTR,3)

#define	DAC0_DAT3H DAC_DATH_REG(DAC0_BASE_PTR,3)

#define	DAC0_DAT4L DAC_DATL_REG(DAC0_BASE_PTR,4)

#define	DAC0_DAT4H DAC_DATH_REG(DAC0_BASE_PTR,4)

#define	DAC0_DAT5L DAC_DATL_REG(DAC0_BASE_PTR,5)

#define	DAC0_DAT5H DAC_DATH_REG(DAC0_BASE_PTR,5)

#define	DAC0_DAT6L DAC_DATL_REG(DAC0_BASE_PTR,6)

#define	DAC0_DAT6H DAC_DATH_REG(DAC0_BASE_PTR,6)

#define	DAC0_DAT7L DAC_DATL_REG(DAC0_BASE_PTR,7)

#define	DAC0_DAT7H DAC_DATH_REG(DAC0_BASE_PTR,7)

#define	DAC0_DAT8L DAC_DATL_REG(DAC0_BASE_PTR,8)

#define	DAC0_DAT8H DAC_DATH_REG(DAC0_BASE_PTR,8)

#define	DAC0_DAT9L DAC_DATL_REG(DAC0_BASE_PTR,9)

#define	DAC0_DAT9H DAC_DATH_REG(DAC0_BASE_PTR,9)

#define	DAC0_DAT10L DAC_DATL_REG(DAC0_BASE_PTR,10)

#define	DAC0_DAT10H DAC_DATH_REG(DAC0_BASE_PTR,10)

#define	DAC0_DAT11L DAC_DATL_REG(DAC0_BASE_PTR,11)

#define	DAC0_DAT11H DAC_DATH_REG(DAC0_BASE_PTR,11)

#define	DAC0_DAT12L DAC_DATL_REG(DAC0_BASE_PTR,12)

#define	DAC0_DAT12H DAC_DATH_REG(DAC0_BASE_PTR,12)

#define	DAC0_DAT13L DAC_DATL_REG(DAC0_BASE_PTR,13)

#define	DAC0_DAT13H DAC_DATH_REG(DAC0_BASE_PTR,13)

#define	DAC0_DAT14L DAC_DATL_REG(DAC0_BASE_PTR,14)

#define	DAC0_DAT14H DAC_DATH_REG(DAC0_BASE_PTR,14)

#define	DAC0_DAT15L DAC_DATL_REG(DAC0_BASE_PTR,15)

#define	DAC0_DAT15H DAC_DATH_REG(DAC0_BASE_PTR,15)

#define	DAC0_SR DAC_SR_REG(DAC0_BASE_PTR)

#define	DAC0_C0 DAC_C0_REG(DAC0_BASE_PTR)

#define	DAC0_C1 DAC_C1_REG(DAC0_BASE_PTR)

#define	DAC0_C2 DAC_C2_REG(DAC0_BASE_PTR)

#define	DAC1_DAT0L DAC_DATL_REG(DAC1_BASE_PTR,0)

#define	DAC1_DAT0H DAC_DATH_REG(DAC1_BASE_PTR,0)

#define	DAC1_DAT1L DAC_DATL_REG(DAC1_BASE_PTR,1)

#define	DAC1_DAT1H DAC_DATH_REG(DAC1_BASE_PTR,1)

#define	DAC1_DAT2L DAC_DATL_REG(DAC1_BASE_PTR,2)

#define	DAC1_DAT2H DAC_DATH_REG(DAC1_BASE_PTR,2)

#define	DAC1_DAT3L DAC_DATL_REG(DAC1_BASE_PTR,3)

#define	DAC1_DAT3H DAC_DATH_REG(DAC1_BASE_PTR,3)

#define	DAC1_DAT4L DAC_DATL_REG(DAC1_BASE_PTR,4)

#define	DAC1_DAT4H DAC_DATH_REG(DAC1_BASE_PTR,4)

#define	DAC1_DAT5L DAC_DATL_REG(DAC1_BASE_PTR,5)

#define	DAC1_DAT5H DAC_DATH_REG(DAC1_BASE_PTR,5)

#define	DAC1_DAT6L DAC_DATL_REG(DAC1_BASE_PTR,6)

#define	DAC1_DAT6H DAC_DATH_REG(DAC1_BASE_PTR,6)

#define	DAC1_DAT7L DAC_DATL_REG(DAC1_BASE_PTR,7)

#define	DAC1_DAT7H DAC_DATH_REG(DAC1_BASE_PTR,7)

#define	DAC1_DAT8L DAC_DATL_REG(DAC1_BASE_PTR,8)

#define	DAC1_DAT8H DAC_DATH_REG(DAC1_BASE_PTR,8)

#define	DAC1_DAT9L DAC_DATL_REG(DAC1_BASE_PTR,9)

#define	DAC1_DAT9H DAC_DATH_REG(DAC1_BASE_PTR,9)

#define	DAC1_DAT10L DAC_DATL_REG(DAC1_BASE_PTR,10)

#define	DAC1_DAT10H DAC_DATH_REG(DAC1_BASE_PTR,10)

#define	DAC1_DAT11L DAC_DATL_REG(DAC1_BASE_PTR,11)

#define	DAC1_DAT11H DAC_DATH_REG(DAC1_BASE_PTR,11)

#define	DAC1_DAT12L DAC_DATL_REG(DAC1_BASE_PTR,12)

#define	DAC1_DAT12H DAC_DATH_REG(DAC1_BASE_PTR,12)

#define	DAC1_DAT13L DAC_DATL_REG(DAC1_BASE_PTR,13)

#define	DAC1_DAT13H DAC_DATH_REG(DAC1_BASE_PTR,13)

#define	DAC1_DAT14L DAC_DATL_REG(DAC1_BASE_PTR,14)

#define	DAC1_DAT14H DAC_DATH_REG(DAC1_BASE_PTR,14)

#define	DAC1_DAT15L DAC_DATL_REG(DAC1_BASE_PTR,15)

#define	DAC1_DAT15H DAC_DATH_REG(DAC1_BASE_PTR,15)

#define	DAC1_SR DAC_SR_REG(DAC1_BASE_PTR)

#define	DAC1_C0 DAC_C0_REG(DAC1_BASE_PTR)

#define	DAC1_C1 DAC_C1_REG(DAC1_BASE_PTR)

#define	DAC1_C2 DAC_C2_REG(DAC1_BASE_PTR)

#define	DAC0_DATL(index) DAC_DATL_REG(DAC0_BASE_PTR,index)

#define	DAC1_DATL(index) DAC_DATL_REG(DAC1_BASE_PTR,index)

#define	DAC0_DATH(index) DAC_DATH_REG(DAC0_BASE_PTR,index)

#define	DAC1_DATH(index) DAC_DATH_REG(DAC1_BASE_PTR,index)

#define	DDR_CR00_REG(base) ((base)->CR00)

#define	DDR_CR01_REG(base) ((base)->CR01)

#define	DDR_CR02_REG(base) ((base)->CR02)

#define	DDR_CR03_REG(base) ((base)->CR03)

#define	DDR_CR04_REG(base) ((base)->CR04)

#define	DDR_CR05_REG(base) ((base)->CR05)

#define	DDR_CR06_REG(base) ((base)->CR06)

#define	DDR_CR07_REG(base) ((base)->CR07)

#define	DDR_CR08_REG(base) ((base)->CR08)

#define	DDR_CR09_REG(base) ((base)->CR09)

#define	DDR_CR10_REG(base) ((base)->CR10)

#define	DDR_CR11_REG(base) ((base)->CR11)

#define	DDR_CR12_REG(base) ((base)->CR12)

#define	DDR_CR13_REG(base) ((base)->CR13)

#define	DDR_CR14_REG(base) ((base)->CR14)

#define	DDR_CR15_REG(base) ((base)->CR15)

#define	DDR_CR16_REG(base) ((base)->CR16)

#define	DDR_CR17_REG(base) ((base)->CR17)

#define	DDR_CR18_REG(base) ((base)->CR18)

#define	DDR_CR19_REG(base) ((base)->CR19)

#define	DDR_CR20_REG(base) ((base)->CR20)

#define	DDR_CR21_REG(base) ((base)->CR21)

#define	DDR_CR22_REG(base) ((base)->CR22)

#define	DDR_CR23_REG(base) ((base)->CR23)

#define	DDR_CR24_REG(base) ((base)->CR24)

#define	DDR_CR25_REG(base) ((base)->CR25)

#define	DDR_CR26_REG(base) ((base)->CR26)

#define	DDR_CR27_REG(base) ((base)->CR27)

#define	DDR_CR28_REG(base) ((base)->CR28)

#define	DDR_CR29_REG(base) ((base)->CR29)

#define	DDR_CR30_REG(base) ((base)->CR30)

#define	DDR_CR31_REG(base) ((base)->CR31)

#define	DDR_CR32_REG(base) ((base)->CR32)

#define	DDR_CR33_REG(base) ((base)->CR33)

#define	DDR_CR34_REG(base) ((base)->CR34)

#define	DDR_CR35_REG(base) ((base)->CR35)

#define	DDR_CR36_REG(base) ((base)->CR36)

#define	DDR_CR37_REG(base) ((base)->CR37)

#define	DDR_CR38_REG(base) ((base)->CR38)

#define	DDR_CR39_REG(base) ((base)->CR39)

#define	DDR_CR40_REG(base) ((base)->CR40)

#define	DDR_CR41_REG(base) ((base)->CR41)

#define	DDR_CR42_REG(base) ((base)->CR42)

#define	DDR_CR43_REG(base) ((base)->CR43)

#define	DDR_CR44_REG(base) ((base)->CR44)

#define	DDR_CR45_REG(base) ((base)->CR45)

#define	DDR_CR46_REG(base) ((base)->CR46)

#define	DDR_CR47_REG(base) ((base)->CR47)

#define	DDR_CR48_REG(base) ((base)->CR48)

#define	DDR_CR49_REG(base) ((base)->CR49)

#define	DDR_CR50_REG(base) ((base)->CR50)

#define	DDR_CR51_REG(base) ((base)->CR51)

#define	DDR_CR52_REG(base) ((base)->CR52)

#define	DDR_CR53_REG(base) ((base)->CR53)

#define	DDR_CR54_REG(base) ((base)->CR54)

#define	DDR_CR55_REG(base) ((base)->CR55)

#define	DDR_CR56_REG(base) ((base)->CR56)

#define	DDR_CR57_REG(base) ((base)->CR57)

#define	DDR_CR58_REG(base) ((base)->CR58)

#define	DDR_CR59_REG(base) ((base)->CR59)

#define	DDR_CR60_REG(base) ((base)->CR60)

#define	DDR_CR61_REG(base) ((base)->CR61)

#define	DDR_CR62_REG(base) ((base)->CR62)

#define	DDR_CR63_REG(base) ((base)->CR63)

#define	DDR_RCR_REG(base) ((base)->RCR)

#define	DDR_PAD_CTRL_REG(base) ((base)->PAD_CTRL)

#define	DDR_CR00_START_MASK 0x1u

#define	DDR_CR00_START_SHIFT 0

#define	DDR_CR00_DDRCLS_MASK 0xF00u

#define	DDR_CR00_DDRCLS_SHIFT 8

#define	DDR_CR00_DDRCLS(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR00_DDRCLS_SHIFT))&DDR_CR00_DDRCLS_MASK)

#define	DDR_CR00_VERSION_MASK 0xFFFF0000u

#define	DDR_CR00_VERSION_SHIFT 16

#define	DDR_CR00_VERSION(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR00_VERSION_SHIFT))&DDR_CR00_VERSION_MASK)

#define	DDR_CR01_MAXROW_MASK 0x1Fu

#define	DDR_CR01_MAXROW_SHIFT 0

#define	DDR_CR01_MAXROW(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR01_MAXROW_SHIFT))&DDR_CR01_MAXROW_MASK)

#define	DDR_CR01_MAXCOL_MASK 0xF00u

#define	DDR_CR01_MAXCOL_SHIFT 8

#define	DDR_CR01_MAXCOL(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR01_MAXCOL_SHIFT))&DDR_CR01_MAXCOL_MASK)

#define	DDR_CR01_CSMAX_MASK 0x30000u

#define	DDR_CR01_CSMAX_SHIFT 16

#define	DDR_CR01_CSMAX(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR01_CSMAX_SHIFT))&DDR_CR01_CSMAX_MASK)

#define	DDR_CR02_TINIT_MASK 0xFFFFFFu

#define	DDR_CR02_TINIT_SHIFT 0

#define	DDR_CR02_TINIT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR02_TINIT_SHIFT))&DDR_CR02_TINIT_MASK)

#define	DDR_CR02_INITAREF_MASK 0xF000000u

#define	DDR_CR02_INITAREF_SHIFT 24

#define	DDR_CR02_INITAREF(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR02_INITAREF_SHIFT))&DDR_CR02_INITAREF_MASK)

#define	DDR_CR03_LATLIN_MASK 0xFu

#define	DDR_CR03_LATLIN_SHIFT 0

#define	DDR_CR03_LATLIN(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR03_LATLIN_SHIFT))&DDR_CR03_LATLIN_MASK)

#define	DDR_CR03_LATGATE_MASK 0xF00u

#define	DDR_CR03_LATGATE_SHIFT 8

#define	DDR_CR03_LATGATE(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR03_LATGATE_SHIFT))&DDR_CR03_LATGATE_MASK)

#define	DDR_CR03_WRLAT_MASK 0xF0000u

#define	DDR_CR03_WRLAT_SHIFT 16

#define	DDR_CR03_WRLAT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR03_WRLAT_SHIFT))&DDR_CR03_WRLAT_MASK)

#define	DDR_CR03_TCCD_MASK 0x1F000000u

#define	DDR_CR03_TCCD_SHIFT 24

#define	DDR_CR03_TCCD(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR03_TCCD_SHIFT))&DDR_CR03_TCCD_MASK)

#define	DDR_CR04_TBINT_MASK 0x7u

#define	DDR_CR04_TBINT_SHIFT 0

#define	DDR_CR04_TBINT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR04_TBINT_SHIFT))&DDR_CR04_TBINT_MASK)

#define	DDR_CR04_TRRD_MASK 0x700u

#define	DDR_CR04_TRRD_SHIFT 8

#define	DDR_CR04_TRRD(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR04_TRRD_SHIFT))&DDR_CR04_TRRD_MASK)

#define	DDR_CR04_TRC_MASK 0x3F0000u

#define	DDR_CR04_TRC_SHIFT 16

#define	DDR_CR04_TRC(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR04_TRC_SHIFT))&DDR_CR04_TRC_MASK)

#define	DDR_CR04_TRASMIN_MASK 0xFF000000u

#define	DDR_CR04_TRASMIN_SHIFT 24

#define	DDR_CR04_TRASMIN(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR04_TRASMIN_SHIFT))&DDR_CR04_TRASMIN_MASK)

#define	DDR_CR05_TWTR_MASK 0xFu

#define	DDR_CR05_TWTR_SHIFT 0

#define	DDR_CR05_TWTR(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR05_TWTR_SHIFT))&DDR_CR05_TWTR_MASK)

#define	DDR_CR05_TRP_MASK 0xF00u

#define	DDR_CR05_TRP_SHIFT 8

#define	DDR_CR05_TRP(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR05_TRP_SHIFT))&DDR_CR05_TRP_MASK)

#define	DDR_CR05_TRTP_MASK 0x70000u

#define	DDR_CR05_TRTP_SHIFT 16

#define	DDR_CR05_TRTP(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR05_TRTP_SHIFT))&DDR_CR05_TRTP_MASK)

#define	DDR_CR05_TMRD_MASK 0x1F000000u

#define	DDR_CR05_TMRD_SHIFT 24

#define	DDR_CR05_TMRD(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR05_TMRD_SHIFT))&DDR_CR05_TMRD_MASK)

#define	DDR_CR06_TMOD_MASK 0xFFu

#define	DDR_CR06_TMOD_SHIFT 0

#define	DDR_CR06_TMOD(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR06_TMOD_SHIFT))&DDR_CR06_TMOD_MASK)

#define	DDR_CR06_TRASMAX_MASK 0xFFFF00u

#define	DDR_CR06_TRASMAX_SHIFT 8

#define	DDR_CR06_TRASMAX(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR06_TRASMAX_SHIFT))&DDR_CR06_TRASMAX_MASK)

#define	DDR_CR06_INTWBR_MASK 0x1000000u

#define	DDR_CR06_INTWBR_SHIFT 24

#define	DDR_CR07_CLKPW_MASK 0x7u

#define	DDR_CR07_CLKPW_SHIFT 0

#define	DDR_CR07_CLKPW(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR07_CLKPW_SHIFT))&DDR_CR07_CLKPW_MASK)

#define	DDR_CR07_TCKESR_MASK 0x1F00u

#define	DDR_CR07_TCKESR_SHIFT 8

#define	DDR_CR07_TCKESR(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR07_TCKESR_SHIFT))&DDR_CR07_TCKESR_MASK)

#define	DDR_CR07_AP_MASK 0x10000u

#define	DDR_CR07_AP_SHIFT 16

#define	DDR_CR07_CCAPEN_MASK 0x1000000u

#define	DDR_CR07_CCAPEN_SHIFT 24

#define	DDR_CR08_TRAS_MASK 0x1u

#define	DDR_CR08_TRAS_SHIFT 0

#define	DDR_CR08_TRASDI_MASK 0xFF00u

#define	DDR_CR08_TRASDI_SHIFT 8

#define	DDR_CR08_TRASDI(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR08_TRASDI_SHIFT))&DDR_CR08_TRASDI_MASK)

#define	DDR_CR08_TWR_MASK 0x1F0000u

#define	DDR_CR08_TWR_SHIFT 16

#define	DDR_CR08_TWR(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR08_TWR_SHIFT))&DDR_CR08_TWR_MASK)

#define	DDR_CR08_TDAL_MASK 0x1F000000u

#define	DDR_CR08_TDAL_SHIFT 24

#define	DDR_CR08_TDAL(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR08_TDAL_SHIFT))&DDR_CR08_TDAL_MASK)

#define	DDR_CR09_TDLL_MASK 0xFFFFu

#define	DDR_CR09_TDLL_SHIFT 0

#define	DDR_CR09_TDLL(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR09_TDLL_SHIFT))&DDR_CR09_TDLL_MASK)

#define	DDR_CR09_NOCMD_MASK 0x10000u

#define	DDR_CR09_NOCMD_SHIFT 16

#define	DDR_CR09_BSTLEN_MASK 0x7000000u

#define	DDR_CR09_BSTLEN_SHIFT 24

#define	DDR_CR09_BSTLEN(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR09_BSTLEN_SHIFT))&DDR_CR09_BSTLEN_MASK)

#define	DDR_CR10_TFAW_MASK 0x3Fu

#define	DDR_CR10_TFAW_SHIFT 0

#define	DDR_CR10_TFAW(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR10_TFAW_SHIFT))&DDR_CR10_TFAW_MASK)

#define	DDR_CR10_TCPD_MASK 0xFFFF00u

#define	DDR_CR10_TCPD_SHIFT 8

#define	DDR_CR10_TCPD(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR10_TCPD_SHIFT))&DDR_CR10_TCPD_MASK)

#define	DDR_CR10_TRPAB_MASK 0xF000000u

#define	DDR_CR10_TRPAB_SHIFT 24

#define	DDR_CR10_TRPAB(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR10_TRPAB_SHIFT))&DDR_CR10_TRPAB_MASK)

#define	DDR_CR11_REGDIMM_MASK 0x1u

#define	DDR_CR11_REGDIMM_SHIFT 0

#define	DDR_CR11_AREF_MASK 0x100u

#define	DDR_CR11_AREF_SHIFT 8

#define	DDR_CR11_AREFMODE_MASK 0x10000u

#define	DDR_CR11_AREFMODE_SHIFT 16

#define	DDR_CR11_TREFEN_MASK 0x1000000u

#define	DDR_CR11_TREFEN_SHIFT 24

#define	DDR_CR12_TRFC_MASK 0x3FFu

#define	DDR_CR12_TRFC_SHIFT 0

#define	DDR_CR12_TRFC(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR12_TRFC_SHIFT))&DDR_CR12_TRFC_MASK)

#define	DDR_CR12_TREF_MASK 0x3FFF0000u

#define	DDR_CR12_TREF_SHIFT 16

#define	DDR_CR12_TREF(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR12_TREF_SHIFT))&DDR_CR12_TREF_MASK)

#define	DDR_CR13_TREFINT_MASK 0x3FFFu

#define	DDR_CR13_TREFINT_SHIFT 0

#define	DDR_CR13_TREFINT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR13_TREFINT_SHIFT))&DDR_CR13_TREFINT_MASK)

#define	DDR_CR13_PD_MASK 0x10000u

#define	DDR_CR13_PD_SHIFT 16

#define	DDR_CR14_TPDEX_MASK 0xFFFFu

#define	DDR_CR14_TPDEX_SHIFT 0

#define	DDR_CR14_TPDEX(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR14_TPDEX_SHIFT))&DDR_CR14_TPDEX_MASK)

#define	DDR_CR14_TXSR_MASK 0xFFFF0000u

#define	DDR_CR14_TXSR_SHIFT 16

#define	DDR_CR14_TXSR(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR14_TXSR_SHIFT))&DDR_CR14_TXSR_MASK)

#define	DDR_CR15_TXSNR_MASK 0xFFFFu

#define	DDR_CR15_TXSNR_SHIFT 0

#define	DDR_CR15_TXSNR(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR15_TXSNR_SHIFT))&DDR_CR15_TXSNR_MASK)

#define	DDR_CR15_SREF_MASK 0x10000u

#define	DDR_CR15_SREF_SHIFT 16

#define	DDR_CR15_PUREF_MASK 0x1000000u

#define	DDR_CR15_PUREF_SHIFT 24

#define	DDR_CR16_QKREF_MASK 0x1u

#define	DDR_CR16_QKREF_SHIFT 0

#define	DDR_CR16_CLKDLY_MASK 0x700u

#define	DDR_CR16_CLKDLY_SHIFT 8

#define	DDR_CR16_CLKDLY(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR16_CLKDLY_SHIFT))&DDR_CR16_CLKDLY_MASK)

#define	DDR_CR16_LPCTRL_MASK 0x1F0000u

#define	DDR_CR16_LPCTRL_SHIFT 16

#define	DDR_CR16_LPCTRL(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR16_LPCTRL_SHIFT))&DDR_CR16_LPCTRL_MASK)

#define	DDR_CR17_LPPDCNT_MASK 0xFFFFu

#define	DDR_CR17_LPPDCNT_SHIFT 0

#define	DDR_CR17_LPPDCNT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR17_LPPDCNT_SHIFT))&DDR_CR17_LPPDCNT_MASK)

#define	DDR_CR17_LPRFCNT_MASK 0xFFFF0000u

#define	DDR_CR17_LPRFCNT_SHIFT 16

#define	DDR_CR17_LPRFCNT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR17_LPRFCNT_SHIFT))&DDR_CR17_LPRFCNT_MASK)

#define	DDR_CR18_LPEXTCNT_MASK 0xFFFFu

#define	DDR_CR18_LPEXTCNT_SHIFT 0

#define	DDR_CR18_LPEXTCNT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR18_LPEXTCNT_SHIFT))&DDR_CR18_LPEXTCNT_MASK)

#define	DDR_CR18_LPAUTO_MASK 0x1F0000u

#define	DDR_CR18_LPAUTO_SHIFT 16

#define	DDR_CR18_LPAUTO(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR18_LPAUTO_SHIFT))&DDR_CR18_LPAUTO_MASK)

#define	DDR_CR19_LPINTCNT_MASK 0xFFFFu

#define	DDR_CR19_LPINTCNT_SHIFT 0

#define	DDR_CR19_LPINTCNT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR19_LPINTCNT_SHIFT))&DDR_CR19_LPINTCNT_MASK)

#define	DDR_CR19_LPRFHOLD_MASK 0xFFFF0000u

#define	DDR_CR19_LPRFHOLD_SHIFT 16

#define	DDR_CR19_LPRFHOLD(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR19_LPRFHOLD_SHIFT))&DDR_CR19_LPRFHOLD_MASK)

#define	DDR_CR20_LPRE_MASK 0x3u

#define	DDR_CR20_LPRE_SHIFT 0

#define	DDR_CR20_LPRE(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR20_LPRE_SHIFT))&DDR_CR20_LPRE_MASK)

#define	DDR_CR20_CKSRE_MASK 0xF00u

#define	DDR_CR20_CKSRE_SHIFT 8

#define	DDR_CR20_CKSRE(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR20_CKSRE_SHIFT))&DDR_CR20_CKSRE_MASK)

#define	DDR_CR20_CKSRX_MASK 0xF0000u

#define	DDR_CR20_CKSRX_SHIFT 16

#define	DDR_CR20_CKSRX(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR20_CKSRX_SHIFT))&DDR_CR20_CKSRX_MASK)

#define	DDR_CR20_WRMD_MASK 0x1000000u

#define	DDR_CR20_WRMD_SHIFT 24

#define	DDR_CR21_MR0DAT0_MASK 0xFFFFu

#define	DDR_CR21_MR0DAT0_SHIFT 0

#define	DDR_CR21_MR0DAT0(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR21_MR0DAT0_SHIFT))&DDR_CR21_MR0DAT0_MASK)

#define	DDR_CR21_MR1DAT0_MASK 0xFFFF0000u

#define	DDR_CR21_MR1DAT0_SHIFT 16

#define	DDR_CR21_MR1DAT0(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR21_MR1DAT0_SHIFT))&DDR_CR21_MR1DAT0_MASK)

#define	DDR_CR22_MR2DATA0_MASK 0xFFFFu

#define	DDR_CR22_MR2DATA0_SHIFT 0

#define	DDR_CR22_MR2DATA0(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR22_MR2DATA0_SHIFT))&DDR_CR22_MR2DATA0_MASK)

#define	DDR_CR22_MR3DAT0_MASK 0xFFFF0000u

#define	DDR_CR22_MR3DAT0_SHIFT 16

#define	DDR_CR22_MR3DAT0(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR22_MR3DAT0_SHIFT))&DDR_CR22_MR3DAT0_MASK)

#define	DDR_CR23_Not_Used_MASK 0xFFFFu

#define	DDR_CR23_Not_Used_SHIFT 0

#define	DDR_CR23_Not_Used(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR23_Not_Used_SHIFT))&DDR_CR23_Not_Used_MASK)

#define	DDR_CR23_NOT_USED_MASK 0xFFFF0000u

#define	DDR_CR23_NOT_USED_SHIFT 16

#define	DDR_CR23_NOT_USED(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR23_NOT_USED_SHIFT))&DDR_CR23_NOT_USED_MASK)

#define	DDR_CR25_BNK8_MASK 0x1u

#define	DDR_CR25_BNK8_SHIFT 0

#define	DDR_CR25_ADDPINS_MASK 0x700u

#define	DDR_CR25_ADDPINS_SHIFT 8

#define	DDR_CR25_ADDPINS(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR25_ADDPINS_SHIFT))&DDR_CR25_ADDPINS_MASK)

#define	DDR_CR25_COLSIZ_MASK 0x70000u

#define	DDR_CR25_COLSIZ_SHIFT 16

#define	DDR_CR25_COLSIZ(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR25_COLSIZ_SHIFT))&DDR_CR25_COLSIZ_MASK)

#define	DDR_CR25_APREBIT_MASK 0xF000000u

#define	DDR_CR25_APREBIT_SHIFT 24

#define	DDR_CR25_APREBIT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR25_APREBIT_SHIFT))&DDR_CR25_APREBIT_MASK)

#define	DDR_CR26_AGECNT_MASK 0xFFu

#define	DDR_CR26_AGECNT_SHIFT 0

#define	DDR_CR26_AGECNT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR26_AGECNT_SHIFT))&DDR_CR26_AGECNT_MASK)

#define	DDR_CR26_CMDAGE_MASK 0xFF00u

#define	DDR_CR26_CMDAGE_SHIFT 8

#define	DDR_CR26_CMDAGE(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR26_CMDAGE_SHIFT))&DDR_CR26_CMDAGE_MASK)

#define	DDR_CR26_ADDCOL_MASK 0x10000u

#define	DDR_CR26_ADDCOL_SHIFT 16

#define	DDR_CR26_BNKSPT_MASK 0x1000000u

#define	DDR_CR26_BNKSPT_SHIFT 24

#define	DDR_CR27_PLEN_MASK 0x1u

#define	DDR_CR27_PLEN_SHIFT 0

#define	DDR_CR27_PRIEN_MASK 0x100u

#define	DDR_CR27_PRIEN_SHIFT 8

#define	DDR_CR27_RWEN_MASK 0x10000u

#define	DDR_CR27_RWEN_SHIFT 16

#define	DDR_CR27_SWPEN_MASK 0x1000000u

#define	DDR_CR27_SWPEN_SHIFT 24

#define	DDR_CR28_CSMAP_MASK 0x1u

#define	DDR_CR28_CSMAP_SHIFT 0

#define	DDR_CR28_REDUC_MASK 0x100u

#define	DDR_CR28_REDUC_SHIFT 8

#define	DDR_CR28_BIGEND_MASK 0x10000u

#define	DDR_CR28_BIGEND_SHIFT 16

#define	DDR_CR28_CMDLATR_MASK 0x1000000u

#define	DDR_CR28_CMDLATR_SHIFT 24

#define	DDR_CR29_WRLATR_MASK 0x1u

#define	DDR_CR29_WRLATR_SHIFT 0

#define	DDR_CR29_FSTWR_MASK 0x100u

#define	DDR_CR29_FSTWR_SHIFT 8

#define	DDR_CR29_QFULL_MASK 0x30000u

#define	DDR_CR29_QFULL_SHIFT 16

#define	DDR_CR29_QFULL(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR29_QFULL_SHIFT))&DDR_CR29_QFULL_MASK)

#define	DDR_CR29_RESYNC_MASK 0x1000000u

#define	DDR_CR29_RESYNC_SHIFT 24

#define	DDR_CR30_RSYNCRF_MASK 0x1u

#define	DDR_CR30_RSYNCRF_SHIFT 0

#define	DDR_CR30_INTSTAT_MASK 0x1FF00u

#define	DDR_CR30_INTSTAT_SHIFT 8

#define	DDR_CR30_INTSTAT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR30_INTSTAT_SHIFT))&DDR_CR30_INTSTAT_MASK)

#define	DDR_CR30_INTACK_MASK 0xFF000000u

#define	DDR_CR30_INTACK_SHIFT 24

#define	DDR_CR30_INTACK(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR30_INTACK_SHIFT))&DDR_CR30_INTACK_MASK)

#define	DDR_CR31_INTMASK_MASK 0x1FFu

#define	DDR_CR31_INTMASK_SHIFT 0

#define	DDR_CR31_INTMASK(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR31_INTMASK_SHIFT))&DDR_CR31_INTMASK_MASK)

#define	DDR_CR32_OORAD_MASK 0xFFFFFFFFu

#define	DDR_CR32_OORAD_SHIFT 0

#define	DDR_CR32_OORAD(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR32_OORAD_SHIFT))&DDR_CR32_OORAD_MASK)

#define	DDR_CR33_OORLEN_MASK 0x3FFu

#define	DDR_CR33_OORLEN_SHIFT 0

#define	DDR_CR33_OORLEN(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR33_OORLEN_SHIFT))&DDR_CR33_OORLEN_MASK)

#define	DDR_CR33_OORTYP_MASK 0x3F0000u

#define	DDR_CR33_OORTYP_SHIFT 16

#define	DDR_CR33_OORTYP(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR33_OORTYP_SHIFT))&DDR_CR33_OORTYP_MASK)

#define	DDR_CR33_OORID_MASK 0x3000000u

#define	DDR_CR33_OORID_SHIFT 24

#define	DDR_CR33_OORID(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR33_OORID_SHIFT))&DDR_CR33_OORID_MASK)

#define	DDR_CR34_ODTRDC_MASK 0x1u

#define	DDR_CR34_ODTRDC_SHIFT 0

#define	DDR_CR34_ODTWRCS_MASK 0x100u

#define	DDR_CR34_ODTWRCS_SHIFT 8

#define	DDR_CR35_R2WSMCS_MASK 0xFu

#define	DDR_CR35_R2WSMCS_SHIFT 0

#define	DDR_CR35_R2WSMCS(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR35_R2WSMCS_SHIFT))&DDR_CR35_R2WSMCS_MASK)

#define	DDR_CR35_W2RSMCS_MASK 0xF00u

#define	DDR_CR35_W2RSMCS_SHIFT 8

#define	DDR_CR35_W2RSMCS(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR35_W2RSMCS_SHIFT))&DDR_CR35_W2RSMCS_MASK)

#define	DDR_CR36_Not_Used_MASK 0xFFFFu

#define	DDR_CR36_Not_Used_SHIFT 0

#define	DDR_CR36_Not_Used(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR36_Not_Used_SHIFT))&DDR_CR36_Not_Used_MASK)

#define	DDR_CR36_NOT_USED_MASK 0xFFFF0000u

#define	DDR_CR36_NOT_USED_SHIFT 16

#define	DDR_CR36_NOT_USED(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR36_NOT_USED_SHIFT))&DDR_CR36_NOT_USED_MASK)

#define	DDR_CR37_R2RSAME_MASK 0x7u

#define	DDR_CR37_R2RSAME_SHIFT 0

#define	DDR_CR37_R2RSAME(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR37_R2RSAME_SHIFT))&DDR_CR37_R2RSAME_MASK)

#define	DDR_CR37_R2WSAME_MASK 0x700u

#define	DDR_CR37_R2WSAME_SHIFT 8

#define	DDR_CR37_R2WSAME(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR37_R2WSAME_SHIFT))&DDR_CR37_R2WSAME_MASK)

#define	DDR_CR37_W2RSAME_MASK 0x70000u

#define	DDR_CR37_W2RSAME_SHIFT 16

#define	DDR_CR37_W2RSAME(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR37_W2RSAME_SHIFT))&DDR_CR37_W2RSAME_MASK)

#define	DDR_CR37_W2WSAME_MASK 0x7000000u

#define	DDR_CR37_W2WSAME_SHIFT 24

#define	DDR_CR37_W2WSAME(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR37_W2WSAME_SHIFT))&DDR_CR37_W2WSAME_MASK)

#define	DDR_CR38_PDNCS_MASK 0x1Fu

#define	DDR_CR38_PDNCS_SHIFT 0

#define	DDR_CR38_PDNCS(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR38_PDNCS_SHIFT))&DDR_CR38_PDNCS_MASK)

#define	DDR_CR38_PUPCS_MASK 0x1F00u

#define	DDR_CR38_PUPCS_SHIFT 8

#define	DDR_CR38_PUPCS(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR38_PUPCS_SHIFT))&DDR_CR38_PUPCS_MASK)

#define	DDR_CR38_PWRCNT_MASK 0x7FF0000u

#define	DDR_CR38_PWRCNT_SHIFT 16

#define	DDR_CR38_PWRCNT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR38_PWRCNT_SHIFT))&DDR_CR38_PWRCNT_MASK)

#define	DDR_CR39_P0RDCNT_MASK 0x7FFu

#define	DDR_CR39_P0RDCNT_SHIFT 0

#define	DDR_CR39_P0RDCNT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR39_P0RDCNT_SHIFT))&DDR_CR39_P0RDCNT_MASK)

#define	DDR_CR39_RP0_MASK 0x30000u

#define	DDR_CR39_RP0_SHIFT 16

#define	DDR_CR39_RP0(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR39_RP0_SHIFT))&DDR_CR39_RP0_MASK)

#define	DDR_CR39_WP0_MASK 0x3000000u

#define	DDR_CR39_WP0_SHIFT 24

#define	DDR_CR39_WP0(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR39_WP0_SHIFT))&DDR_CR39_WP0_MASK)

#define	DDR_CR40_P0TYP_MASK 0x3u

#define	DDR_CR40_P0TYP_SHIFT 0

#define	DDR_CR40_P0TYP(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR40_P0TYP_SHIFT))&DDR_CR40_P0TYP_MASK)

#define	DDR_CR40_P1WRCNT_MASK 0x7FF00u

#define	DDR_CR40_P1WRCNT_SHIFT 8

#define	DDR_CR40_P1WRCNT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR40_P1WRCNT_SHIFT))&DDR_CR40_P1WRCNT_MASK)

#define	DDR_CR41_P1RDCNT_MASK 0x7FFu

#define	DDR_CR41_P1RDCNT_SHIFT 0

#define	DDR_CR41_P1RDCNT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR41_P1RDCNT_SHIFT))&DDR_CR41_P1RDCNT_MASK)

#define	DDR_CR41_RP1_MASK 0x30000u

#define	DDR_CR41_RP1_SHIFT 16

#define	DDR_CR41_RP1(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR41_RP1_SHIFT))&DDR_CR41_RP1_MASK)

#define	DDR_CR41_WP1_MASK 0x3000000u

#define	DDR_CR41_WP1_SHIFT 24

#define	DDR_CR41_WP1(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR41_WP1_SHIFT))&DDR_CR41_WP1_MASK)

#define	DDR_CR42_P1TYP_MASK 0x3u

#define	DDR_CR42_P1TYP_SHIFT 0

#define	DDR_CR42_P1TYP(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR42_P1TYP_SHIFT))&DDR_CR42_P1TYP_MASK)

#define	DDR_CR42_P2WRCNT_MASK 0x7FF00u

#define	DDR_CR42_P2WRCNT_SHIFT 8

#define	DDR_CR42_P2WRCNT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR42_P2WRCNT_SHIFT))&DDR_CR42_P2WRCNT_MASK)

#define	DDR_CR43_P2RDCNT_MASK 0x7FFu

#define	DDR_CR43_P2RDCNT_SHIFT 0

#define	DDR_CR43_P2RDCNT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR43_P2RDCNT_SHIFT))&DDR_CR43_P2RDCNT_MASK)

#define	DDR_CR43_RP2_MASK 0x30000u

#define	DDR_CR43_RP2_SHIFT 16

#define	DDR_CR43_RP2(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR43_RP2_SHIFT))&DDR_CR43_RP2_MASK)

#define	DDR_CR43_WP2_MASK 0x3000000u

#define	DDR_CR43_WP2_SHIFT 24

#define	DDR_CR43_WP2(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR43_WP2_SHIFT))&DDR_CR43_WP2_MASK)

#define	DDR_CR44_P2TYP_MASK 0x3u

#define	DDR_CR44_P2TYP_SHIFT 0

#define	DDR_CR44_P2TYP(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR44_P2TYP_SHIFT))&DDR_CR44_P2TYP_MASK)

#define	DDR_CR44_WRRLAT_MASK 0x100u

#define	DDR_CR44_WRRLAT_SHIFT 8

#define	DDR_CR44_WRRSHARE_MASK 0x10000u

#define	DDR_CR44_WRRSHARE_SHIFT 16

#define	DDR_CR44_WRRERR_MASK 0xF000000u

#define	DDR_CR44_WRRERR_SHIFT 24

#define	DDR_CR44_WRRERR(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR44_WRRERR_SHIFT))&DDR_CR44_WRRERR_MASK)

#define	DDR_CR45_P0PRI0_MASK 0xFu

#define	DDR_CR45_P0PRI0_SHIFT 0

#define	DDR_CR45_P0PRI0(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR45_P0PRI0_SHIFT))&DDR_CR45_P0PRI0_MASK)

#define	DDR_CR45_P0PRI1_MASK 0xF00u

#define	DDR_CR45_P0PRI1_SHIFT 8

#define	DDR_CR45_P0PRI1(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR45_P0PRI1_SHIFT))&DDR_CR45_P0PRI1_MASK)

#define	DDR_CR45_P0PRI2_MASK 0xF0000u

#define	DDR_CR45_P0PRI2_SHIFT 16

#define	DDR_CR45_P0PRI2(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR45_P0PRI2_SHIFT))&DDR_CR45_P0PRI2_MASK)

#define	DDR_CR45_P0PRI3_MASK 0xF000000u

#define	DDR_CR45_P0PRI3_SHIFT 24

#define	DDR_CR45_P0PRI3(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR45_P0PRI3_SHIFT))&DDR_CR45_P0PRI3_MASK)

#define	DDR_CR46_P0ORD_MASK 0x3u

#define	DDR_CR46_P0ORD_SHIFT 0

#define	DDR_CR46_P0ORD(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR46_P0ORD_SHIFT))&DDR_CR46_P0ORD_MASK)

#define	DDR_CR46_P0PRIRLX_MASK 0x3FF00u

#define	DDR_CR46_P0PRIRLX_SHIFT 8

#define	DDR_CR46_P0PRIRLX(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR46_P0PRIRLX_SHIFT))&DDR_CR46_P0PRIRLX_MASK)

#define	DDR_CR46_P1PRI0_MASK 0xF000000u

#define	DDR_CR46_P1PRI0_SHIFT 24

#define	DDR_CR46_P1PRI0(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR46_P1PRI0_SHIFT))&DDR_CR46_P1PRI0_MASK)

#define	DDR_CR47_P1PRI1_MASK 0xFu

#define	DDR_CR47_P1PRI1_SHIFT 0

#define	DDR_CR47_P1PRI1(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR47_P1PRI1_SHIFT))&DDR_CR47_P1PRI1_MASK)

#define	DDR_CR47_P1PRI2_MASK 0xF00u

#define	DDR_CR47_P1PRI2_SHIFT 8

#define	DDR_CR47_P1PRI2(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR47_P1PRI2_SHIFT))&DDR_CR47_P1PRI2_MASK)

#define	DDR_CR47_P1PRI3_MASK 0xF0000u

#define	DDR_CR47_P1PRI3_SHIFT 16

#define	DDR_CR47_P1PRI3(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR47_P1PRI3_SHIFT))&DDR_CR47_P1PRI3_MASK)

#define	DDR_CR47_P1ORD_MASK 0x3000000u

#define	DDR_CR47_P1ORD_SHIFT 24

#define	DDR_CR47_P1ORD(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR47_P1ORD_SHIFT))&DDR_CR47_P1ORD_MASK)

#define	DDR_CR48_P1PRIRLX_MASK 0x3FFu

#define	DDR_CR48_P1PRIRLX_SHIFT 0

#define	DDR_CR48_P1PRIRLX(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR48_P1PRIRLX_SHIFT))&DDR_CR48_P1PRIRLX_MASK)

#define	DDR_CR48_P2PRI0_MASK 0xF0000u

#define	DDR_CR48_P2PRI0_SHIFT 16

#define	DDR_CR48_P2PRI0(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR48_P2PRI0_SHIFT))&DDR_CR48_P2PRI0_MASK)

#define	DDR_CR48_P2PRI1_MASK 0xF000000u

#define	DDR_CR48_P2PRI1_SHIFT 24

#define	DDR_CR48_P2PRI1(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR48_P2PRI1_SHIFT))&DDR_CR48_P2PRI1_MASK)

#define	DDR_CR49_P2PRI2_MASK 0xFu

#define	DDR_CR49_P2PRI2_SHIFT 0

#define	DDR_CR49_P2PRI2(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR49_P2PRI2_SHIFT))&DDR_CR49_P2PRI2_MASK)

#define	DDR_CR49_P2PRI3_MASK 0xF00u

#define	DDR_CR49_P2PRI3_SHIFT 8

#define	DDR_CR49_P2PRI3(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR49_P2PRI3_SHIFT))&DDR_CR49_P2PRI3_MASK)

#define	DDR_CR49_P2ORD_MASK 0x30000u

#define	DDR_CR49_P2ORD_SHIFT 16

#define	DDR_CR49_P2ORD(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR49_P2ORD_SHIFT))&DDR_CR49_P2ORD_MASK)

#define	DDR_CR50_P2PRIRLX_MASK 0x3FFu

#define	DDR_CR50_P2PRIRLX_SHIFT 0

#define	DDR_CR50_P2PRIRLX(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR50_P2PRIRLX_SHIFT))&DDR_CR50_P2PRIRLX_MASK)

#define	DDR_CR50_CLKSTATUS_MASK 0x10000u

#define	DDR_CR50_CLKSTATUS_SHIFT 16

#define	DDR_CR51_DLLRSTDLY_MASK 0xFFFFu

#define	DDR_CR51_DLLRSTDLY_SHIFT 0

#define	DDR_CR51_DLLRSTDLY(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR51_DLLRSTDLY_SHIFT))&DDR_CR51_DLLRSTDLY_MASK)

#define	DDR_CR51_DLLRADLY_MASK 0xFF0000u

#define	DDR_CR51_DLLRADLY_SHIFT 16

#define	DDR_CR51_DLLRADLY(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR51_DLLRADLY_SHIFT))&DDR_CR51_DLLRADLY_MASK)

#define	DDR_CR51_PHYWRLAT_MASK 0xF000000u

#define	DDR_CR51_PHYWRLAT_SHIFT 24

#define	DDR_CR51_PHYWRLAT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR51_PHYWRLAT_SHIFT))&DDR_CR51_PHYWRLAT_MASK)

#define	DDR_CR52_PYWRLTBS_MASK 0xFu

#define	DDR_CR52_PYWRLTBS_SHIFT 0

#define	DDR_CR52_PYWRLTBS(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR52_PYWRLTBS_SHIFT))&DDR_CR52_PYWRLTBS_MASK)

#define	DDR_CR52_PHYRDLAT_MASK 0xF00u

#define	DDR_CR52_PHYRDLAT_SHIFT 8

#define	DDR_CR52_PHYRDLAT(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR52_PHYRDLAT_SHIFT))&DDR_CR52_PHYRDLAT_MASK)

#define	DDR_CR52_RDDATAEN_MASK 0xF0000u

#define	DDR_CR52_RDDATAEN_SHIFT 16

#define	DDR_CR52_RDDATAEN(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR52_RDDATAEN_SHIFT))&DDR_CR52_RDDATAEN_MASK)

#define	DDR_CR52_RDDTENBAS_MASK 0xF000000u

#define	DDR_CR52_RDDTENBAS_SHIFT 24

#define	DDR_CR52_RDDTENBAS(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR52_RDDTENBAS_SHIFT))&DDR_CR52_RDDTENBAS_MASK)

#define	DDR_CR53_CLKDISCS_MASK 0x1u

#define	DDR_CR53_CLKDISCS_SHIFT 0

#define	DDR_CR53_CRTLUPDMN_MASK 0xF00u

#define	DDR_CR53_CRTLUPDMN_SHIFT 8

#define	DDR_CR53_CRTLUPDMN(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR53_CRTLUPDMN_SHIFT))&DDR_CR53_CRTLUPDMN_MASK)

#define	DDR_CR53_CTRLUPDMX_MASK 0x3FFF0000u

#define	DDR_CR53_CTRLUPDMX_SHIFT 16

#define	DDR_CR53_CTRLUPDMX(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR53_CTRLUPDMX_SHIFT))&DDR_CR53_CTRLUPDMX_MASK)

#define	DDR_CR54_PHYUPDTY0_MASK 0x3FFFu

#define	DDR_CR54_PHYUPDTY0_SHIFT 0

#define	DDR_CR54_PHYUPDTY0(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR54_PHYUPDTY0_SHIFT))&DDR_CR54_PHYUPDTY0_MASK)

#define	DDR_CR54_PHYUPDTY1_MASK 0x3FFF0000u

#define	DDR_CR54_PHYUPDTY1_SHIFT 16

#define	DDR_CR54_PHYUPDTY1(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR54_PHYUPDTY1_SHIFT))&DDR_CR54_PHYUPDTY1_MASK)

#define	DDR_CR55_PHYUPDTY2_MASK 0x3FFFu

#define	DDR_CR55_PHYUPDTY2_SHIFT 0

#define	DDR_CR55_PHYUPDTY2(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR55_PHYUPDTY2_SHIFT))&DDR_CR55_PHYUPDTY2_MASK)

#define	DDR_CR55_PHYUPDTY3_MASK 0x3FFF0000u

#define	DDR_CR55_PHYUPDTY3_SHIFT 16

#define	DDR_CR55_PHYUPDTY3(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR55_PHYUPDTY3_SHIFT))&DDR_CR55_PHYUPDTY3_MASK)

#define	DDR_CR56_PHYUPDRESP_MASK 0x3FFFu

#define	DDR_CR56_PHYUPDRESP_SHIFT 0

#define	DDR_CR56_PHYUPDRESP(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR56_PHYUPDRESP_SHIFT))&DDR_CR56_PHYUPDRESP_MASK)

#define	DDR_CR56_RDLATADJ_MASK 0xF0000u

#define	DDR_CR56_RDLATADJ_SHIFT 16

#define	DDR_CR56_RDLATADJ(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR56_RDLATADJ_SHIFT))&DDR_CR56_RDLATADJ_MASK)

#define	DDR_CR56_WRLATADJ_MASK 0xF000000u

#define	DDR_CR56_WRLATADJ_SHIFT 24

#define	DDR_CR56_WRLATADJ(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR56_WRLATADJ_SHIFT))&DDR_CR56_WRLATADJ_MASK)

#define	DDR_CR57_CMDDLY_MASK 0xFu

#define	DDR_CR57_CMDDLY_SHIFT 0

#define	DDR_CR57_CMDDLY(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR57_CMDDLY_SHIFT))&DDR_CR57_CMDDLY_MASK)

#define	DDR_CR57_CLKDISDLY_MASK 0x700u

#define	DDR_CR57_CLKDISDLY_SHIFT 8

#define	DDR_CR57_CLKDISDLY(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR57_CLKDISDLY_SHIFT))&DDR_CR57_CLKDISDLY_MASK)

#define	DDR_CR57_CLKENDLY_MASK 0xF0000u

#define	DDR_CR57_CLKENDLY_SHIFT 16

#define	DDR_CR57_CLKENDLY(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR57_CLKENDLY_SHIFT))&DDR_CR57_CLKENDLY_MASK)

#define	DDR_CR57_ODTALTEN_MASK 0x1000000u

#define	DDR_CR57_ODTALTEN_SHIFT 24

#define	DDR_CR58_Not_Used_MASK 0xFFFFu

#define	DDR_CR58_Not_Used_SHIFT 0

#define	DDR_CR58_Not_Used(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR58_Not_Used_SHIFT))&DDR_CR58_Not_Used_MASK)

#define	DDR_CR58_NOT_USED_MASK 0xFFFF0000u

#define	DDR_CR58_NOT_USED_SHIFT 16

#define	DDR_CR58_NOT_USED(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR58_NOT_USED_SHIFT))&DDR_CR58_NOT_USED_MASK)

#define	DDR_CR59_Not_Used_MASK 0xFFFFu

#define	DDR_CR59_Not_Used_SHIFT 0

#define	DDR_CR59_Not_Used(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR59_Not_Used_SHIFT))&DDR_CR59_Not_Used_MASK)

#define	DDR_CR59_NOT_USED_MASK 0xFFFF0000u

#define	DDR_CR59_NOT_USED_SHIFT 16

#define	DDR_CR59_NOT_USED(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR59_NOT_USED_SHIFT))&DDR_CR59_NOT_USED_MASK)

#define	DDR_CR60_Not_Used_MASK 0xFFFFu

#define	DDR_CR60_Not_Used_SHIFT 0

#define	DDR_CR60_Not_Used(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR60_Not_Used_SHIFT))&DDR_CR60_Not_Used_MASK)

#define	DDR_CR60_NOT_USED_MASK 0xFFFF0000u

#define	DDR_CR60_NOT_USED_SHIFT 16

#define	DDR_CR60_NOT_USED(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR60_NOT_USED_SHIFT))&DDR_CR60_NOT_USED_MASK)

#define	DDR_CR61_Not_Used_MASK 0xFFFFu

#define	DDR_CR61_Not_Used_SHIFT 0

#define	DDR_CR61_Not_Used(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR61_Not_Used_SHIFT))&DDR_CR61_Not_Used_MASK)

#define	DDR_CR61_NOT_USED_MASK 0xFFFF0000u

#define	DDR_CR61_NOT_USED_SHIFT 16

#define	DDR_CR61_NOT_USED(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR61_NOT_USED_SHIFT))&DDR_CR61_NOT_USED_MASK)

#define	DDR_CR62_Not_Used_MASK 0xFFFFu

#define	DDR_CR62_Not_Used_SHIFT 0

#define	DDR_CR62_Not_Used(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR62_Not_Used_SHIFT))&DDR_CR62_Not_Used_MASK)

#define	DDR_CR62_NOT_USED_MASK 0xFFFF0000u

#define	DDR_CR62_NOT_USED_SHIFT 16

#define	DDR_CR62_NOT_USED(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR62_NOT_USED_SHIFT))&DDR_CR62_NOT_USED_MASK)

#define	DDR_CR63_Not_Used_MASK 0xFFFFu

#define	DDR_CR63_Not_Used_SHIFT 0

#define	DDR_CR63_Not_Used(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR63_Not_Used_SHIFT))&DDR_CR63_Not_Used_MASK)

#define	DDR_CR63_NOT_USED_MASK 0xFFFF0000u

#define	DDR_CR63_NOT_USED_SHIFT 16

#define	DDR_CR63_NOT_USED(x) (((uint32_t)(((uint32_t)(x))<<DDR_CR63_NOT_USED_SHIFT))&DDR_CR63_NOT_USED_MASK)

#define	DDR_RCR_RST_MASK 0x40000000u

#define	DDR_RCR_RST_SHIFT 30

#define	DDR_PAD_CTRL_SPARE_DLY_CTRL_MASK 0xFu

#define	DDR_PAD_CTRL_SPARE_DLY_CTRL_SHIFT 0

#define	DDR_PAD_CTRL_SPARE_DLY_CTRL(x) (((uint32_t)(((uint32_t)(x))<<DDR_PAD_CTRL_SPARE_DLY_CTRL_SHIFT))&DDR_PAD_CTRL_SPARE_DLY_CTRL_MASK)

#define	DDR_PAD_CTRL_PAD_ODT_CS0_MASK 0x3000000u

#define	DDR_PAD_CTRL_PAD_ODT_CS0_SHIFT 24

#define	DDR_PAD_CTRL_PAD_ODT_CS0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PAD_CTRL_PAD_ODT_CS0_SHIFT))&DDR_PAD_CTRL_PAD_ODT_CS0_MASK)

#define	DDR_BASE_PTR ((DDR_MemMapPtr)0x400AE000u)

#define	DDR_BASE_PTRS { DDR_BASE_PTR }

#define	DDR_CR00 DDR_CR00_REG(DDR_BASE_PTR)

#define	DDR_CR01 DDR_CR01_REG(DDR_BASE_PTR)

#define	DDR_CR02 DDR_CR02_REG(DDR_BASE_PTR)

#define	DDR_CR03 DDR_CR03_REG(DDR_BASE_PTR)

#define	DDR_CR04 DDR_CR04_REG(DDR_BASE_PTR)

#define	DDR_CR05 DDR_CR05_REG(DDR_BASE_PTR)

#define	DDR_CR06 DDR_CR06_REG(DDR_BASE_PTR)

#define	DDR_CR07 DDR_CR07_REG(DDR_BASE_PTR)

#define	DDR_CR08 DDR_CR08_REG(DDR_BASE_PTR)

#define	DDR_CR09 DDR_CR09_REG(DDR_BASE_PTR)

#define	DDR_CR10 DDR_CR10_REG(DDR_BASE_PTR)

#define	DDR_CR11 DDR_CR11_REG(DDR_BASE_PTR)

#define	DDR_CR12 DDR_CR12_REG(DDR_BASE_PTR)

#define	DDR_CR13 DDR_CR13_REG(DDR_BASE_PTR)

#define	DDR_CR14 DDR_CR14_REG(DDR_BASE_PTR)

#define	DDR_CR15 DDR_CR15_REG(DDR_BASE_PTR)

#define	DDR_CR16 DDR_CR16_REG(DDR_BASE_PTR)

#define	DDR_CR17 DDR_CR17_REG(DDR_BASE_PTR)

#define	DDR_CR18 DDR_CR18_REG(DDR_BASE_PTR)

#define	DDR_CR19 DDR_CR19_REG(DDR_BASE_PTR)

#define	DDR_CR20 DDR_CR20_REG(DDR_BASE_PTR)

#define	DDR_CR21 DDR_CR21_REG(DDR_BASE_PTR)

#define	DDR_CR22 DDR_CR22_REG(DDR_BASE_PTR)

#define	DDR_CR23 DDR_CR23_REG(DDR_BASE_PTR)

#define	DDR_CR24 DDR_CR24_REG(DDR_BASE_PTR)

#define	DDR_CR25 DDR_CR25_REG(DDR_BASE_PTR)

#define	DDR_CR26 DDR_CR26_REG(DDR_BASE_PTR)

#define	DDR_CR27 DDR_CR27_REG(DDR_BASE_PTR)

#define	DDR_CR28 DDR_CR28_REG(DDR_BASE_PTR)

#define	DDR_CR29 DDR_CR29_REG(DDR_BASE_PTR)

#define	DDR_CR30 DDR_CR30_REG(DDR_BASE_PTR)

#define	DDR_CR31 DDR_CR31_REG(DDR_BASE_PTR)

#define	DDR_CR32 DDR_CR32_REG(DDR_BASE_PTR)

#define	DDR_CR33 DDR_CR33_REG(DDR_BASE_PTR)

#define	DDR_CR34 DDR_CR34_REG(DDR_BASE_PTR)

#define	DDR_CR35 DDR_CR35_REG(DDR_BASE_PTR)

#define	DDR_CR36 DDR_CR36_REG(DDR_BASE_PTR)

#define	DDR_CR37 DDR_CR37_REG(DDR_BASE_PTR)

#define	DDR_CR38 DDR_CR38_REG(DDR_BASE_PTR)

#define	DDR_CR39 DDR_CR39_REG(DDR_BASE_PTR)

#define	DDR_CR40 DDR_CR40_REG(DDR_BASE_PTR)

#define	DDR_CR41 DDR_CR41_REG(DDR_BASE_PTR)

#define	DDR_CR42 DDR_CR42_REG(DDR_BASE_PTR)

#define	DDR_CR43 DDR_CR43_REG(DDR_BASE_PTR)

#define	DDR_CR44 DDR_CR44_REG(DDR_BASE_PTR)

#define	DDR_CR45 DDR_CR45_REG(DDR_BASE_PTR)

#define	DDR_CR46 DDR_CR46_REG(DDR_BASE_PTR)

#define	DDR_CR47 DDR_CR47_REG(DDR_BASE_PTR)

#define	DDR_CR48 DDR_CR48_REG(DDR_BASE_PTR)

#define	DDR_CR49 DDR_CR49_REG(DDR_BASE_PTR)

#define	DDR_CR50 DDR_CR50_REG(DDR_BASE_PTR)

#define	DDR_CR51 DDR_CR51_REG(DDR_BASE_PTR)

#define	DDR_CR52 DDR_CR52_REG(DDR_BASE_PTR)

#define	DDR_CR53 DDR_CR53_REG(DDR_BASE_PTR)

#define	DDR_CR54 DDR_CR54_REG(DDR_BASE_PTR)

#define	DDR_CR55 DDR_CR55_REG(DDR_BASE_PTR)

#define	DDR_CR56 DDR_CR56_REG(DDR_BASE_PTR)

#define	DDR_CR57 DDR_CR57_REG(DDR_BASE_PTR)

#define	DDR_CR58 DDR_CR58_REG(DDR_BASE_PTR)

#define	DDR_CR59 DDR_CR59_REG(DDR_BASE_PTR)

#define	DDR_CR60 DDR_CR60_REG(DDR_BASE_PTR)

#define	DDR_CR61 DDR_CR61_REG(DDR_BASE_PTR)

#define	DDR_CR62 DDR_CR62_REG(DDR_BASE_PTR)

#define	DDR_CR63 DDR_CR63_REG(DDR_BASE_PTR)

#define	DDR_RCR DDR_RCR_REG(DDR_BASE_PTR)

#define	DDR_PAD_CTRL DDR_PAD_CTRL_REG(DDR_BASE_PTR)

#define	DMA_CR_REG(base) ((base)->CR)

#define	DMA_ES_REG(base) ((base)->ES)

#define	DMA_ERQ_REG(base) ((base)->ERQ)

#define	DMA_EEI_REG(base) ((base)->EEI)

#define	DMA_CEEI_REG(base) ((base)->CEEI)

#define	DMA_SEEI_REG(base) ((base)->SEEI)

#define	DMA_CERQ_REG(base) ((base)->CERQ)

#define	DMA_SERQ_REG(base) ((base)->SERQ)

#define	DMA_CDNE_REG(base) ((base)->CDNE)

#define	DMA_SSRT_REG(base) ((base)->SSRT)

#define	DMA_CERR_REG(base) ((base)->CERR)

#define	DMA_CINT_REG(base) ((base)->CINT)

#define	DMA_INT_REG(base) ((base)->INT)

#define	DMA_ERR_REG(base) ((base)->ERR)

#define	DMA_HRS_REG(base) ((base)->HRS)

#define	DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)

#define	DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)

#define	DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)

#define	DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)

#define	DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)

#define	DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)

#define	DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)

#define	DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)

#define	DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)

#define	DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)

#define	DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)

#define	DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)

#define	DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)

#define	DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)

#define	DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)

#define	DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)

#define	DMA_DCHPRI19_REG(base) ((base)->DCHPRI19)

#define	DMA_DCHPRI18_REG(base) ((base)->DCHPRI18)

#define	DMA_DCHPRI17_REG(base) ((base)->DCHPRI17)

#define	DMA_DCHPRI16_REG(base) ((base)->DCHPRI16)

#define	DMA_DCHPRI23_REG(base) ((base)->DCHPRI23)

#define	DMA_DCHPRI22_REG(base) ((base)->DCHPRI22)

#define	DMA_DCHPRI21_REG(base) ((base)->DCHPRI21)

#define	DMA_DCHPRI20_REG(base) ((base)->DCHPRI20)

#define	DMA_DCHPRI27_REG(base) ((base)->DCHPRI27)

#define	DMA_DCHPRI26_REG(base) ((base)->DCHPRI26)

#define	DMA_DCHPRI25_REG(base) ((base)->DCHPRI25)

#define	DMA_DCHPRI24_REG(base) ((base)->DCHPRI24)

#define	DMA_DCHPRI31_REG(base) ((base)->DCHPRI31)

#define	DMA_DCHPRI30_REG(base) ((base)->DCHPRI30)

#define	DMA_DCHPRI29_REG(base) ((base)->DCHPRI29)

#define	DMA_DCHPRI28_REG(base) ((base)->DCHPRI28)

#define	DMA_SADDR_REG(base, index) ((base)->TCD[index].SADDR)

#define	DMA_SOFF_REG(base, index) ((base)->TCD[index].SOFF)

#define	DMA_ATTR_REG(base, index) ((base)->TCD[index].ATTR)

#define	DMA_NBYTES_MLNO_REG(base, index) ((base)->TCD[index].NBYTES_MLNO)

#define	DMA_NBYTES_MLOFFNO_REG(base, index) ((base)->TCD[index].NBYTES_MLOFFNO)

#define	DMA_NBYTES_MLOFFYES_REG(base, index) ((base)->TCD[index].NBYTES_MLOFFYES)

#define	DMA_SLAST_REG(base, index) ((base)->TCD[index].SLAST)

#define	DMA_DADDR_REG(base, index) ((base)->TCD[index].DADDR)

#define	DMA_DOFF_REG(base, index) ((base)->TCD[index].DOFF)

#define	DMA_CITER_ELINKNO_REG(base, index) ((base)->TCD[index].CITER_ELINKNO)

#define	DMA_CITER_ELINKYES_REG(base, index) ((base)->TCD[index].CITER_ELINKYES)

#define	DMA_DLAST_SGA_REG(base, index) ((base)->TCD[index].DLAST_SGA)

#define	DMA_CSR_REG(base, index) ((base)->TCD[index].CSR)

#define	DMA_BITER_ELINKNO_REG(base, index) ((base)->TCD[index].BITER_ELINKNO)

#define	DMA_BITER_ELINKYES_REG(base, index) ((base)->TCD[index].BITER_ELINKYES)

#define	DMA_CR_EDBG_MASK 0x2u

#define	DMA_CR_EDBG_SHIFT 1

#define	DMA_CR_ERCA_MASK 0x4u

#define	DMA_CR_ERCA_SHIFT 2

#define	DMA_CR_ERGA_MASK 0x8u

#define	DMA_CR_ERGA_SHIFT 3

#define	DMA_CR_HOE_MASK 0x10u

#define	DMA_CR_HOE_SHIFT 4

#define	DMA_CR_HALT_MASK 0x20u

#define	DMA_CR_HALT_SHIFT 5

#define	DMA_CR_CLM_MASK 0x40u

#define	DMA_CR_CLM_SHIFT 6

#define	DMA_CR_EMLM_MASK 0x80u

#define	DMA_CR_EMLM_SHIFT 7

#define	DMA_CR_GRP0PRI_MASK 0x300u

#define	DMA_CR_GRP0PRI_SHIFT 8

#define	DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_GRP0PRI_SHIFT))&DMA_CR_GRP0PRI_MASK)

#define	DMA_CR_GRP1PRI_MASK 0xC00u

#define	DMA_CR_GRP1PRI_SHIFT 10

#define	DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_GRP1PRI_SHIFT))&DMA_CR_GRP1PRI_MASK)

#define	DMA_CR_ECX_MASK 0x10000u

#define	DMA_CR_ECX_SHIFT 16

#define	DMA_CR_CX_MASK 0x20000u

#define	DMA_CR_CX_SHIFT 17

#define	DMA_ES_DBE_MASK 0x1u

#define	DMA_ES_DBE_SHIFT 0

#define	DMA_ES_SBE_MASK 0x2u

#define	DMA_ES_SBE_SHIFT 1

#define	DMA_ES_SGE_MASK 0x4u

#define	DMA_ES_SGE_SHIFT 2

#define	DMA_ES_NCE_MASK 0x8u

#define	DMA_ES_NCE_SHIFT 3

#define	DMA_ES_DOE_MASK 0x10u

#define	DMA_ES_DOE_SHIFT 4

#define	DMA_ES_DAE_MASK 0x20u

#define	DMA_ES_DAE_SHIFT 5

#define	DMA_ES_SOE_MASK 0x40u

#define	DMA_ES_SOE_SHIFT 6

#define	DMA_ES_SAE_MASK 0x80u

#define	DMA_ES_SAE_SHIFT 7

#define	DMA_ES_ERRCHN_MASK 0x1F00u

#define	DMA_ES_ERRCHN_SHIFT 8

#define	DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)

#define	DMA_ES_CPE_MASK 0x4000u

#define	DMA_ES_CPE_SHIFT 14

#define	DMA_ES_GPE_MASK 0x8000u

#define	DMA_ES_GPE_SHIFT 15

#define	DMA_ES_ECX_MASK 0x10000u

#define	DMA_ES_ECX_SHIFT 16

#define	DMA_ES_VLD_MASK 0x80000000u

#define	DMA_ES_VLD_SHIFT 31

#define	DMA_ERQ_ERQ0_MASK 0x1u

#define	DMA_ERQ_ERQ0_SHIFT 0

#define	DMA_ERQ_ERQ1_MASK 0x2u

#define	DMA_ERQ_ERQ1_SHIFT 1

#define	DMA_ERQ_ERQ2_MASK 0x4u

#define	DMA_ERQ_ERQ2_SHIFT 2

#define	DMA_ERQ_ERQ3_MASK 0x8u

#define	DMA_ERQ_ERQ3_SHIFT 3

#define	DMA_ERQ_ERQ4_MASK 0x10u

#define	DMA_ERQ_ERQ4_SHIFT 4

#define	DMA_ERQ_ERQ5_MASK 0x20u

#define	DMA_ERQ_ERQ5_SHIFT 5

#define	DMA_ERQ_ERQ6_MASK 0x40u

#define	DMA_ERQ_ERQ6_SHIFT 6

#define	DMA_ERQ_ERQ7_MASK 0x80u

#define	DMA_ERQ_ERQ7_SHIFT 7

#define	DMA_ERQ_ERQ8_MASK 0x100u

#define	DMA_ERQ_ERQ8_SHIFT 8

#define	DMA_ERQ_ERQ9_MASK 0x200u

#define	DMA_ERQ_ERQ9_SHIFT 9

#define	DMA_ERQ_ERQ10_MASK 0x400u

#define	DMA_ERQ_ERQ10_SHIFT 10

#define	DMA_ERQ_ERQ11_MASK 0x800u

#define	DMA_ERQ_ERQ11_SHIFT 11

#define	DMA_ERQ_ERQ12_MASK 0x1000u

#define	DMA_ERQ_ERQ12_SHIFT 12

#define	DMA_ERQ_ERQ13_MASK 0x2000u

#define	DMA_ERQ_ERQ13_SHIFT 13

#define	DMA_ERQ_ERQ14_MASK 0x4000u

#define	DMA_ERQ_ERQ14_SHIFT 14

#define	DMA_ERQ_ERQ15_MASK 0x8000u

#define	DMA_ERQ_ERQ15_SHIFT 15

#define	DMA_ERQ_ERQ16_MASK 0x10000u

#define	DMA_ERQ_ERQ16_SHIFT 16

#define	DMA_ERQ_ERQ17_MASK 0x20000u

#define	DMA_ERQ_ERQ17_SHIFT 17

#define	DMA_ERQ_ERQ18_MASK 0x40000u

#define	DMA_ERQ_ERQ18_SHIFT 18

#define	DMA_ERQ_ERQ19_MASK 0x80000u

#define	DMA_ERQ_ERQ19_SHIFT 19

#define	DMA_ERQ_ERQ20_MASK 0x100000u

#define	DMA_ERQ_ERQ20_SHIFT 20

#define	DMA_ERQ_ERQ21_MASK 0x200000u

#define	DMA_ERQ_ERQ21_SHIFT 21

#define	DMA_ERQ_ERQ22_MASK 0x400000u

#define	DMA_ERQ_ERQ22_SHIFT 22

#define	DMA_ERQ_ERQ23_MASK 0x800000u

#define	DMA_ERQ_ERQ23_SHIFT 23

#define	DMA_ERQ_ERQ24_MASK 0x1000000u

#define	DMA_ERQ_ERQ24_SHIFT 24

#define	DMA_ERQ_ERQ25_MASK 0x2000000u

#define	DMA_ERQ_ERQ25_SHIFT 25

#define	DMA_ERQ_ERQ26_MASK 0x4000000u

#define	DMA_ERQ_ERQ26_SHIFT 26

#define	DMA_ERQ_ERQ27_MASK 0x8000000u

#define	DMA_ERQ_ERQ27_SHIFT 27

#define	DMA_ERQ_ERQ28_MASK 0x10000000u

#define	DMA_ERQ_ERQ28_SHIFT 28

#define	DMA_ERQ_ERQ29_MASK 0x20000000u

#define	DMA_ERQ_ERQ29_SHIFT 29

#define	DMA_ERQ_ERQ30_MASK 0x40000000u

#define	DMA_ERQ_ERQ30_SHIFT 30

#define	DMA_ERQ_ERQ31_MASK 0x80000000u

#define	DMA_ERQ_ERQ31_SHIFT 31

#define	DMA_EEI_EEI0_MASK 0x1u

#define	DMA_EEI_EEI0_SHIFT 0

#define	DMA_EEI_EEI1_MASK 0x2u

#define	DMA_EEI_EEI1_SHIFT 1

#define	DMA_EEI_EEI2_MASK 0x4u

#define	DMA_EEI_EEI2_SHIFT 2

#define	DMA_EEI_EEI3_MASK 0x8u

#define	DMA_EEI_EEI3_SHIFT 3

#define	DMA_EEI_EEI4_MASK 0x10u

#define	DMA_EEI_EEI4_SHIFT 4

#define	DMA_EEI_EEI5_MASK 0x20u

#define	DMA_EEI_EEI5_SHIFT 5

#define	DMA_EEI_EEI6_MASK 0x40u

#define	DMA_EEI_EEI6_SHIFT 6

#define	DMA_EEI_EEI7_MASK 0x80u

#define	DMA_EEI_EEI7_SHIFT 7

#define	DMA_EEI_EEI8_MASK 0x100u

#define	DMA_EEI_EEI8_SHIFT 8

#define	DMA_EEI_EEI9_MASK 0x200u

#define	DMA_EEI_EEI9_SHIFT 9

#define	DMA_EEI_EEI10_MASK 0x400u

#define	DMA_EEI_EEI10_SHIFT 10

#define	DMA_EEI_EEI11_MASK 0x800u

#define	DMA_EEI_EEI11_SHIFT 11

#define	DMA_EEI_EEI12_MASK 0x1000u

#define	DMA_EEI_EEI12_SHIFT 12

#define	DMA_EEI_EEI13_MASK 0x2000u

#define	DMA_EEI_EEI13_SHIFT 13

#define	DMA_EEI_EEI14_MASK 0x4000u

#define	DMA_EEI_EEI14_SHIFT 14

#define	DMA_EEI_EEI15_MASK 0x8000u

#define	DMA_EEI_EEI15_SHIFT 15

#define	DMA_EEI_EEI16_MASK 0x10000u

#define	DMA_EEI_EEI16_SHIFT 16

#define	DMA_EEI_EEI17_MASK 0x20000u

#define	DMA_EEI_EEI17_SHIFT 17

#define	DMA_EEI_EEI18_MASK 0x40000u

#define	DMA_EEI_EEI18_SHIFT 18

#define	DMA_EEI_EEI19_MASK 0x80000u

#define	DMA_EEI_EEI19_SHIFT 19

#define	DMA_EEI_EEI20_MASK 0x100000u

#define	DMA_EEI_EEI20_SHIFT 20

#define	DMA_EEI_EEI21_MASK 0x200000u

#define	DMA_EEI_EEI21_SHIFT 21

#define	DMA_EEI_EEI22_MASK 0x400000u

#define	DMA_EEI_EEI22_SHIFT 22

#define	DMA_EEI_EEI23_MASK 0x800000u

#define	DMA_EEI_EEI23_SHIFT 23

#define	DMA_EEI_EEI24_MASK 0x1000000u

#define	DMA_EEI_EEI24_SHIFT 24

#define	DMA_EEI_EEI25_MASK 0x2000000u

#define	DMA_EEI_EEI25_SHIFT 25

#define	DMA_EEI_EEI26_MASK 0x4000000u

#define	DMA_EEI_EEI26_SHIFT 26

#define	DMA_EEI_EEI27_MASK 0x8000000u

#define	DMA_EEI_EEI27_SHIFT 27

#define	DMA_EEI_EEI28_MASK 0x10000000u

#define	DMA_EEI_EEI28_SHIFT 28

#define	DMA_EEI_EEI29_MASK 0x20000000u

#define	DMA_EEI_EEI29_SHIFT 29

#define	DMA_EEI_EEI30_MASK 0x40000000u

#define	DMA_EEI_EEI30_SHIFT 30

#define	DMA_EEI_EEI31_MASK 0x80000000u

#define	DMA_EEI_EEI31_SHIFT 31

#define	DMA_CEEI_CEEI_MASK 0x1Fu

#define	DMA_CEEI_CEEI_SHIFT 0

#define	DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)

#define	DMA_CEEI_CAEE_MASK 0x40u

#define	DMA_CEEI_CAEE_SHIFT 6

#define	DMA_CEEI_NOP_MASK 0x80u

#define	DMA_CEEI_NOP_SHIFT 7

#define	DMA_SEEI_SEEI_MASK 0x1Fu

#define	DMA_SEEI_SEEI_SHIFT 0

#define	DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)

#define	DMA_SEEI_SAEE_MASK 0x40u

#define	DMA_SEEI_SAEE_SHIFT 6

#define	DMA_SEEI_NOP_MASK 0x80u

#define	DMA_SEEI_NOP_SHIFT 7

#define	DMA_CERQ_CERQ_MASK 0x1Fu

#define	DMA_CERQ_CERQ_SHIFT 0

#define	DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)

#define	DMA_CERQ_CAER_MASK 0x40u

#define	DMA_CERQ_CAER_SHIFT 6

#define	DMA_CERQ_NOP_MASK 0x80u

#define	DMA_CERQ_NOP_SHIFT 7

#define	DMA_SERQ_SERQ_MASK 0x1Fu

#define	DMA_SERQ_SERQ_SHIFT 0

#define	DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)

#define	DMA_SERQ_SAER_MASK 0x40u

#define	DMA_SERQ_SAER_SHIFT 6

#define	DMA_SERQ_NOP_MASK 0x80u

#define	DMA_SERQ_NOP_SHIFT 7

#define	DMA_CDNE_CDNE_MASK 0x1Fu

#define	DMA_CDNE_CDNE_SHIFT 0

#define	DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)

#define	DMA_CDNE_CADN_MASK 0x40u

#define	DMA_CDNE_CADN_SHIFT 6

#define	DMA_CDNE_NOP_MASK 0x80u

#define	DMA_CDNE_NOP_SHIFT 7

#define	DMA_SSRT_SSRT_MASK 0x1Fu

#define	DMA_SSRT_SSRT_SHIFT 0

#define	DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)

#define	DMA_SSRT_SAST_MASK 0x40u

#define	DMA_SSRT_SAST_SHIFT 6

#define	DMA_SSRT_NOP_MASK 0x80u

#define	DMA_SSRT_NOP_SHIFT 7

#define	DMA_CERR_CERR_MASK 0x1Fu

#define	DMA_CERR_CERR_SHIFT 0

#define	DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)

#define	DMA_CERR_CAEI_MASK 0x40u

#define	DMA_CERR_CAEI_SHIFT 6

#define	DMA_CERR_NOP_MASK 0x80u

#define	DMA_CERR_NOP_SHIFT 7

#define	DMA_CINT_CINT_MASK 0x1Fu

#define	DMA_CINT_CINT_SHIFT 0

#define	DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)

#define	DMA_CINT_CAIR_MASK 0x40u

#define	DMA_CINT_CAIR_SHIFT 6

#define	DMA_CINT_NOP_MASK 0x80u

#define	DMA_CINT_NOP_SHIFT 7

#define	DMA_INT_INT0_MASK 0x1u

#define	DMA_INT_INT0_SHIFT 0

#define	DMA_INT_INT1_MASK 0x2u

#define	DMA_INT_INT1_SHIFT 1

#define	DMA_INT_INT2_MASK 0x4u

#define	DMA_INT_INT2_SHIFT 2

#define	DMA_INT_INT3_MASK 0x8u

#define	DMA_INT_INT3_SHIFT 3

#define	DMA_INT_INT4_MASK 0x10u

#define	DMA_INT_INT4_SHIFT 4

#define	DMA_INT_INT5_MASK 0x20u

#define	DMA_INT_INT5_SHIFT 5

#define	DMA_INT_INT6_MASK 0x40u

#define	DMA_INT_INT6_SHIFT 6

#define	DMA_INT_INT7_MASK 0x80u

#define	DMA_INT_INT7_SHIFT 7

#define	DMA_INT_INT8_MASK 0x100u

#define	DMA_INT_INT8_SHIFT 8

#define	DMA_INT_INT9_MASK 0x200u

#define	DMA_INT_INT9_SHIFT 9

#define	DMA_INT_INT10_MASK 0x400u

#define	DMA_INT_INT10_SHIFT 10

#define	DMA_INT_INT11_MASK 0x800u

#define	DMA_INT_INT11_SHIFT 11

#define	DMA_INT_INT12_MASK 0x1000u

#define	DMA_INT_INT12_SHIFT 12

#define	DMA_INT_INT13_MASK 0x2000u

#define	DMA_INT_INT13_SHIFT 13

#define	DMA_INT_INT14_MASK 0x4000u

#define	DMA_INT_INT14_SHIFT 14

#define	DMA_INT_INT15_MASK 0x8000u

#define	DMA_INT_INT15_SHIFT 15

#define	DMA_INT_INT16_MASK 0x10000u

#define	DMA_INT_INT16_SHIFT 16

#define	DMA_INT_INT17_MASK 0x20000u

#define	DMA_INT_INT17_SHIFT 17

#define	DMA_INT_INT18_MASK 0x40000u

#define	DMA_INT_INT18_SHIFT 18

#define	DMA_INT_INT19_MASK 0x80000u

#define	DMA_INT_INT19_SHIFT 19

#define	DMA_INT_INT20_MASK 0x100000u

#define	DMA_INT_INT20_SHIFT 20

#define	DMA_INT_INT21_MASK 0x200000u

#define	DMA_INT_INT21_SHIFT 21

#define	DMA_INT_INT22_MASK 0x400000u

#define	DMA_INT_INT22_SHIFT 22

#define	DMA_INT_INT23_MASK 0x800000u

#define	DMA_INT_INT23_SHIFT 23

#define	DMA_INT_INT24_MASK 0x1000000u

#define	DMA_INT_INT24_SHIFT 24

#define	DMA_INT_INT25_MASK 0x2000000u

#define	DMA_INT_INT25_SHIFT 25

#define	DMA_INT_INT26_MASK 0x4000000u

#define	DMA_INT_INT26_SHIFT 26

#define	DMA_INT_INT27_MASK 0x8000000u

#define	DMA_INT_INT27_SHIFT 27

#define	DMA_INT_INT28_MASK 0x10000000u

#define	DMA_INT_INT28_SHIFT 28

#define	DMA_INT_INT29_MASK 0x20000000u

#define	DMA_INT_INT29_SHIFT 29

#define	DMA_INT_INT30_MASK 0x40000000u

#define	DMA_INT_INT30_SHIFT 30

#define	DMA_INT_INT31_MASK 0x80000000u

#define	DMA_INT_INT31_SHIFT 31

#define	DMA_ERR_ERR0_MASK 0x1u

#define	DMA_ERR_ERR0_SHIFT 0

#define	DMA_ERR_ERR1_MASK 0x2u

#define	DMA_ERR_ERR1_SHIFT 1

#define	DMA_ERR_ERR2_MASK 0x4u

#define	DMA_ERR_ERR2_SHIFT 2

#define	DMA_ERR_ERR3_MASK 0x8u

#define	DMA_ERR_ERR3_SHIFT 3

#define	DMA_ERR_ERR4_MASK 0x10u

#define	DMA_ERR_ERR4_SHIFT 4

#define	DMA_ERR_ERR5_MASK 0x20u

#define	DMA_ERR_ERR5_SHIFT 5

#define	DMA_ERR_ERR6_MASK 0x40u

#define	DMA_ERR_ERR6_SHIFT 6

#define	DMA_ERR_ERR7_MASK 0x80u

#define	DMA_ERR_ERR7_SHIFT 7

#define	DMA_ERR_ERR8_MASK 0x100u

#define	DMA_ERR_ERR8_SHIFT 8

#define	DMA_ERR_ERR9_MASK 0x200u

#define	DMA_ERR_ERR9_SHIFT 9

#define	DMA_ERR_ERR10_MASK 0x400u

#define	DMA_ERR_ERR10_SHIFT 10

#define	DMA_ERR_ERR11_MASK 0x800u

#define	DMA_ERR_ERR11_SHIFT 11

#define	DMA_ERR_ERR12_MASK 0x1000u

#define	DMA_ERR_ERR12_SHIFT 12

#define	DMA_ERR_ERR13_MASK 0x2000u

#define	DMA_ERR_ERR13_SHIFT 13

#define	DMA_ERR_ERR14_MASK 0x4000u

#define	DMA_ERR_ERR14_SHIFT 14

#define	DMA_ERR_ERR15_MASK 0x8000u

#define	DMA_ERR_ERR15_SHIFT 15

#define	DMA_ERR_ERR16_MASK 0x10000u

#define	DMA_ERR_ERR16_SHIFT 16

#define	DMA_ERR_ERR17_MASK 0x20000u

#define	DMA_ERR_ERR17_SHIFT 17

#define	DMA_ERR_ERR18_MASK 0x40000u

#define	DMA_ERR_ERR18_SHIFT 18

#define	DMA_ERR_ERR19_MASK 0x80000u

#define	DMA_ERR_ERR19_SHIFT 19

#define	DMA_ERR_ERR20_MASK 0x100000u

#define	DMA_ERR_ERR20_SHIFT 20

#define	DMA_ERR_ERR21_MASK 0x200000u

#define	DMA_ERR_ERR21_SHIFT 21

#define	DMA_ERR_ERR22_MASK 0x400000u

#define	DMA_ERR_ERR22_SHIFT 22

#define	DMA_ERR_ERR23_MASK 0x800000u

#define	DMA_ERR_ERR23_SHIFT 23

#define	DMA_ERR_ERR24_MASK 0x1000000u

#define	DMA_ERR_ERR24_SHIFT 24

#define	DMA_ERR_ERR25_MASK 0x2000000u

#define	DMA_ERR_ERR25_SHIFT 25

#define	DMA_ERR_ERR26_MASK 0x4000000u

#define	DMA_ERR_ERR26_SHIFT 26

#define	DMA_ERR_ERR27_MASK 0x8000000u

#define	DMA_ERR_ERR27_SHIFT 27

#define	DMA_ERR_ERR28_MASK 0x10000000u

#define	DMA_ERR_ERR28_SHIFT 28

#define	DMA_ERR_ERR29_MASK 0x20000000u

#define	DMA_ERR_ERR29_SHIFT 29

#define	DMA_ERR_ERR30_MASK 0x40000000u

#define	DMA_ERR_ERR30_SHIFT 30

#define	DMA_ERR_ERR31_MASK 0x80000000u

#define	DMA_ERR_ERR31_SHIFT 31

#define	DMA_HRS_HRS0_MASK 0x1u

#define	DMA_HRS_HRS0_SHIFT 0

#define	DMA_HRS_HRS1_MASK 0x2u

#define	DMA_HRS_HRS1_SHIFT 1

#define	DMA_HRS_HRS2_MASK 0x4u

#define	DMA_HRS_HRS2_SHIFT 2

#define	DMA_HRS_HRS3_MASK 0x8u

#define	DMA_HRS_HRS3_SHIFT 3

#define	DMA_HRS_HRS4_MASK 0x10u

#define	DMA_HRS_HRS4_SHIFT 4

#define	DMA_HRS_HRS5_MASK 0x20u

#define	DMA_HRS_HRS5_SHIFT 5

#define	DMA_HRS_HRS6_MASK 0x40u

#define	DMA_HRS_HRS6_SHIFT 6

#define	DMA_HRS_HRS7_MASK 0x80u

#define	DMA_HRS_HRS7_SHIFT 7

#define	DMA_HRS_HRS8_MASK 0x100u

#define	DMA_HRS_HRS8_SHIFT 8

#define	DMA_HRS_HRS9_MASK 0x200u

#define	DMA_HRS_HRS9_SHIFT 9

#define	DMA_HRS_HRS10_MASK 0x400u

#define	DMA_HRS_HRS10_SHIFT 10

#define	DMA_HRS_HRS11_MASK 0x800u

#define	DMA_HRS_HRS11_SHIFT 11

#define	DMA_HRS_HRS12_MASK 0x1000u

#define	DMA_HRS_HRS12_SHIFT 12

#define	DMA_HRS_HRS13_MASK 0x2000u

#define	DMA_HRS_HRS13_SHIFT 13

#define	DMA_HRS_HRS14_MASK 0x4000u

#define	DMA_HRS_HRS14_SHIFT 14

#define	DMA_HRS_HRS15_MASK 0x8000u

#define	DMA_HRS_HRS15_SHIFT 15

#define	DMA_HRS_HRS16_MASK 0x10000u

#define	DMA_HRS_HRS16_SHIFT 16

#define	DMA_HRS_HRS17_MASK 0x20000u

#define	DMA_HRS_HRS17_SHIFT 17

#define	DMA_HRS_HRS18_MASK 0x40000u

#define	DMA_HRS_HRS18_SHIFT 18

#define	DMA_HRS_HRS19_MASK 0x80000u

#define	DMA_HRS_HRS19_SHIFT 19

#define	DMA_HRS_HRS20_MASK 0x100000u

#define	DMA_HRS_HRS20_SHIFT 20

#define	DMA_HRS_HRS21_MASK 0x200000u

#define	DMA_HRS_HRS21_SHIFT 21

#define	DMA_HRS_HRS22_MASK 0x400000u

#define	DMA_HRS_HRS22_SHIFT 22

#define	DMA_HRS_HRS23_MASK 0x800000u

#define	DMA_HRS_HRS23_SHIFT 23

#define	DMA_HRS_HRS24_MASK 0x1000000u

#define	DMA_HRS_HRS24_SHIFT 24

#define	DMA_HRS_HRS25_MASK 0x2000000u

#define	DMA_HRS_HRS25_SHIFT 25

#define	DMA_HRS_HRS26_MASK 0x4000000u

#define	DMA_HRS_HRS26_SHIFT 26

#define	DMA_HRS_HRS27_MASK 0x8000000u

#define	DMA_HRS_HRS27_SHIFT 27

#define	DMA_HRS_HRS28_MASK 0x10000000u

#define	DMA_HRS_HRS28_SHIFT 28

#define	DMA_HRS_HRS29_MASK 0x20000000u

#define	DMA_HRS_HRS29_SHIFT 29

#define	DMA_HRS_HRS30_MASK 0x40000000u

#define	DMA_HRS_HRS30_SHIFT 30

#define	DMA_HRS_HRS31_MASK 0x80000000u

#define	DMA_HRS_HRS31_SHIFT 31

#define	DMA_DCHPRI3_CHPRI_MASK 0xFu

#define	DMA_DCHPRI3_CHPRI_SHIFT 0

#define	DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)

#define	DMA_DCHPRI3_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI3_GRPPRI_SHIFT 4

#define	DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_GRPPRI_SHIFT))&DMA_DCHPRI3_GRPPRI_MASK)

#define	DMA_DCHPRI3_DPA_MASK 0x40u

#define	DMA_DCHPRI3_DPA_SHIFT 6

#define	DMA_DCHPRI3_ECP_MASK 0x80u

#define	DMA_DCHPRI3_ECP_SHIFT 7

#define	DMA_DCHPRI2_CHPRI_MASK 0xFu

#define	DMA_DCHPRI2_CHPRI_SHIFT 0

#define	DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)

#define	DMA_DCHPRI2_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI2_GRPPRI_SHIFT 4

#define	DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_GRPPRI_SHIFT))&DMA_DCHPRI2_GRPPRI_MASK)

#define	DMA_DCHPRI2_DPA_MASK 0x40u

#define	DMA_DCHPRI2_DPA_SHIFT 6

#define	DMA_DCHPRI2_ECP_MASK 0x80u

#define	DMA_DCHPRI2_ECP_SHIFT 7

#define	DMA_DCHPRI1_CHPRI_MASK 0xFu

#define	DMA_DCHPRI1_CHPRI_SHIFT 0

#define	DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)

#define	DMA_DCHPRI1_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI1_GRPPRI_SHIFT 4

#define	DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_GRPPRI_SHIFT))&DMA_DCHPRI1_GRPPRI_MASK)

#define	DMA_DCHPRI1_DPA_MASK 0x40u

#define	DMA_DCHPRI1_DPA_SHIFT 6

#define	DMA_DCHPRI1_ECP_MASK 0x80u

#define	DMA_DCHPRI1_ECP_SHIFT 7

#define	DMA_DCHPRI0_CHPRI_MASK 0xFu

#define	DMA_DCHPRI0_CHPRI_SHIFT 0

#define	DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)

#define	DMA_DCHPRI0_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI0_GRPPRI_SHIFT 4

#define	DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_GRPPRI_SHIFT))&DMA_DCHPRI0_GRPPRI_MASK)

#define	DMA_DCHPRI0_DPA_MASK 0x40u

#define	DMA_DCHPRI0_DPA_SHIFT 6

#define	DMA_DCHPRI0_ECP_MASK 0x80u

#define	DMA_DCHPRI0_ECP_SHIFT 7

#define	DMA_DCHPRI7_CHPRI_MASK 0xFu

#define	DMA_DCHPRI7_CHPRI_SHIFT 0

#define	DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)

#define	DMA_DCHPRI7_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI7_GRPPRI_SHIFT 4

#define	DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_GRPPRI_SHIFT))&DMA_DCHPRI7_GRPPRI_MASK)

#define	DMA_DCHPRI7_DPA_MASK 0x40u

#define	DMA_DCHPRI7_DPA_SHIFT 6

#define	DMA_DCHPRI7_ECP_MASK 0x80u

#define	DMA_DCHPRI7_ECP_SHIFT 7

#define	DMA_DCHPRI6_CHPRI_MASK 0xFu

#define	DMA_DCHPRI6_CHPRI_SHIFT 0

#define	DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)

#define	DMA_DCHPRI6_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI6_GRPPRI_SHIFT 4

#define	DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_GRPPRI_SHIFT))&DMA_DCHPRI6_GRPPRI_MASK)

#define	DMA_DCHPRI6_DPA_MASK 0x40u

#define	DMA_DCHPRI6_DPA_SHIFT 6

#define	DMA_DCHPRI6_ECP_MASK 0x80u

#define	DMA_DCHPRI6_ECP_SHIFT 7

#define	DMA_DCHPRI5_CHPRI_MASK 0xFu

#define	DMA_DCHPRI5_CHPRI_SHIFT 0

#define	DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)

#define	DMA_DCHPRI5_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI5_GRPPRI_SHIFT 4

#define	DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_GRPPRI_SHIFT))&DMA_DCHPRI5_GRPPRI_MASK)

#define	DMA_DCHPRI5_DPA_MASK 0x40u

#define	DMA_DCHPRI5_DPA_SHIFT 6

#define	DMA_DCHPRI5_ECP_MASK 0x80u

#define	DMA_DCHPRI5_ECP_SHIFT 7

#define	DMA_DCHPRI4_CHPRI_MASK 0xFu

#define	DMA_DCHPRI4_CHPRI_SHIFT 0

#define	DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)

#define	DMA_DCHPRI4_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI4_GRPPRI_SHIFT 4

#define	DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_GRPPRI_SHIFT))&DMA_DCHPRI4_GRPPRI_MASK)

#define	DMA_DCHPRI4_DPA_MASK 0x40u

#define	DMA_DCHPRI4_DPA_SHIFT 6

#define	DMA_DCHPRI4_ECP_MASK 0x80u

#define	DMA_DCHPRI4_ECP_SHIFT 7

#define	DMA_DCHPRI11_CHPRI_MASK 0xFu

#define	DMA_DCHPRI11_CHPRI_SHIFT 0

#define	DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)

#define	DMA_DCHPRI11_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI11_GRPPRI_SHIFT 4

#define	DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_GRPPRI_SHIFT))&DMA_DCHPRI11_GRPPRI_MASK)

#define	DMA_DCHPRI11_DPA_MASK 0x40u

#define	DMA_DCHPRI11_DPA_SHIFT 6

#define	DMA_DCHPRI11_ECP_MASK 0x80u

#define	DMA_DCHPRI11_ECP_SHIFT 7

#define	DMA_DCHPRI10_CHPRI_MASK 0xFu

#define	DMA_DCHPRI10_CHPRI_SHIFT 0

#define	DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)

#define	DMA_DCHPRI10_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI10_GRPPRI_SHIFT 4

#define	DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_GRPPRI_SHIFT))&DMA_DCHPRI10_GRPPRI_MASK)

#define	DMA_DCHPRI10_DPA_MASK 0x40u

#define	DMA_DCHPRI10_DPA_SHIFT 6

#define	DMA_DCHPRI10_ECP_MASK 0x80u

#define	DMA_DCHPRI10_ECP_SHIFT 7

#define	DMA_DCHPRI9_CHPRI_MASK 0xFu

#define	DMA_DCHPRI9_CHPRI_SHIFT 0

#define	DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)

#define	DMA_DCHPRI9_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI9_GRPPRI_SHIFT 4

#define	DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_GRPPRI_SHIFT))&DMA_DCHPRI9_GRPPRI_MASK)

#define	DMA_DCHPRI9_DPA_MASK 0x40u

#define	DMA_DCHPRI9_DPA_SHIFT 6

#define	DMA_DCHPRI9_ECP_MASK 0x80u

#define	DMA_DCHPRI9_ECP_SHIFT 7

#define	DMA_DCHPRI8_CHPRI_MASK 0xFu

#define	DMA_DCHPRI8_CHPRI_SHIFT 0

#define	DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)

#define	DMA_DCHPRI8_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI8_GRPPRI_SHIFT 4

#define	DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_GRPPRI_SHIFT))&DMA_DCHPRI8_GRPPRI_MASK)

#define	DMA_DCHPRI8_DPA_MASK 0x40u

#define	DMA_DCHPRI8_DPA_SHIFT 6

#define	DMA_DCHPRI8_ECP_MASK 0x80u

#define	DMA_DCHPRI8_ECP_SHIFT 7

#define	DMA_DCHPRI15_CHPRI_MASK 0xFu

#define	DMA_DCHPRI15_CHPRI_SHIFT 0

#define	DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)

#define	DMA_DCHPRI15_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI15_GRPPRI_SHIFT 4

#define	DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_GRPPRI_SHIFT))&DMA_DCHPRI15_GRPPRI_MASK)

#define	DMA_DCHPRI15_DPA_MASK 0x40u

#define	DMA_DCHPRI15_DPA_SHIFT 6

#define	DMA_DCHPRI15_ECP_MASK 0x80u

#define	DMA_DCHPRI15_ECP_SHIFT 7

#define	DMA_DCHPRI14_CHPRI_MASK 0xFu

#define	DMA_DCHPRI14_CHPRI_SHIFT 0

#define	DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)

#define	DMA_DCHPRI14_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI14_GRPPRI_SHIFT 4

#define	DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_GRPPRI_SHIFT))&DMA_DCHPRI14_GRPPRI_MASK)

#define	DMA_DCHPRI14_DPA_MASK 0x40u

#define	DMA_DCHPRI14_DPA_SHIFT 6

#define	DMA_DCHPRI14_ECP_MASK 0x80u

#define	DMA_DCHPRI14_ECP_SHIFT 7

#define	DMA_DCHPRI13_CHPRI_MASK 0xFu

#define	DMA_DCHPRI13_CHPRI_SHIFT 0

#define	DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)

#define	DMA_DCHPRI13_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI13_GRPPRI_SHIFT 4

#define	DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_GRPPRI_SHIFT))&DMA_DCHPRI13_GRPPRI_MASK)

#define	DMA_DCHPRI13_DPA_MASK 0x40u

#define	DMA_DCHPRI13_DPA_SHIFT 6

#define	DMA_DCHPRI13_ECP_MASK 0x80u

#define	DMA_DCHPRI13_ECP_SHIFT 7

#define	DMA_DCHPRI12_CHPRI_MASK 0xFu

#define	DMA_DCHPRI12_CHPRI_SHIFT 0

#define	DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)

#define	DMA_DCHPRI12_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI12_GRPPRI_SHIFT 4

#define	DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_GRPPRI_SHIFT))&DMA_DCHPRI12_GRPPRI_MASK)

#define	DMA_DCHPRI12_DPA_MASK 0x40u

#define	DMA_DCHPRI12_DPA_SHIFT 6

#define	DMA_DCHPRI12_ECP_MASK 0x80u

#define	DMA_DCHPRI12_ECP_SHIFT 7

#define	DMA_DCHPRI19_CHPRI_MASK 0xFu

#define	DMA_DCHPRI19_CHPRI_SHIFT 0

#define	DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI19_CHPRI_SHIFT))&DMA_DCHPRI19_CHPRI_MASK)

#define	DMA_DCHPRI19_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI19_GRPPRI_SHIFT 4

#define	DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI19_GRPPRI_SHIFT))&DMA_DCHPRI19_GRPPRI_MASK)

#define	DMA_DCHPRI19_DPA_MASK 0x40u

#define	DMA_DCHPRI19_DPA_SHIFT 6

#define	DMA_DCHPRI19_ECP_MASK 0x80u

#define	DMA_DCHPRI19_ECP_SHIFT 7

#define	DMA_DCHPRI18_CHPRI_MASK 0xFu

#define	DMA_DCHPRI18_CHPRI_SHIFT 0

#define	DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI18_CHPRI_SHIFT))&DMA_DCHPRI18_CHPRI_MASK)

#define	DMA_DCHPRI18_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI18_GRPPRI_SHIFT 4

#define	DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI18_GRPPRI_SHIFT))&DMA_DCHPRI18_GRPPRI_MASK)

#define	DMA_DCHPRI18_DPA_MASK 0x40u

#define	DMA_DCHPRI18_DPA_SHIFT 6

#define	DMA_DCHPRI18_ECP_MASK 0x80u

#define	DMA_DCHPRI18_ECP_SHIFT 7

#define	DMA_DCHPRI17_CHPRI_MASK 0xFu

#define	DMA_DCHPRI17_CHPRI_SHIFT 0

#define	DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI17_CHPRI_SHIFT))&DMA_DCHPRI17_CHPRI_MASK)

#define	DMA_DCHPRI17_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI17_GRPPRI_SHIFT 4

#define	DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI17_GRPPRI_SHIFT))&DMA_DCHPRI17_GRPPRI_MASK)

#define	DMA_DCHPRI17_DPA_MASK 0x40u

#define	DMA_DCHPRI17_DPA_SHIFT 6

#define	DMA_DCHPRI17_ECP_MASK 0x80u

#define	DMA_DCHPRI17_ECP_SHIFT 7

#define	DMA_DCHPRI16_CHPRI_MASK 0xFu

#define	DMA_DCHPRI16_CHPRI_SHIFT 0

#define	DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI16_CHPRI_SHIFT))&DMA_DCHPRI16_CHPRI_MASK)

#define	DMA_DCHPRI16_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI16_GRPPRI_SHIFT 4

#define	DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI16_GRPPRI_SHIFT))&DMA_DCHPRI16_GRPPRI_MASK)

#define	DMA_DCHPRI16_DPA_MASK 0x40u

#define	DMA_DCHPRI16_DPA_SHIFT 6

#define	DMA_DCHPRI16_ECP_MASK 0x80u

#define	DMA_DCHPRI16_ECP_SHIFT 7

#define	DMA_DCHPRI23_CHPRI_MASK 0xFu

#define	DMA_DCHPRI23_CHPRI_SHIFT 0

#define	DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI23_CHPRI_SHIFT))&DMA_DCHPRI23_CHPRI_MASK)

#define	DMA_DCHPRI23_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI23_GRPPRI_SHIFT 4

#define	DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI23_GRPPRI_SHIFT))&DMA_DCHPRI23_GRPPRI_MASK)

#define	DMA_DCHPRI23_DPA_MASK 0x40u

#define	DMA_DCHPRI23_DPA_SHIFT 6

#define	DMA_DCHPRI23_ECP_MASK 0x80u

#define	DMA_DCHPRI23_ECP_SHIFT 7

#define	DMA_DCHPRI22_CHPRI_MASK 0xFu

#define	DMA_DCHPRI22_CHPRI_SHIFT 0

#define	DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI22_CHPRI_SHIFT))&DMA_DCHPRI22_CHPRI_MASK)

#define	DMA_DCHPRI22_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI22_GRPPRI_SHIFT 4

#define	DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI22_GRPPRI_SHIFT))&DMA_DCHPRI22_GRPPRI_MASK)

#define	DMA_DCHPRI22_DPA_MASK 0x40u

#define	DMA_DCHPRI22_DPA_SHIFT 6

#define	DMA_DCHPRI22_ECP_MASK 0x80u

#define	DMA_DCHPRI22_ECP_SHIFT 7

#define	DMA_DCHPRI21_CHPRI_MASK 0xFu

#define	DMA_DCHPRI21_CHPRI_SHIFT 0

#define	DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI21_CHPRI_SHIFT))&DMA_DCHPRI21_CHPRI_MASK)

#define	DMA_DCHPRI21_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI21_GRPPRI_SHIFT 4

#define	DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI21_GRPPRI_SHIFT))&DMA_DCHPRI21_GRPPRI_MASK)

#define	DMA_DCHPRI21_DPA_MASK 0x40u

#define	DMA_DCHPRI21_DPA_SHIFT 6

#define	DMA_DCHPRI21_ECP_MASK 0x80u

#define	DMA_DCHPRI21_ECP_SHIFT 7

#define	DMA_DCHPRI20_CHPRI_MASK 0xFu

#define	DMA_DCHPRI20_CHPRI_SHIFT 0

#define	DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI20_CHPRI_SHIFT))&DMA_DCHPRI20_CHPRI_MASK)

#define	DMA_DCHPRI20_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI20_GRPPRI_SHIFT 4

#define	DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI20_GRPPRI_SHIFT))&DMA_DCHPRI20_GRPPRI_MASK)

#define	DMA_DCHPRI20_DPA_MASK 0x40u

#define	DMA_DCHPRI20_DPA_SHIFT 6

#define	DMA_DCHPRI20_ECP_MASK 0x80u

#define	DMA_DCHPRI20_ECP_SHIFT 7

#define	DMA_DCHPRI27_CHPRI_MASK 0xFu

#define	DMA_DCHPRI27_CHPRI_SHIFT 0

#define	DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI27_CHPRI_SHIFT))&DMA_DCHPRI27_CHPRI_MASK)

#define	DMA_DCHPRI27_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI27_GRPPRI_SHIFT 4

#define	DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI27_GRPPRI_SHIFT))&DMA_DCHPRI27_GRPPRI_MASK)

#define	DMA_DCHPRI27_DPA_MASK 0x40u

#define	DMA_DCHPRI27_DPA_SHIFT 6

#define	DMA_DCHPRI27_ECP_MASK 0x80u

#define	DMA_DCHPRI27_ECP_SHIFT 7

#define	DMA_DCHPRI26_CHPRI_MASK 0xFu

#define	DMA_DCHPRI26_CHPRI_SHIFT 0

#define	DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI26_CHPRI_SHIFT))&DMA_DCHPRI26_CHPRI_MASK)

#define	DMA_DCHPRI26_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI26_GRPPRI_SHIFT 4

#define	DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI26_GRPPRI_SHIFT))&DMA_DCHPRI26_GRPPRI_MASK)

#define	DMA_DCHPRI26_DPA_MASK 0x40u

#define	DMA_DCHPRI26_DPA_SHIFT 6

#define	DMA_DCHPRI26_ECP_MASK 0x80u

#define	DMA_DCHPRI26_ECP_SHIFT 7

#define	DMA_DCHPRI25_CHPRI_MASK 0xFu

#define	DMA_DCHPRI25_CHPRI_SHIFT 0

#define	DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI25_CHPRI_SHIFT))&DMA_DCHPRI25_CHPRI_MASK)

#define	DMA_DCHPRI25_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI25_GRPPRI_SHIFT 4

#define	DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI25_GRPPRI_SHIFT))&DMA_DCHPRI25_GRPPRI_MASK)

#define	DMA_DCHPRI25_DPA_MASK 0x40u

#define	DMA_DCHPRI25_DPA_SHIFT 6

#define	DMA_DCHPRI25_ECP_MASK 0x80u

#define	DMA_DCHPRI25_ECP_SHIFT 7

#define	DMA_DCHPRI24_CHPRI_MASK 0xFu

#define	DMA_DCHPRI24_CHPRI_SHIFT 0

#define	DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI24_CHPRI_SHIFT))&DMA_DCHPRI24_CHPRI_MASK)

#define	DMA_DCHPRI24_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI24_GRPPRI_SHIFT 4

#define	DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI24_GRPPRI_SHIFT))&DMA_DCHPRI24_GRPPRI_MASK)

#define	DMA_DCHPRI24_DPA_MASK 0x40u

#define	DMA_DCHPRI24_DPA_SHIFT 6

#define	DMA_DCHPRI24_ECP_MASK 0x80u

#define	DMA_DCHPRI24_ECP_SHIFT 7

#define	DMA_DCHPRI31_CHPRI_MASK 0xFu

#define	DMA_DCHPRI31_CHPRI_SHIFT 0

#define	DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI31_CHPRI_SHIFT))&DMA_DCHPRI31_CHPRI_MASK)

#define	DMA_DCHPRI31_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI31_GRPPRI_SHIFT 4

#define	DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI31_GRPPRI_SHIFT))&DMA_DCHPRI31_GRPPRI_MASK)

#define	DMA_DCHPRI31_DPA_MASK 0x40u

#define	DMA_DCHPRI31_DPA_SHIFT 6

#define	DMA_DCHPRI31_ECP_MASK 0x80u

#define	DMA_DCHPRI31_ECP_SHIFT 7

#define	DMA_DCHPRI30_CHPRI_MASK 0xFu

#define	DMA_DCHPRI30_CHPRI_SHIFT 0

#define	DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI30_CHPRI_SHIFT))&DMA_DCHPRI30_CHPRI_MASK)

#define	DMA_DCHPRI30_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI30_GRPPRI_SHIFT 4

#define	DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI30_GRPPRI_SHIFT))&DMA_DCHPRI30_GRPPRI_MASK)

#define	DMA_DCHPRI30_DPA_MASK 0x40u

#define	DMA_DCHPRI30_DPA_SHIFT 6

#define	DMA_DCHPRI30_ECP_MASK 0x80u

#define	DMA_DCHPRI30_ECP_SHIFT 7

#define	DMA_DCHPRI29_CHPRI_MASK 0xFu

#define	DMA_DCHPRI29_CHPRI_SHIFT 0

#define	DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI29_CHPRI_SHIFT))&DMA_DCHPRI29_CHPRI_MASK)

#define	DMA_DCHPRI29_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI29_GRPPRI_SHIFT 4

#define	DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI29_GRPPRI_SHIFT))&DMA_DCHPRI29_GRPPRI_MASK)

#define	DMA_DCHPRI29_DPA_MASK 0x40u

#define	DMA_DCHPRI29_DPA_SHIFT 6

#define	DMA_DCHPRI29_ECP_MASK 0x80u

#define	DMA_DCHPRI29_ECP_SHIFT 7

#define	DMA_DCHPRI28_CHPRI_MASK 0xFu

#define	DMA_DCHPRI28_CHPRI_SHIFT 0

#define	DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI28_CHPRI_SHIFT))&DMA_DCHPRI28_CHPRI_MASK)

#define	DMA_DCHPRI28_GRPPRI_MASK 0x30u

#define	DMA_DCHPRI28_GRPPRI_SHIFT 4

#define	DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI28_GRPPRI_SHIFT))&DMA_DCHPRI28_GRPPRI_MASK)

#define	DMA_DCHPRI28_DPA_MASK 0x40u

#define	DMA_DCHPRI28_DPA_SHIFT 6

#define	DMA_DCHPRI28_ECP_MASK 0x80u

#define	DMA_DCHPRI28_ECP_SHIFT 7

#define	DMA_SADDR_SADDR_MASK 0xFFFFFFFFu

#define	DMA_SADDR_SADDR_SHIFT 0

#define	DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)

#define	DMA_SOFF_SOFF_MASK 0xFFFFu

#define	DMA_SOFF_SOFF_SHIFT 0

#define	DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)

#define	DMA_ATTR_DSIZE_MASK 0x7u

#define	DMA_ATTR_DSIZE_SHIFT 0

#define	DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)

#define	DMA_ATTR_DMOD_MASK 0xF8u

#define	DMA_ATTR_DMOD_SHIFT 3

#define	DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)

#define	DMA_ATTR_SSIZE_MASK 0x700u

#define	DMA_ATTR_SSIZE_SHIFT 8

#define	DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)

#define	DMA_ATTR_SMOD_MASK 0xF800u

#define	DMA_ATTR_SMOD_SHIFT 11

#define	DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)

#define	DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu

#define	DMA_NBYTES_MLNO_NBYTES_SHIFT 0

#define	DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)

#define	DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu

#define	DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0

#define	DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)

#define	DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u

#define	DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30

#define	DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u

#define	DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31

#define	DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu

#define	DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0

#define	DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)

#define	DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u

#define	DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10

#define	DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)

#define	DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u

#define	DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30

#define	DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u

#define	DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31

#define	DMA_SLAST_SLAST_MASK 0xFFFFFFFFu

#define	DMA_SLAST_SLAST_SHIFT 0

#define	DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)

#define	DMA_DADDR_DADDR_MASK 0xFFFFFFFFu

#define	DMA_DADDR_DADDR_SHIFT 0

#define	DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)

#define	DMA_DOFF_DOFF_MASK 0xFFFFu

#define	DMA_DOFF_DOFF_SHIFT 0

#define	DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)

#define	DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu

#define	DMA_CITER_ELINKNO_CITER_SHIFT 0

#define	DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)

#define	DMA_CITER_ELINKNO_ELINK_MASK 0x8000u

#define	DMA_CITER_ELINKNO_ELINK_SHIFT 15

#define	DMA_CITER_ELINKYES_CITER_MASK 0x1FFu

#define	DMA_CITER_ELINKYES_CITER_SHIFT 0

#define	DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)

#define	DMA_CITER_ELINKYES_LINKCH_MASK 0x3E00u

#define	DMA_CITER_ELINKYES_LINKCH_SHIFT 9

#define	DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)

#define	DMA_CITER_ELINKYES_ELINK_MASK 0x8000u

#define	DMA_CITER_ELINKYES_ELINK_SHIFT 15

#define	DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu

#define	DMA_DLAST_SGA_DLASTSGA_SHIFT 0

#define	DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)

#define	DMA_CSR_START_MASK 0x1u

#define	DMA_CSR_START_SHIFT 0

#define	DMA_CSR_INTMAJOR_MASK 0x2u

#define	DMA_CSR_INTMAJOR_SHIFT 1

#define	DMA_CSR_INTHALF_MASK 0x4u

#define	DMA_CSR_INTHALF_SHIFT 2

#define	DMA_CSR_DREQ_MASK 0x8u

#define	DMA_CSR_DREQ_SHIFT 3

#define	DMA_CSR_ESG_MASK 0x10u

#define	DMA_CSR_ESG_SHIFT 4

#define	DMA_CSR_MAJORELINK_MASK 0x20u

#define	DMA_CSR_MAJORELINK_SHIFT 5

#define	DMA_CSR_ACTIVE_MASK 0x40u

#define	DMA_CSR_ACTIVE_SHIFT 6

#define	DMA_CSR_DONE_MASK 0x80u

#define	DMA_CSR_DONE_SHIFT 7

#define	DMA_CSR_MAJORLINKCH_MASK 0x1F00u

#define	DMA_CSR_MAJORLINKCH_SHIFT 8

#define	DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)

#define	DMA_CSR_BWC_MASK 0xC000u

#define	DMA_CSR_BWC_SHIFT 14

#define	DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)

#define	DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu

#define	DMA_BITER_ELINKNO_BITER_SHIFT 0

#define	DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)

#define	DMA_BITER_ELINKNO_ELINK_MASK 0x8000u

#define	DMA_BITER_ELINKNO_ELINK_SHIFT 15

#define	DMA_BITER_ELINKYES_BITER_MASK 0x1FFu

#define	DMA_BITER_ELINKYES_BITER_SHIFT 0

#define	DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)

#define	DMA_BITER_ELINKYES_LINKCH_MASK 0x3E00u

#define	DMA_BITER_ELINKYES_LINKCH_SHIFT 9

#define	DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)

#define	DMA_BITER_ELINKYES_ELINK_MASK 0x8000u

#define	DMA_BITER_ELINKYES_ELINK_SHIFT 15

#define	DMA_BASE_PTR ((DMA_MemMapPtr)0x40008000u)

#define	DMA_BASE_PTRS { DMA_BASE_PTR }

#define	DMA_CR DMA_CR_REG(DMA_BASE_PTR)

#define	DMA_ES DMA_ES_REG(DMA_BASE_PTR)

#define	DMA_ERQ DMA_ERQ_REG(DMA_BASE_PTR)

#define	DMA_EEI DMA_EEI_REG(DMA_BASE_PTR)

#define	DMA_CEEI DMA_CEEI_REG(DMA_BASE_PTR)

#define	DMA_SEEI DMA_SEEI_REG(DMA_BASE_PTR)

#define	DMA_CERQ DMA_CERQ_REG(DMA_BASE_PTR)

#define	DMA_SERQ DMA_SERQ_REG(DMA_BASE_PTR)

#define	DMA_CDNE DMA_CDNE_REG(DMA_BASE_PTR)

#define	DMA_SSRT DMA_SSRT_REG(DMA_BASE_PTR)

#define	DMA_CERR DMA_CERR_REG(DMA_BASE_PTR)

#define	DMA_CINT DMA_CINT_REG(DMA_BASE_PTR)

#define	DMA_INT DMA_INT_REG(DMA_BASE_PTR)

#define	DMA_ERR DMA_ERR_REG(DMA_BASE_PTR)

#define	DMA_HRS DMA_HRS_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI19 DMA_DCHPRI19_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI18 DMA_DCHPRI18_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI17 DMA_DCHPRI17_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI16 DMA_DCHPRI16_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI23 DMA_DCHPRI23_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI22 DMA_DCHPRI22_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI21 DMA_DCHPRI21_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI20 DMA_DCHPRI20_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI27 DMA_DCHPRI27_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI26 DMA_DCHPRI26_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI25 DMA_DCHPRI25_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI24 DMA_DCHPRI24_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI31 DMA_DCHPRI31_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI30 DMA_DCHPRI30_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI29 DMA_DCHPRI29_REG(DMA_BASE_PTR)

#define	DMA_DCHPRI28 DMA_DCHPRI28_REG(DMA_BASE_PTR)

#define	DMA_TCD0_SADDR DMA_SADDR_REG(DMA_BASE_PTR,0)

#define	DMA_TCD0_SOFF DMA_SOFF_REG(DMA_BASE_PTR,0)

#define	DMA_TCD0_ATTR DMA_ATTR_REG(DMA_BASE_PTR,0)

#define	DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,0)

#define	DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,0)

#define	DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,0)

#define	DMA_TCD0_SLAST DMA_SLAST_REG(DMA_BASE_PTR,0)

#define	DMA_TCD0_DADDR DMA_DADDR_REG(DMA_BASE_PTR,0)

#define	DMA_TCD0_DOFF DMA_DOFF_REG(DMA_BASE_PTR,0)

#define	DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,0)

#define	DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,0)

#define	DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,0)

#define	DMA_TCD0_CSR DMA_CSR_REG(DMA_BASE_PTR,0)

#define	DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,0)

#define	DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,0)

#define	DMA_TCD1_SADDR DMA_SADDR_REG(DMA_BASE_PTR,1)

#define	DMA_TCD1_SOFF DMA_SOFF_REG(DMA_BASE_PTR,1)

#define	DMA_TCD1_ATTR DMA_ATTR_REG(DMA_BASE_PTR,1)

#define	DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,1)

#define	DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,1)

#define	DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,1)

#define	DMA_TCD1_SLAST DMA_SLAST_REG(DMA_BASE_PTR,1)

#define	DMA_TCD1_DADDR DMA_DADDR_REG(DMA_BASE_PTR,1)

#define	DMA_TCD1_DOFF DMA_DOFF_REG(DMA_BASE_PTR,1)

#define	DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,1)

#define	DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,1)

#define	DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,1)

#define	DMA_TCD1_CSR DMA_CSR_REG(DMA_BASE_PTR,1)

#define	DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,1)

#define	DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,1)

#define	DMA_TCD2_SADDR DMA_SADDR_REG(DMA_BASE_PTR,2)

#define	DMA_TCD2_SOFF DMA_SOFF_REG(DMA_BASE_PTR,2)

#define	DMA_TCD2_ATTR DMA_ATTR_REG(DMA_BASE_PTR,2)

#define	DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,2)

#define	DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,2)

#define	DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,2)

#define	DMA_TCD2_SLAST DMA_SLAST_REG(DMA_BASE_PTR,2)

#define	DMA_TCD2_DADDR DMA_DADDR_REG(DMA_BASE_PTR,2)

#define	DMA_TCD2_DOFF DMA_DOFF_REG(DMA_BASE_PTR,2)

#define	DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,2)

#define	DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,2)

#define	DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,2)

#define	DMA_TCD2_CSR DMA_CSR_REG(DMA_BASE_PTR,2)

#define	DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,2)

#define	DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,2)

#define	DMA_TCD3_SADDR DMA_SADDR_REG(DMA_BASE_PTR,3)

#define	DMA_TCD3_SOFF DMA_SOFF_REG(DMA_BASE_PTR,3)

#define	DMA_TCD3_ATTR DMA_ATTR_REG(DMA_BASE_PTR,3)

#define	DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,3)

#define	DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,3)

#define	DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,3)

#define	DMA_TCD3_SLAST DMA_SLAST_REG(DMA_BASE_PTR,3)

#define	DMA_TCD3_DADDR DMA_DADDR_REG(DMA_BASE_PTR,3)

#define	DMA_TCD3_DOFF DMA_DOFF_REG(DMA_BASE_PTR,3)

#define	DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,3)

#define	DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,3)

#define	DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,3)

#define	DMA_TCD3_CSR DMA_CSR_REG(DMA_BASE_PTR,3)

#define	DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,3)

#define	DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,3)

#define	DMA_TCD4_SADDR DMA_SADDR_REG(DMA_BASE_PTR,4)

#define	DMA_TCD4_SOFF DMA_SOFF_REG(DMA_BASE_PTR,4)

#define	DMA_TCD4_ATTR DMA_ATTR_REG(DMA_BASE_PTR,4)

#define	DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,4)

#define	DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,4)

#define	DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,4)

#define	DMA_TCD4_SLAST DMA_SLAST_REG(DMA_BASE_PTR,4)

#define	DMA_TCD4_DADDR DMA_DADDR_REG(DMA_BASE_PTR,4)

#define	DMA_TCD4_DOFF DMA_DOFF_REG(DMA_BASE_PTR,4)

#define	DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,4)

#define	DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,4)

#define	DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,4)

#define	DMA_TCD4_CSR DMA_CSR_REG(DMA_BASE_PTR,4)

#define	DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,4)

#define	DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,4)

#define	DMA_TCD5_SADDR DMA_SADDR_REG(DMA_BASE_PTR,5)

#define	DMA_TCD5_SOFF DMA_SOFF_REG(DMA_BASE_PTR,5)

#define	DMA_TCD5_ATTR DMA_ATTR_REG(DMA_BASE_PTR,5)

#define	DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,5)

#define	DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,5)

#define	DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,5)

#define	DMA_TCD5_SLAST DMA_SLAST_REG(DMA_BASE_PTR,5)

#define	DMA_TCD5_DADDR DMA_DADDR_REG(DMA_BASE_PTR,5)

#define	DMA_TCD5_DOFF DMA_DOFF_REG(DMA_BASE_PTR,5)

#define	DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,5)

#define	DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,5)

#define	DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,5)

#define	DMA_TCD5_CSR DMA_CSR_REG(DMA_BASE_PTR,5)

#define	DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,5)

#define	DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,5)

#define	DMA_TCD6_SADDR DMA_SADDR_REG(DMA_BASE_PTR,6)

#define	DMA_TCD6_SOFF DMA_SOFF_REG(DMA_BASE_PTR,6)

#define	DMA_TCD6_ATTR DMA_ATTR_REG(DMA_BASE_PTR,6)

#define	DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,6)

#define	DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,6)

#define	DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,6)

#define	DMA_TCD6_SLAST DMA_SLAST_REG(DMA_BASE_PTR,6)

#define	DMA_TCD6_DADDR DMA_DADDR_REG(DMA_BASE_PTR,6)

#define	DMA_TCD6_DOFF DMA_DOFF_REG(DMA_BASE_PTR,6)

#define	DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,6)

#define	DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,6)

#define	DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,6)

#define	DMA_TCD6_CSR DMA_CSR_REG(DMA_BASE_PTR,6)

#define	DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,6)

#define	DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,6)

#define	DMA_TCD7_SADDR DMA_SADDR_REG(DMA_BASE_PTR,7)

#define	DMA_TCD7_SOFF DMA_SOFF_REG(DMA_BASE_PTR,7)

#define	DMA_TCD7_ATTR DMA_ATTR_REG(DMA_BASE_PTR,7)

#define	DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,7)

#define	DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,7)

#define	DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,7)

#define	DMA_TCD7_SLAST DMA_SLAST_REG(DMA_BASE_PTR,7)

#define	DMA_TCD7_DADDR DMA_DADDR_REG(DMA_BASE_PTR,7)

#define	DMA_TCD7_DOFF DMA_DOFF_REG(DMA_BASE_PTR,7)

#define	DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,7)

#define	DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,7)

#define	DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,7)

#define	DMA_TCD7_CSR DMA_CSR_REG(DMA_BASE_PTR,7)

#define	DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,7)

#define	DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,7)

#define	DMA_TCD8_SADDR DMA_SADDR_REG(DMA_BASE_PTR,8)

#define	DMA_TCD8_SOFF DMA_SOFF_REG(DMA_BASE_PTR,8)

#define	DMA_TCD8_ATTR DMA_ATTR_REG(DMA_BASE_PTR,8)

#define	DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,8)

#define	DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,8)

#define	DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,8)

#define	DMA_TCD8_SLAST DMA_SLAST_REG(DMA_BASE_PTR,8)

#define	DMA_TCD8_DADDR DMA_DADDR_REG(DMA_BASE_PTR,8)

#define	DMA_TCD8_DOFF DMA_DOFF_REG(DMA_BASE_PTR,8)

#define	DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,8)

#define	DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,8)

#define	DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,8)

#define	DMA_TCD8_CSR DMA_CSR_REG(DMA_BASE_PTR,8)

#define	DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,8)

#define	DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,8)

#define	DMA_TCD9_SADDR DMA_SADDR_REG(DMA_BASE_PTR,9)

#define	DMA_TCD9_SOFF DMA_SOFF_REG(DMA_BASE_PTR,9)

#define	DMA_TCD9_ATTR DMA_ATTR_REG(DMA_BASE_PTR,9)

#define	DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,9)

#define	DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,9)

#define	DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,9)

#define	DMA_TCD9_SLAST DMA_SLAST_REG(DMA_BASE_PTR,9)

#define	DMA_TCD9_DADDR DMA_DADDR_REG(DMA_BASE_PTR,9)

#define	DMA_TCD9_DOFF DMA_DOFF_REG(DMA_BASE_PTR,9)

#define	DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,9)

#define	DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,9)

#define	DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,9)

#define	DMA_TCD9_CSR DMA_CSR_REG(DMA_BASE_PTR,9)

#define	DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,9)

#define	DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,9)

#define	DMA_TCD10_SADDR DMA_SADDR_REG(DMA_BASE_PTR,10)

#define	DMA_TCD10_SOFF DMA_SOFF_REG(DMA_BASE_PTR,10)

#define	DMA_TCD10_ATTR DMA_ATTR_REG(DMA_BASE_PTR,10)

#define	DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,10)

#define	DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,10)

#define	DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,10)

#define	DMA_TCD10_SLAST DMA_SLAST_REG(DMA_BASE_PTR,10)

#define	DMA_TCD10_DADDR DMA_DADDR_REG(DMA_BASE_PTR,10)

#define	DMA_TCD10_DOFF DMA_DOFF_REG(DMA_BASE_PTR,10)

#define	DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,10)

#define	DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,10)

#define	DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,10)

#define	DMA_TCD10_CSR DMA_CSR_REG(DMA_BASE_PTR,10)

#define	DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,10)

#define	DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,10)

#define	DMA_TCD11_SADDR DMA_SADDR_REG(DMA_BASE_PTR,11)

#define	DMA_TCD11_SOFF DMA_SOFF_REG(DMA_BASE_PTR,11)

#define	DMA_TCD11_ATTR DMA_ATTR_REG(DMA_BASE_PTR,11)

#define	DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,11)

#define	DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,11)

#define	DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,11)

#define	DMA_TCD11_SLAST DMA_SLAST_REG(DMA_BASE_PTR,11)

#define	DMA_TCD11_DADDR DMA_DADDR_REG(DMA_BASE_PTR,11)

#define	DMA_TCD11_DOFF DMA_DOFF_REG(DMA_BASE_PTR,11)

#define	DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,11)

#define	DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,11)

#define	DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,11)

#define	DMA_TCD11_CSR DMA_CSR_REG(DMA_BASE_PTR,11)

#define	DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,11)

#define	DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,11)

#define	DMA_TCD12_SADDR DMA_SADDR_REG(DMA_BASE_PTR,12)

#define	DMA_TCD12_SOFF DMA_SOFF_REG(DMA_BASE_PTR,12)

#define	DMA_TCD12_ATTR DMA_ATTR_REG(DMA_BASE_PTR,12)

#define	DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,12)

#define	DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,12)

#define	DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,12)

#define	DMA_TCD12_SLAST DMA_SLAST_REG(DMA_BASE_PTR,12)

#define	DMA_TCD12_DADDR DMA_DADDR_REG(DMA_BASE_PTR,12)

#define	DMA_TCD12_DOFF DMA_DOFF_REG(DMA_BASE_PTR,12)

#define	DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,12)

#define	DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,12)

#define	DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,12)

#define	DMA_TCD12_CSR DMA_CSR_REG(DMA_BASE_PTR,12)

#define	DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,12)

#define	DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,12)

#define	DMA_TCD13_SADDR DMA_SADDR_REG(DMA_BASE_PTR,13)

#define	DMA_TCD13_SOFF DMA_SOFF_REG(DMA_BASE_PTR,13)

#define	DMA_TCD13_ATTR DMA_ATTR_REG(DMA_BASE_PTR,13)

#define	DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,13)

#define	DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,13)

#define	DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,13)

#define	DMA_TCD13_SLAST DMA_SLAST_REG(DMA_BASE_PTR,13)

#define	DMA_TCD13_DADDR DMA_DADDR_REG(DMA_BASE_PTR,13)

#define	DMA_TCD13_DOFF DMA_DOFF_REG(DMA_BASE_PTR,13)

#define	DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,13)

#define	DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,13)

#define	DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,13)

#define	DMA_TCD13_CSR DMA_CSR_REG(DMA_BASE_PTR,13)

#define	DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,13)

#define	DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,13)

#define	DMA_TCD14_SADDR DMA_SADDR_REG(DMA_BASE_PTR,14)

#define	DMA_TCD14_SOFF DMA_SOFF_REG(DMA_BASE_PTR,14)

#define	DMA_TCD14_ATTR DMA_ATTR_REG(DMA_BASE_PTR,14)

#define	DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,14)

#define	DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,14)

#define	DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,14)

#define	DMA_TCD14_SLAST DMA_SLAST_REG(DMA_BASE_PTR,14)

#define	DMA_TCD14_DADDR DMA_DADDR_REG(DMA_BASE_PTR,14)

#define	DMA_TCD14_DOFF DMA_DOFF_REG(DMA_BASE_PTR,14)

#define	DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,14)

#define	DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,14)

#define	DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,14)

#define	DMA_TCD14_CSR DMA_CSR_REG(DMA_BASE_PTR,14)

#define	DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,14)

#define	DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,14)

#define	DMA_TCD15_SADDR DMA_SADDR_REG(DMA_BASE_PTR,15)

#define	DMA_TCD15_SOFF DMA_SOFF_REG(DMA_BASE_PTR,15)

#define	DMA_TCD15_ATTR DMA_ATTR_REG(DMA_BASE_PTR,15)

#define	DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,15)

#define	DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,15)

#define	DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,15)

#define	DMA_TCD15_SLAST DMA_SLAST_REG(DMA_BASE_PTR,15)

#define	DMA_TCD15_DADDR DMA_DADDR_REG(DMA_BASE_PTR,15)

#define	DMA_TCD15_DOFF DMA_DOFF_REG(DMA_BASE_PTR,15)

#define	DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,15)

#define	DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,15)

#define	DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,15)

#define	DMA_TCD15_CSR DMA_CSR_REG(DMA_BASE_PTR,15)

#define	DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,15)

#define	DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,15)

#define	DMA_TCD16_SADDR DMA_SADDR_REG(DMA_BASE_PTR,16)

#define	DMA_TCD16_SOFF DMA_SOFF_REG(DMA_BASE_PTR,16)

#define	DMA_TCD16_ATTR DMA_ATTR_REG(DMA_BASE_PTR,16)

#define	DMA_TCD16_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,16)

#define	DMA_TCD16_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,16)

#define	DMA_TCD16_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,16)

#define	DMA_TCD16_SLAST DMA_SLAST_REG(DMA_BASE_PTR,16)

#define	DMA_TCD16_DADDR DMA_DADDR_REG(DMA_BASE_PTR,16)

#define	DMA_TCD16_DOFF DMA_DOFF_REG(DMA_BASE_PTR,16)

#define	DMA_TCD16_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,16)

#define	DMA_TCD16_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,16)

#define	DMA_TCD16_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,16)

#define	DMA_TCD16_CSR DMA_CSR_REG(DMA_BASE_PTR,16)

#define	DMA_TCD16_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,16)

#define	DMA_TCD16_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,16)

#define	DMA_TCD17_SADDR DMA_SADDR_REG(DMA_BASE_PTR,17)

#define	DMA_TCD17_SOFF DMA_SOFF_REG(DMA_BASE_PTR,17)

#define	DMA_TCD17_ATTR DMA_ATTR_REG(DMA_BASE_PTR,17)

#define	DMA_TCD17_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,17)

#define	DMA_TCD17_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,17)

#define	DMA_TCD17_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,17)

#define	DMA_TCD17_SLAST DMA_SLAST_REG(DMA_BASE_PTR,17)

#define	DMA_TCD17_DADDR DMA_DADDR_REG(DMA_BASE_PTR,17)

#define	DMA_TCD17_DOFF DMA_DOFF_REG(DMA_BASE_PTR,17)

#define	DMA_TCD17_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,17)

#define	DMA_TCD17_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,17)

#define	DMA_TCD17_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,17)

#define	DMA_TCD17_CSR DMA_CSR_REG(DMA_BASE_PTR,17)

#define	DMA_TCD17_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,17)

#define	DMA_TCD17_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,17)

#define	DMA_TCD18_SADDR DMA_SADDR_REG(DMA_BASE_PTR,18)

#define	DMA_TCD18_SOFF DMA_SOFF_REG(DMA_BASE_PTR,18)

#define	DMA_TCD18_ATTR DMA_ATTR_REG(DMA_BASE_PTR,18)

#define	DMA_TCD18_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,18)

#define	DMA_TCD18_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,18)

#define	DMA_TCD18_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,18)

#define	DMA_TCD18_SLAST DMA_SLAST_REG(DMA_BASE_PTR,18)

#define	DMA_TCD18_DADDR DMA_DADDR_REG(DMA_BASE_PTR,18)

#define	DMA_TCD18_DOFF DMA_DOFF_REG(DMA_BASE_PTR,18)

#define	DMA_TCD18_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,18)

#define	DMA_TCD18_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,18)

#define	DMA_TCD18_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,18)

#define	DMA_TCD18_CSR DMA_CSR_REG(DMA_BASE_PTR,18)

#define	DMA_TCD18_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,18)

#define	DMA_TCD18_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,18)

#define	DMA_TCD19_SADDR DMA_SADDR_REG(DMA_BASE_PTR,19)

#define	DMA_TCD19_SOFF DMA_SOFF_REG(DMA_BASE_PTR,19)

#define	DMA_TCD19_ATTR DMA_ATTR_REG(DMA_BASE_PTR,19)

#define	DMA_TCD19_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,19)

#define	DMA_TCD19_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,19)

#define	DMA_TCD19_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,19)

#define	DMA_TCD19_SLAST DMA_SLAST_REG(DMA_BASE_PTR,19)

#define	DMA_TCD19_DADDR DMA_DADDR_REG(DMA_BASE_PTR,19)

#define	DMA_TCD19_DOFF DMA_DOFF_REG(DMA_BASE_PTR,19)

#define	DMA_TCD19_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,19)

#define	DMA_TCD19_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,19)

#define	DMA_TCD19_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,19)

#define	DMA_TCD19_CSR DMA_CSR_REG(DMA_BASE_PTR,19)

#define	DMA_TCD19_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,19)

#define	DMA_TCD19_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,19)

#define	DMA_TCD20_SADDR DMA_SADDR_REG(DMA_BASE_PTR,20)

#define	DMA_TCD20_SOFF DMA_SOFF_REG(DMA_BASE_PTR,20)

#define	DMA_TCD20_ATTR DMA_ATTR_REG(DMA_BASE_PTR,20)

#define	DMA_TCD20_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,20)

#define	DMA_TCD20_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,20)

#define	DMA_TCD20_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,20)

#define	DMA_TCD20_SLAST DMA_SLAST_REG(DMA_BASE_PTR,20)

#define	DMA_TCD20_DADDR DMA_DADDR_REG(DMA_BASE_PTR,20)

#define	DMA_TCD20_DOFF DMA_DOFF_REG(DMA_BASE_PTR,20)

#define	DMA_TCD20_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,20)

#define	DMA_TCD20_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,20)

#define	DMA_TCD20_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,20)

#define	DMA_TCD20_CSR DMA_CSR_REG(DMA_BASE_PTR,20)

#define	DMA_TCD20_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,20)

#define	DMA_TCD20_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,20)

#define	DMA_TCD21_SADDR DMA_SADDR_REG(DMA_BASE_PTR,21)

#define	DMA_TCD21_SOFF DMA_SOFF_REG(DMA_BASE_PTR,21)

#define	DMA_TCD21_ATTR DMA_ATTR_REG(DMA_BASE_PTR,21)

#define	DMA_TCD21_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,21)

#define	DMA_TCD21_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,21)

#define	DMA_TCD21_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,21)

#define	DMA_TCD21_SLAST DMA_SLAST_REG(DMA_BASE_PTR,21)

#define	DMA_TCD21_DADDR DMA_DADDR_REG(DMA_BASE_PTR,21)

#define	DMA_TCD21_DOFF DMA_DOFF_REG(DMA_BASE_PTR,21)

#define	DMA_TCD21_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,21)

#define	DMA_TCD21_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,21)

#define	DMA_TCD21_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,21)

#define	DMA_TCD21_CSR DMA_CSR_REG(DMA_BASE_PTR,21)

#define	DMA_TCD21_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,21)

#define	DMA_TCD21_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,21)

#define	DMA_TCD22_SADDR DMA_SADDR_REG(DMA_BASE_PTR,22)

#define	DMA_TCD22_SOFF DMA_SOFF_REG(DMA_BASE_PTR,22)

#define	DMA_TCD22_ATTR DMA_ATTR_REG(DMA_BASE_PTR,22)

#define	DMA_TCD22_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,22)

#define	DMA_TCD22_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,22)

#define	DMA_TCD22_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,22)

#define	DMA_TCD22_SLAST DMA_SLAST_REG(DMA_BASE_PTR,22)

#define	DMA_TCD22_DADDR DMA_DADDR_REG(DMA_BASE_PTR,22)

#define	DMA_TCD22_DOFF DMA_DOFF_REG(DMA_BASE_PTR,22)

#define	DMA_TCD22_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,22)

#define	DMA_TCD22_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,22)

#define	DMA_TCD22_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,22)

#define	DMA_TCD22_CSR DMA_CSR_REG(DMA_BASE_PTR,22)

#define	DMA_TCD22_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,22)

#define	DMA_TCD22_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,22)

#define	DMA_TCD23_SADDR DMA_SADDR_REG(DMA_BASE_PTR,23)

#define	DMA_TCD23_SOFF DMA_SOFF_REG(DMA_BASE_PTR,23)

#define	DMA_TCD23_ATTR DMA_ATTR_REG(DMA_BASE_PTR,23)

#define	DMA_TCD23_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,23)

#define	DMA_TCD23_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,23)

#define	DMA_TCD23_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,23)

#define	DMA_TCD23_SLAST DMA_SLAST_REG(DMA_BASE_PTR,23)

#define	DMA_TCD23_DADDR DMA_DADDR_REG(DMA_BASE_PTR,23)

#define	DMA_TCD23_DOFF DMA_DOFF_REG(DMA_BASE_PTR,23)

#define	DMA_TCD23_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,23)

#define	DMA_TCD23_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,23)

#define	DMA_TCD23_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,23)

#define	DMA_TCD23_CSR DMA_CSR_REG(DMA_BASE_PTR,23)

#define	DMA_TCD23_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,23)

#define	DMA_TCD23_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,23)

#define	DMA_TCD24_SADDR DMA_SADDR_REG(DMA_BASE_PTR,24)

#define	DMA_TCD24_SOFF DMA_SOFF_REG(DMA_BASE_PTR,24)

#define	DMA_TCD24_ATTR DMA_ATTR_REG(DMA_BASE_PTR,24)

#define	DMA_TCD24_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,24)

#define	DMA_TCD24_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,24)

#define	DMA_TCD24_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,24)

#define	DMA_TCD24_SLAST DMA_SLAST_REG(DMA_BASE_PTR,24)

#define	DMA_TCD24_DADDR DMA_DADDR_REG(DMA_BASE_PTR,24)

#define	DMA_TCD24_DOFF DMA_DOFF_REG(DMA_BASE_PTR,24)

#define	DMA_TCD24_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,24)

#define	DMA_TCD24_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,24)

#define	DMA_TCD24_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,24)

#define	DMA_TCD24_CSR DMA_CSR_REG(DMA_BASE_PTR,24)

#define	DMA_TCD24_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,24)

#define	DMA_TCD24_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,24)

#define	DMA_TCD25_SADDR DMA_SADDR_REG(DMA_BASE_PTR,25)

#define	DMA_TCD25_SOFF DMA_SOFF_REG(DMA_BASE_PTR,25)

#define	DMA_TCD25_ATTR DMA_ATTR_REG(DMA_BASE_PTR,25)

#define	DMA_TCD25_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,25)

#define	DMA_TCD25_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,25)

#define	DMA_TCD25_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,25)

#define	DMA_TCD25_SLAST DMA_SLAST_REG(DMA_BASE_PTR,25)

#define	DMA_TCD25_DADDR DMA_DADDR_REG(DMA_BASE_PTR,25)

#define	DMA_TCD25_DOFF DMA_DOFF_REG(DMA_BASE_PTR,25)

#define	DMA_TCD25_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,25)

#define	DMA_TCD25_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,25)

#define	DMA_TCD25_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,25)

#define	DMA_TCD25_CSR DMA_CSR_REG(DMA_BASE_PTR,25)

#define	DMA_TCD25_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,25)

#define	DMA_TCD25_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,25)

#define	DMA_TCD26_SADDR DMA_SADDR_REG(DMA_BASE_PTR,26)

#define	DMA_TCD26_SOFF DMA_SOFF_REG(DMA_BASE_PTR,26)

#define	DMA_TCD26_ATTR DMA_ATTR_REG(DMA_BASE_PTR,26)

#define	DMA_TCD26_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,26)

#define	DMA_TCD26_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,26)

#define	DMA_TCD26_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,26)

#define	DMA_TCD26_SLAST DMA_SLAST_REG(DMA_BASE_PTR,26)

#define	DMA_TCD26_DADDR DMA_DADDR_REG(DMA_BASE_PTR,26)

#define	DMA_TCD26_DOFF DMA_DOFF_REG(DMA_BASE_PTR,26)

#define	DMA_TCD26_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,26)

#define	DMA_TCD26_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,26)

#define	DMA_TCD26_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,26)

#define	DMA_TCD26_CSR DMA_CSR_REG(DMA_BASE_PTR,26)

#define	DMA_TCD26_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,26)

#define	DMA_TCD26_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,26)

#define	DMA_TCD27_SADDR DMA_SADDR_REG(DMA_BASE_PTR,27)

#define	DMA_TCD27_SOFF DMA_SOFF_REG(DMA_BASE_PTR,27)

#define	DMA_TCD27_ATTR DMA_ATTR_REG(DMA_BASE_PTR,27)

#define	DMA_TCD27_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,27)

#define	DMA_TCD27_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,27)

#define	DMA_TCD27_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,27)

#define	DMA_TCD27_SLAST DMA_SLAST_REG(DMA_BASE_PTR,27)

#define	DMA_TCD27_DADDR DMA_DADDR_REG(DMA_BASE_PTR,27)

#define	DMA_TCD27_DOFF DMA_DOFF_REG(DMA_BASE_PTR,27)

#define	DMA_TCD27_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,27)

#define	DMA_TCD27_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,27)

#define	DMA_TCD27_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,27)

#define	DMA_TCD27_CSR DMA_CSR_REG(DMA_BASE_PTR,27)

#define	DMA_TCD27_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,27)

#define	DMA_TCD27_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,27)

#define	DMA_TCD28_SADDR DMA_SADDR_REG(DMA_BASE_PTR,28)

#define	DMA_TCD28_SOFF DMA_SOFF_REG(DMA_BASE_PTR,28)

#define	DMA_TCD28_ATTR DMA_ATTR_REG(DMA_BASE_PTR,28)

#define	DMA_TCD28_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,28)

#define	DMA_TCD28_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,28)

#define	DMA_TCD28_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,28)

#define	DMA_TCD28_SLAST DMA_SLAST_REG(DMA_BASE_PTR,28)

#define	DMA_TCD28_DADDR DMA_DADDR_REG(DMA_BASE_PTR,28)

#define	DMA_TCD28_DOFF DMA_DOFF_REG(DMA_BASE_PTR,28)

#define	DMA_TCD28_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,28)

#define	DMA_TCD28_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,28)

#define	DMA_TCD28_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,28)

#define	DMA_TCD28_CSR DMA_CSR_REG(DMA_BASE_PTR,28)

#define	DMA_TCD28_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,28)

#define	DMA_TCD28_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,28)

#define	DMA_TCD29_SADDR DMA_SADDR_REG(DMA_BASE_PTR,29)

#define	DMA_TCD29_SOFF DMA_SOFF_REG(DMA_BASE_PTR,29)

#define	DMA_TCD29_ATTR DMA_ATTR_REG(DMA_BASE_PTR,29)

#define	DMA_TCD29_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,29)

#define	DMA_TCD29_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,29)

#define	DMA_TCD29_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,29)

#define	DMA_TCD29_SLAST DMA_SLAST_REG(DMA_BASE_PTR,29)

#define	DMA_TCD29_DADDR DMA_DADDR_REG(DMA_BASE_PTR,29)

#define	DMA_TCD29_DOFF DMA_DOFF_REG(DMA_BASE_PTR,29)

#define	DMA_TCD29_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,29)

#define	DMA_TCD29_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,29)

#define	DMA_TCD29_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,29)

#define	DMA_TCD29_CSR DMA_CSR_REG(DMA_BASE_PTR,29)

#define	DMA_TCD29_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,29)

#define	DMA_TCD29_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,29)

#define	DMA_TCD30_SADDR DMA_SADDR_REG(DMA_BASE_PTR,30)

#define	DMA_TCD30_SOFF DMA_SOFF_REG(DMA_BASE_PTR,30)

#define	DMA_TCD30_ATTR DMA_ATTR_REG(DMA_BASE_PTR,30)

#define	DMA_TCD30_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,30)

#define	DMA_TCD30_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,30)

#define	DMA_TCD30_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,30)

#define	DMA_TCD30_SLAST DMA_SLAST_REG(DMA_BASE_PTR,30)

#define	DMA_TCD30_DADDR DMA_DADDR_REG(DMA_BASE_PTR,30)

#define	DMA_TCD30_DOFF DMA_DOFF_REG(DMA_BASE_PTR,30)

#define	DMA_TCD30_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,30)

#define	DMA_TCD30_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,30)

#define	DMA_TCD30_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,30)

#define	DMA_TCD30_CSR DMA_CSR_REG(DMA_BASE_PTR,30)

#define	DMA_TCD30_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,30)

#define	DMA_TCD30_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,30)

#define	DMA_TCD31_SADDR DMA_SADDR_REG(DMA_BASE_PTR,31)

#define	DMA_TCD31_SOFF DMA_SOFF_REG(DMA_BASE_PTR,31)

#define	DMA_TCD31_ATTR DMA_ATTR_REG(DMA_BASE_PTR,31)

#define	DMA_TCD31_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,31)

#define	DMA_TCD31_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,31)

#define	DMA_TCD31_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,31)

#define	DMA_TCD31_SLAST DMA_SLAST_REG(DMA_BASE_PTR,31)

#define	DMA_TCD31_DADDR DMA_DADDR_REG(DMA_BASE_PTR,31)

#define	DMA_TCD31_DOFF DMA_DOFF_REG(DMA_BASE_PTR,31)

#define	DMA_TCD31_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,31)

#define	DMA_TCD31_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,31)

#define	DMA_TCD31_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,31)

#define	DMA_TCD31_CSR DMA_CSR_REG(DMA_BASE_PTR,31)

#define	DMA_TCD31_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,31)

#define	DMA_TCD31_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,31)

#define	DMA_SADDR(index) DMA_SADDR_REG(DMA_BASE_PTR,index)

#define	DMA_SOFF(index) DMA_SOFF_REG(DMA_BASE_PTR,index)

#define	DMA_ATTR(index) DMA_ATTR_REG(DMA_BASE_PTR,index)

#define	DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,index)

#define	DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,index)

#define	DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,index)

#define	DMA_SLAST(index) DMA_SLAST_REG(DMA_BASE_PTR,index)

#define	DMA_DADDR(index) DMA_DADDR_REG(DMA_BASE_PTR,index)

#define	DMA_DOFF(index) DMA_DOFF_REG(DMA_BASE_PTR,index)

#define	DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,index)

#define	DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,index)

#define	DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA_BASE_PTR,index)

#define	DMA_CSR(index) DMA_CSR_REG(DMA_BASE_PTR,index)

#define	DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,index)

#define	DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,index)

#define	DMAMUX_CHCFG_REG(base, index) ((base)->CHCFG[index])

#define	DMAMUX_CHCFG_SOURCE_MASK 0x3Fu

#define	DMAMUX_CHCFG_SOURCE_SHIFT 0

#define	DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)

#define	DMAMUX_CHCFG_TRIG_MASK 0x40u

#define	DMAMUX_CHCFG_TRIG_SHIFT 6

#define	DMAMUX_CHCFG_ENBL_MASK 0x80u

#define	DMAMUX_CHCFG_ENBL_SHIFT 7

#define	DMAMUX0_BASE_PTR ((DMAMUX_MemMapPtr)0x40021000u)

#define	DMAMUX1_BASE_PTR ((DMAMUX_MemMapPtr)0x40022000u)

#define	DMAMUX_BASE_PTRS { DMAMUX0_BASE_PTR, DMAMUX1_BASE_PTR }

#define	DMAMUX0_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,0)

#define	DMAMUX0_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,1)

#define	DMAMUX0_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,2)

#define	DMAMUX0_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,3)

#define	DMAMUX0_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,4)

#define	DMAMUX0_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,5)

#define	DMAMUX0_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,6)

#define	DMAMUX0_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,7)

#define	DMAMUX0_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,8)

#define	DMAMUX0_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,9)

#define	DMAMUX0_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,10)

#define	DMAMUX0_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,11)

#define	DMAMUX0_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,12)

#define	DMAMUX0_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,13)

#define	DMAMUX0_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,14)

#define	DMAMUX0_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,15)

#define	DMAMUX1_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX1_BASE_PTR,0)

#define	DMAMUX1_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX1_BASE_PTR,1)

#define	DMAMUX1_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX1_BASE_PTR,2)

#define	DMAMUX1_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX1_BASE_PTR,3)

#define	DMAMUX1_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX1_BASE_PTR,4)

#define	DMAMUX1_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX1_BASE_PTR,5)

#define	DMAMUX1_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX1_BASE_PTR,6)

#define	DMAMUX1_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX1_BASE_PTR,7)

#define	DMAMUX1_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX1_BASE_PTR,8)

#define	DMAMUX1_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX1_BASE_PTR,9)

#define	DMAMUX1_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX1_BASE_PTR,10)

#define	DMAMUX1_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX1_BASE_PTR,11)

#define	DMAMUX1_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX1_BASE_PTR,12)

#define	DMAMUX1_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX1_BASE_PTR,13)

#define	DMAMUX1_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX1_BASE_PTR,14)

#define	DMAMUX1_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX1_BASE_PTR,15)

#define	DMAMUX0_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,index)

#define	DMAMUX1_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX1_BASE_PTR,index)

#define	DWT_CTRL_REG(base) ((base)->CTRL)

#define	DWT_CYCCNT_REG(base) ((base)->CYCCNT)

#define	DWT_CPICNT_REG(base) ((base)->CPICNT)

#define	DWT_EXCCNT_REG(base) ((base)->EXCCNT)

#define	DWT_SLEEPCNT_REG(base) ((base)->SLEEPCNT)

#define	DWT_LSUCNT_REG(base) ((base)->LSUCNT)

#define	DWT_FOLDCNT_REG(base) ((base)->FOLDCNT)

#define	DWT_PCSR_REG(base) ((base)->PCSR)

#define	DWT_COMP_REG(base, index) ((base)->COMPARATOR[index].COMP)

#define	DWT_MASK_REG(base, index) ((base)->COMPARATOR[index].MASK)

#define	DWT_FUNCTION_REG(base, index) ((base)->COMPARATOR[index].FUNCTION)

#define	DWT_PID4_REG(base) ((base)->PID4)

#define	DWT_PID5_REG(base) ((base)->PID5)

#define	DWT_PID6_REG(base) ((base)->PID6)

#define	DWT_PID7_REG(base) ((base)->PID7)

#define	DWT_PID0_REG(base) ((base)->PID0)

#define	DWT_PID1_REG(base) ((base)->PID1)

#define	DWT_PID2_REG(base) ((base)->PID2)

#define	DWT_PID3_REG(base) ((base)->PID3)

#define	DWT_CID0_REG(base) ((base)->CID0)

#define	DWT_CID1_REG(base) ((base)->CID1)

#define	DWT_CID2_REG(base) ((base)->CID2)

#define	DWT_CID3_REG(base) ((base)->CID3)

#define	DWT_BASE_PTR ((DWT_MemMapPtr)0xE0001000u)

#define	DWT_BASE_PTRS { DWT_BASE_PTR }

#define	DWT_CTRL DWT_CTRL_REG(DWT_BASE_PTR)

#define	DWT_CYCCNT DWT_CYCCNT_REG(DWT_BASE_PTR)

#define	DWT_CPICNT DWT_CPICNT_REG(DWT_BASE_PTR)

#define	DWT_EXCCNT DWT_EXCCNT_REG(DWT_BASE_PTR)

#define	DWT_SLEEPCNT DWT_SLEEPCNT_REG(DWT_BASE_PTR)

#define	DWT_LSUCNT DWT_LSUCNT_REG(DWT_BASE_PTR)

#define	DWT_FOLDCNT DWT_FOLDCNT_REG(DWT_BASE_PTR)

#define	DWT_PCSR DWT_PCSR_REG(DWT_BASE_PTR)

#define	DWT_COMP0 DWT_COMP_REG(DWT_BASE_PTR,0)

#define	DWT_MASK0 DWT_MASK_REG(DWT_BASE_PTR,0)

#define	DWT_FUNCTION0 DWT_FUNCTION_REG(DWT_BASE_PTR,0)

#define	DWT_COMP1 DWT_COMP_REG(DWT_BASE_PTR,1)

#define	DWT_MASK1 DWT_MASK_REG(DWT_BASE_PTR,1)

#define	DWT_FUNCTION1 DWT_FUNCTION_REG(DWT_BASE_PTR,1)

#define	DWT_COMP2 DWT_COMP_REG(DWT_BASE_PTR,2)

#define	DWT_MASK2 DWT_MASK_REG(DWT_BASE_PTR,2)

#define	DWT_FUNCTION2 DWT_FUNCTION_REG(DWT_BASE_PTR,2)

#define	DWT_COMP3 DWT_COMP_REG(DWT_BASE_PTR,3)

#define	DWT_MASK3 DWT_MASK_REG(DWT_BASE_PTR,3)

#define	DWT_FUNCTION3 DWT_FUNCTION_REG(DWT_BASE_PTR,3)

#define	DWT_PID4 DWT_PID4_REG(DWT_BASE_PTR)

#define	DWT_PID5 DWT_PID5_REG(DWT_BASE_PTR)

#define	DWT_PID6 DWT_PID6_REG(DWT_BASE_PTR)

#define	DWT_PID7 DWT_PID7_REG(DWT_BASE_PTR)

#define	DWT_PID0 DWT_PID0_REG(DWT_BASE_PTR)

#define	DWT_PID1 DWT_PID1_REG(DWT_BASE_PTR)

#define	DWT_PID2 DWT_PID2_REG(DWT_BASE_PTR)

#define	DWT_PID3 DWT_PID3_REG(DWT_BASE_PTR)

#define	DWT_CID0 DWT_CID0_REG(DWT_BASE_PTR)

#define	DWT_CID1 DWT_CID1_REG(DWT_BASE_PTR)

#define	DWT_CID2 DWT_CID2_REG(DWT_BASE_PTR)

#define	DWT_CID3 DWT_CID3_REG(DWT_BASE_PTR)

#define	DWT_COMP(index) DWT_COMP_REG(DWT_BASE_PTR,index)

#define	DWT_MASK(index) DWT_MASK_REG(DWT_BASE_PTR,index)

#define	DWT_FUNCTION(index) DWT_FUNCTION_REG(DWT_BASE_PTR,index)

#define	ENET_EIR_REG(base) ((base)->EIR)

#define	ENET_EIMR_REG(base) ((base)->EIMR)

#define	ENET_RDAR_REG(base) ((base)->RDAR)

#define	ENET_TDAR_REG(base) ((base)->TDAR)

#define	ENET_ECR_REG(base) ((base)->ECR)

#define	ENET_MMFR_REG(base) ((base)->MMFR)

#define	ENET_MSCR_REG(base) ((base)->MSCR)

#define	ENET_MIBC_REG(base) ((base)->MIBC)

#define	ENET_RCR_REG(base) ((base)->RCR)

#define	ENET_TCR_REG(base) ((base)->TCR)

#define	ENET_PALR_REG(base) ((base)->PALR)

#define	ENET_PAUR_REG(base) ((base)->PAUR)

#define	ENET_OPD_REG(base) ((base)->OPD)

#define	ENET_IAUR_REG(base) ((base)->IAUR)

#define	ENET_IALR_REG(base) ((base)->IALR)

#define	ENET_GAUR_REG(base) ((base)->GAUR)

#define	ENET_GALR_REG(base) ((base)->GALR)

#define	ENET_TFWR_REG(base) ((base)->TFWR)

#define	ENET_RDSR_REG(base) ((base)->RDSR)

#define	ENET_TDSR_REG(base) ((base)->TDSR)

#define	ENET_MRBR_REG(base) ((base)->MRBR)

#define	ENET_RSFL_REG(base) ((base)->RSFL)

#define	ENET_RSEM_REG(base) ((base)->RSEM)

#define	ENET_RAEM_REG(base) ((base)->RAEM)

#define	ENET_RAFL_REG(base) ((base)->RAFL)

#define	ENET_TSEM_REG(base) ((base)->TSEM)

#define	ENET_TAEM_REG(base) ((base)->TAEM)

#define	ENET_TAFL_REG(base) ((base)->TAFL)

#define	ENET_TIPG_REG(base) ((base)->TIPG)

#define	ENET_FTRL_REG(base) ((base)->FTRL)

#define	ENET_TACC_REG(base) ((base)->TACC)

#define	ENET_RACC_REG(base) ((base)->RACC)

#define	ENET_RMON_T_DROP_REG(base) ((base)->RMON_T_DROP)

#define	ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS)

#define	ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT)

#define	ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT)

#define	ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN)

#define	ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE)

#define	ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE)

#define	ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG)

#define	ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB)

#define	ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL)

#define	ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64)

#define	ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127)

#define	ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255)

#define	ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511)

#define	ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023)

#define	ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047)

#define	ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048)

#define	ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS)

#define	ENET_IEEE_T_DROP_REG(base) ((base)->IEEE_T_DROP)

#define	ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK)

#define	ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL)

#define	ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL)

#define	ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF)

#define	ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL)

#define	ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL)

#define	ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR)

#define	ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR)

#define	ENET_IEEE_T_SQE_REG(base) ((base)->IEEE_T_SQE)

#define	ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC)

#define	ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK)

#define	ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS)

#define	ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT)

#define	ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT)

#define	ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN)

#define	ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE)

#define	ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE)

#define	ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG)

#define	ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB)

#define	ENET_RMON_R_RESVD_0_REG(base) ((base)->RMON_R_RESVD_0)

#define	ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64)

#define	ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127)

#define	ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255)

#define	ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511)

#define	ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023)

#define	ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047)

#define	ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048)

#define	ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS)

#define	ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP)

#define	ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK)

#define	ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC)

#define	ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN)

#define	ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR)

#define	ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC)

#define	ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK)

#define	ENET_ATCR_REG(base) ((base)->ATCR)

#define	ENET_ATVR_REG(base) ((base)->ATVR)

#define	ENET_ATOFF_REG(base) ((base)->ATOFF)

#define	ENET_ATPER_REG(base) ((base)->ATPER)

#define	ENET_ATCOR_REG(base) ((base)->ATCOR)

#define	ENET_ATINC_REG(base) ((base)->ATINC)

#define	ENET_ATSTMP_REG(base) ((base)->ATSTMP)

#define	ENET_TGSR_REG(base) ((base)->TGSR)

#define	ENET_TCSR_REG(base, index) ((base)->CHANNEL[index].TCSR)

#define	ENET_TCCR_REG(base, index) ((base)->CHANNEL[index].TCCR)

#define	ENET_EIR_TS_TIMER_MASK 0x8000u

#define	ENET_EIR_TS_TIMER_SHIFT 15

#define	ENET_EIR_TS_AVAIL_MASK 0x10000u

#define	ENET_EIR_TS_AVAIL_SHIFT 16

#define	ENET_EIR_WAKEUP_MASK 0x20000u

#define	ENET_EIR_WAKEUP_SHIFT 17

#define	ENET_EIR_PLR_MASK 0x40000u

#define	ENET_EIR_PLR_SHIFT 18

#define	ENET_EIR_UN_MASK 0x80000u

#define	ENET_EIR_UN_SHIFT 19

#define	ENET_EIR_RL_MASK 0x100000u

#define	ENET_EIR_RL_SHIFT 20

#define	ENET_EIR_LC_MASK 0x200000u

#define	ENET_EIR_LC_SHIFT 21

#define	ENET_EIR_EBERR_MASK 0x400000u

#define	ENET_EIR_EBERR_SHIFT 22

#define	ENET_EIR_MII_MASK 0x800000u

#define	ENET_EIR_MII_SHIFT 23

#define	ENET_EIR_RXB_MASK 0x1000000u

#define	ENET_EIR_RXB_SHIFT 24

#define	ENET_EIR_RXF_MASK 0x2000000u

#define	ENET_EIR_RXF_SHIFT 25

#define	ENET_EIR_TXB_MASK 0x4000000u

#define	ENET_EIR_TXB_SHIFT 26

#define	ENET_EIR_TXF_MASK 0x8000000u

#define	ENET_EIR_TXF_SHIFT 27

#define	ENET_EIR_GRA_MASK 0x10000000u

#define	ENET_EIR_GRA_SHIFT 28

#define	ENET_EIR_BABT_MASK 0x20000000u

#define	ENET_EIR_BABT_SHIFT 29

#define	ENET_EIR_BABR_MASK 0x40000000u

#define	ENET_EIR_BABR_SHIFT 30

#define	ENET_EIMR_TS_TIMER_MASK 0x8000u

#define	ENET_EIMR_TS_TIMER_SHIFT 15

#define	ENET_EIMR_TS_AVAIL_MASK 0x10000u

#define	ENET_EIMR_TS_AVAIL_SHIFT 16

#define	ENET_EIMR_WAKEUP_MASK 0x20000u

#define	ENET_EIMR_WAKEUP_SHIFT 17

#define	ENET_EIMR_PLR_MASK 0x40000u

#define	ENET_EIMR_PLR_SHIFT 18

#define	ENET_EIMR_UN_MASK 0x80000u

#define	ENET_EIMR_UN_SHIFT 19

#define	ENET_EIMR_RL_MASK 0x100000u

#define	ENET_EIMR_RL_SHIFT 20

#define	ENET_EIMR_LC_MASK 0x200000u

#define	ENET_EIMR_LC_SHIFT 21

#define	ENET_EIMR_EBERR_MASK 0x400000u

#define	ENET_EIMR_EBERR_SHIFT 22

#define	ENET_EIMR_MII_MASK 0x800000u

#define	ENET_EIMR_MII_SHIFT 23

#define	ENET_EIMR_RXB_MASK 0x1000000u

#define	ENET_EIMR_RXB_SHIFT 24

#define	ENET_EIMR_RXF_MASK 0x2000000u

#define	ENET_EIMR_RXF_SHIFT 25

#define	ENET_EIMR_TXB_MASK 0x4000000u

#define	ENET_EIMR_TXB_SHIFT 26

#define	ENET_EIMR_TXF_MASK 0x8000000u

#define	ENET_EIMR_TXF_SHIFT 27

#define	ENET_EIMR_GRA_MASK 0x10000000u

#define	ENET_EIMR_GRA_SHIFT 28

#define	ENET_EIMR_BABT_MASK 0x20000000u

#define	ENET_EIMR_BABT_SHIFT 29

#define	ENET_EIMR_BABR_MASK 0x40000000u

#define	ENET_EIMR_BABR_SHIFT 30

#define	ENET_RDAR_RDAR_MASK 0x1000000u

#define	ENET_RDAR_RDAR_SHIFT 24

#define	ENET_TDAR_TDAR_MASK 0x1000000u

#define	ENET_TDAR_TDAR_SHIFT 24

#define	ENET_ECR_RESET_MASK 0x1u

#define	ENET_ECR_RESET_SHIFT 0

#define	ENET_ECR_ETHEREN_MASK 0x2u

#define	ENET_ECR_ETHEREN_SHIFT 1

#define	ENET_ECR_MAGICEN_MASK 0x4u

#define	ENET_ECR_MAGICEN_SHIFT 2

#define	ENET_ECR_SLEEP_MASK 0x8u

#define	ENET_ECR_SLEEP_SHIFT 3

#define	ENET_ECR_EN1588_MASK 0x10u

#define	ENET_ECR_EN1588_SHIFT 4

#define	ENET_ECR_DBGEN_MASK 0x40u

#define	ENET_ECR_DBGEN_SHIFT 6

#define	ENET_ECR_STOPEN_MASK 0x80u

#define	ENET_ECR_STOPEN_SHIFT 7

#define	ENET_ECR_DBSWP_MASK 0x100u

#define	ENET_ECR_DBSWP_SHIFT 8

#define	ENET_MMFR_DATA_MASK 0xFFFFu

#define	ENET_MMFR_DATA_SHIFT 0

#define	ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)

#define	ENET_MMFR_TA_MASK 0x30000u

#define	ENET_MMFR_TA_SHIFT 16

#define	ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)

#define	ENET_MMFR_RA_MASK 0x7C0000u

#define	ENET_MMFR_RA_SHIFT 18

#define	ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)

#define	ENET_MMFR_PA_MASK 0xF800000u

#define	ENET_MMFR_PA_SHIFT 23

#define	ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)

#define	ENET_MMFR_OP_MASK 0x30000000u

#define	ENET_MMFR_OP_SHIFT 28

#define	ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)

#define	ENET_MMFR_ST_MASK 0xC0000000u

#define	ENET_MMFR_ST_SHIFT 30

#define	ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)

#define	ENET_MSCR_MII_SPEED_MASK 0x7Eu

#define	ENET_MSCR_MII_SPEED_SHIFT 1

#define	ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)

#define	ENET_MSCR_DIS_PRE_MASK 0x80u

#define	ENET_MSCR_DIS_PRE_SHIFT 7

#define	ENET_MSCR_HOLDTIME_MASK 0x700u

#define	ENET_MSCR_HOLDTIME_SHIFT 8

#define	ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)

#define	ENET_MIBC_MIB_CLEAR_MASK 0x20000000u

#define	ENET_MIBC_MIB_CLEAR_SHIFT 29

#define	ENET_MIBC_MIB_IDLE_MASK 0x40000000u

#define	ENET_MIBC_MIB_IDLE_SHIFT 30

#define	ENET_MIBC_MIB_DIS_MASK 0x80000000u

#define	ENET_MIBC_MIB_DIS_SHIFT 31

#define	ENET_RCR_LOOP_MASK 0x1u

#define	ENET_RCR_LOOP_SHIFT 0

#define	ENET_RCR_DRT_MASK 0x2u

#define	ENET_RCR_DRT_SHIFT 1

#define	ENET_RCR_MII_MODE_MASK 0x4u

#define	ENET_RCR_MII_MODE_SHIFT 2

#define	ENET_RCR_PROM_MASK 0x8u

#define	ENET_RCR_PROM_SHIFT 3

#define	ENET_RCR_BC_REJ_MASK 0x10u

#define	ENET_RCR_BC_REJ_SHIFT 4

#define	ENET_RCR_FCE_MASK 0x20u

#define	ENET_RCR_FCE_SHIFT 5

#define	ENET_RCR_RMII_MODE_MASK 0x100u

#define	ENET_RCR_RMII_MODE_SHIFT 8

#define	ENET_RCR_RMII_10T_MASK 0x200u

#define	ENET_RCR_RMII_10T_SHIFT 9

#define	ENET_RCR_PADEN_MASK 0x1000u

#define	ENET_RCR_PADEN_SHIFT 12

#define	ENET_RCR_PAUFWD_MASK 0x2000u

#define	ENET_RCR_PAUFWD_SHIFT 13

#define	ENET_RCR_CRCFWD_MASK 0x4000u

#define	ENET_RCR_CRCFWD_SHIFT 14

#define	ENET_RCR_CFEN_MASK 0x8000u

#define	ENET_RCR_CFEN_SHIFT 15

#define	ENET_RCR_MAX_FL_MASK 0x3FFF0000u

#define	ENET_RCR_MAX_FL_SHIFT 16

#define	ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)

#define	ENET_RCR_NLC_MASK 0x40000000u

#define	ENET_RCR_NLC_SHIFT 30

#define	ENET_RCR_GRS_MASK 0x80000000u

#define	ENET_RCR_GRS_SHIFT 31

#define	ENET_TCR_GTS_MASK 0x1u

#define	ENET_TCR_GTS_SHIFT 0

#define	ENET_TCR_FDEN_MASK 0x4u

#define	ENET_TCR_FDEN_SHIFT 2

#define	ENET_TCR_TFC_PAUSE_MASK 0x8u

#define	ENET_TCR_TFC_PAUSE_SHIFT 3

#define	ENET_TCR_RFC_PAUSE_MASK 0x10u

#define	ENET_TCR_RFC_PAUSE_SHIFT 4

#define	ENET_TCR_ADDSEL_MASK 0xE0u

#define	ENET_TCR_ADDSEL_SHIFT 5

#define	ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)

#define	ENET_TCR_ADDINS_MASK 0x100u

#define	ENET_TCR_ADDINS_SHIFT 8

#define	ENET_TCR_CRCFWD_MASK 0x200u

#define	ENET_TCR_CRCFWD_SHIFT 9

#define	ENET_PALR_PADDR1_MASK 0xFFFFFFFFu

#define	ENET_PALR_PADDR1_SHIFT 0

#define	ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)

#define	ENET_PAUR_TYPE_MASK 0xFFFFu

#define	ENET_PAUR_TYPE_SHIFT 0

#define	ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)

#define	ENET_PAUR_PADDR2_MASK 0xFFFF0000u

#define	ENET_PAUR_PADDR2_SHIFT 16

#define	ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)

#define	ENET_OPD_PAUSE_DUR_MASK 0xFFFFu

#define	ENET_OPD_PAUSE_DUR_SHIFT 0

#define	ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)

#define	ENET_OPD_OPCODE_MASK 0xFFFF0000u

#define	ENET_OPD_OPCODE_SHIFT 16

#define	ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)

#define	ENET_IAUR_IADDR1_MASK 0xFFFFFFFFu

#define	ENET_IAUR_IADDR1_SHIFT 0

#define	ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)

#define	ENET_IALR_IADDR2_MASK 0xFFFFFFFFu

#define	ENET_IALR_IADDR2_SHIFT 0

#define	ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)

#define	ENET_GAUR_GADDR1_MASK 0xFFFFFFFFu

#define	ENET_GAUR_GADDR1_SHIFT 0

#define	ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)

#define	ENET_GALR_GADDR2_MASK 0xFFFFFFFFu

#define	ENET_GALR_GADDR2_SHIFT 0

#define	ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)

#define	ENET_TFWR_TFWR_MASK 0x3Fu

#define	ENET_TFWR_TFWR_SHIFT 0

#define	ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)

#define	ENET_TFWR_STRFWD_MASK 0x100u

#define	ENET_TFWR_STRFWD_SHIFT 8

#define	ENET_RDSR_R_DES_START_MASK 0xFFFFFFF8u

#define	ENET_RDSR_R_DES_START_SHIFT 3

#define	ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)

#define	ENET_TDSR_X_DES_START_MASK 0xFFFFFFF8u

#define	ENET_TDSR_X_DES_START_SHIFT 3

#define	ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)

#define	ENET_MRBR_R_BUF_SIZE_MASK 0x3FF0u

#define	ENET_MRBR_R_BUF_SIZE_SHIFT 4

#define	ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)

#define	ENET_RSFL_RX_SECTION_FULL_MASK 0xFFu

#define	ENET_RSFL_RX_SECTION_FULL_SHIFT 0

#define	ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)

#define	ENET_RSEM_RX_SECTION_EMPTY_MASK 0xFFu

#define	ENET_RSEM_RX_SECTION_EMPTY_SHIFT 0

#define	ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)

#define	ENET_RAEM_RX_ALMOST_EMPTY_MASK 0xFFu

#define	ENET_RAEM_RX_ALMOST_EMPTY_SHIFT 0

#define	ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)

#define	ENET_RAFL_RX_ALMOST_FULL_MASK 0xFFu

#define	ENET_RAFL_RX_ALMOST_FULL_SHIFT 0

#define	ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)

#define	ENET_TSEM_TX_SECTION_EMPTY_MASK 0xFFu

#define	ENET_TSEM_TX_SECTION_EMPTY_SHIFT 0

#define	ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)

#define	ENET_TAEM_TX_ALMOST_EMPTY_MASK 0xFFu

#define	ENET_TAEM_TX_ALMOST_EMPTY_SHIFT 0

#define	ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)

#define	ENET_TAFL_TX_ALMOST_FULL_MASK 0xFFu

#define	ENET_TAFL_TX_ALMOST_FULL_SHIFT 0

#define	ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)

#define	ENET_TIPG_IPG_MASK 0x1Fu

#define	ENET_TIPG_IPG_SHIFT 0

#define	ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)

#define	ENET_FTRL_TRUNC_FL_MASK 0x3FFFu

#define	ENET_FTRL_TRUNC_FL_SHIFT 0

#define	ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)

#define	ENET_TACC_SHIFT16_MASK 0x1u

#define	ENET_TACC_SHIFT16_SHIFT 0

#define	ENET_TACC_IPCHK_MASK 0x8u

#define	ENET_TACC_IPCHK_SHIFT 3

#define	ENET_TACC_PROCHK_MASK 0x10u

#define	ENET_TACC_PROCHK_SHIFT 4

#define	ENET_RACC_PADREM_MASK 0x1u

#define	ENET_RACC_PADREM_SHIFT 0

#define	ENET_RACC_IPDIS_MASK 0x2u

#define	ENET_RACC_IPDIS_SHIFT 1

#define	ENET_RACC_PRODIS_MASK 0x4u

#define	ENET_RACC_PRODIS_SHIFT 2

#define	ENET_RACC_LINEDIS_MASK 0x40u

#define	ENET_RACC_LINEDIS_SHIFT 6

#define	ENET_RACC_SHIFT16_MASK 0x80u

#define	ENET_RACC_SHIFT16_SHIFT 7

#define	ENET_RMON_T_PACKETS_TXPKTS_MASK 0xFFFFu

#define	ENET_RMON_T_PACKETS_TXPKTS_SHIFT 0

#define	ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)

#define	ENET_RMON_T_BC_PKT_TXPKTS_MASK 0xFFFFu

#define	ENET_RMON_T_BC_PKT_TXPKTS_SHIFT 0

#define	ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)

#define	ENET_RMON_T_MC_PKT_TXPKTS_MASK 0xFFFFu

#define	ENET_RMON_T_MC_PKT_TXPKTS_SHIFT 0

#define	ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)

#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK 0xFFFFu

#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT 0

#define	ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)

#define	ENET_RMON_T_UNDERSIZE_TXPKTS_MASK 0xFFFFu

#define	ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT 0

#define	ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)

#define	ENET_RMON_T_OVERSIZE_TXPKTS_MASK 0xFFFFu

#define	ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT 0

#define	ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)

#define	ENET_RMON_T_FRAG_TXPKTS_MASK 0xFFFFu

#define	ENET_RMON_T_FRAG_TXPKTS_SHIFT 0

#define	ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)

#define	ENET_RMON_T_JAB_TXPKTS_MASK 0xFFFFu

#define	ENET_RMON_T_JAB_TXPKTS_SHIFT 0

#define	ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)

#define	ENET_RMON_T_COL_TXPKTS_MASK 0xFFFFu

#define	ENET_RMON_T_COL_TXPKTS_SHIFT 0

#define	ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)

#define	ENET_RMON_T_P64_TXPKTS_MASK 0xFFFFu

#define	ENET_RMON_T_P64_TXPKTS_SHIFT 0

#define	ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)

#define	ENET_RMON_T_P65TO127_TXPKTS_MASK 0xFFFFu

#define	ENET_RMON_T_P65TO127_TXPKTS_SHIFT 0

#define	ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)

#define	ENET_RMON_T_P128TO255_TXPKTS_MASK 0xFFFFu

#define	ENET_RMON_T_P128TO255_TXPKTS_SHIFT 0

#define	ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)

#define	ENET_RMON_T_P256TO511_TXPKTS_MASK 0xFFFFu

#define	ENET_RMON_T_P256TO511_TXPKTS_SHIFT 0

#define	ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)

#define	ENET_RMON_T_P512TO1023_TXPKTS_MASK 0xFFFFu

#define	ENET_RMON_T_P512TO1023_TXPKTS_SHIFT 0

#define	ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)

#define	ENET_RMON_T_P1024TO2047_TXPKTS_MASK 0xFFFFu

#define	ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT 0

#define	ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)

#define	ENET_RMON_T_P_GTE2048_TXPKTS_MASK 0xFFFFu

#define	ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT 0

#define	ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)

#define	ENET_RMON_T_OCTETS_TXOCTS_MASK 0xFFFFFFFFu

#define	ENET_RMON_T_OCTETS_TXOCTS_SHIFT 0

#define	ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)

#define	ENET_IEEE_T_FRAME_OK_COUNT_MASK 0xFFFFu

#define	ENET_IEEE_T_FRAME_OK_COUNT_SHIFT 0

#define	ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)

#define	ENET_IEEE_T_1COL_COUNT_MASK 0xFFFFu

#define	ENET_IEEE_T_1COL_COUNT_SHIFT 0

#define	ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)

#define	ENET_IEEE_T_MCOL_COUNT_MASK 0xFFFFu

#define	ENET_IEEE_T_MCOL_COUNT_SHIFT 0

#define	ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)

#define	ENET_IEEE_T_DEF_COUNT_MASK 0xFFFFu

#define	ENET_IEEE_T_DEF_COUNT_SHIFT 0

#define	ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)

#define	ENET_IEEE_T_LCOL_COUNT_MASK 0xFFFFu

#define	ENET_IEEE_T_LCOL_COUNT_SHIFT 0

#define	ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)

#define	ENET_IEEE_T_EXCOL_COUNT_MASK 0xFFFFu

#define	ENET_IEEE_T_EXCOL_COUNT_SHIFT 0

#define	ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)

#define	ENET_IEEE_T_MACERR_COUNT_MASK 0xFFFFu

#define	ENET_IEEE_T_MACERR_COUNT_SHIFT 0

#define	ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)

#define	ENET_IEEE_T_CSERR_COUNT_MASK 0xFFFFu

#define	ENET_IEEE_T_CSERR_COUNT_SHIFT 0

#define	ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)

#define	ENET_IEEE_T_FDXFC_COUNT_MASK 0xFFFFu

#define	ENET_IEEE_T_FDXFC_COUNT_SHIFT 0

#define	ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)

#define	ENET_IEEE_T_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu

#define	ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT 0

#define	ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)

#define	ENET_RMON_R_PACKETS_COUNT_MASK 0xFFFFu

#define	ENET_RMON_R_PACKETS_COUNT_SHIFT 0

#define	ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)

#define	ENET_RMON_R_BC_PKT_COUNT_MASK 0xFFFFu

#define	ENET_RMON_R_BC_PKT_COUNT_SHIFT 0

#define	ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)

#define	ENET_RMON_R_MC_PKT_COUNT_MASK 0xFFFFu

#define	ENET_RMON_R_MC_PKT_COUNT_SHIFT 0

#define	ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)

#define	ENET_RMON_R_CRC_ALIGN_COUNT_MASK 0xFFFFu

#define	ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT 0

#define	ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)

#define	ENET_RMON_R_UNDERSIZE_COUNT_MASK 0xFFFFu

#define	ENET_RMON_R_UNDERSIZE_COUNT_SHIFT 0

#define	ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)

#define	ENET_RMON_R_OVERSIZE_COUNT_MASK 0xFFFFu

#define	ENET_RMON_R_OVERSIZE_COUNT_SHIFT 0

#define	ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)

#define	ENET_RMON_R_FRAG_COUNT_MASK 0xFFFFu

#define	ENET_RMON_R_FRAG_COUNT_SHIFT 0

#define	ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)

#define	ENET_RMON_R_JAB_COUNT_MASK 0xFFFFu

#define	ENET_RMON_R_JAB_COUNT_SHIFT 0

#define	ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)

#define	ENET_RMON_R_P64_COUNT_MASK 0xFFFFu

#define	ENET_RMON_R_P64_COUNT_SHIFT 0

#define	ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)

#define	ENET_RMON_R_P65TO127_COUNT_MASK 0xFFFFu

#define	ENET_RMON_R_P65TO127_COUNT_SHIFT 0

#define	ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)

#define	ENET_RMON_R_P128TO255_COUNT_MASK 0xFFFFu

#define	ENET_RMON_R_P128TO255_COUNT_SHIFT 0

#define	ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)

#define	ENET_RMON_R_P256TO511_COUNT_MASK 0xFFFFu

#define	ENET_RMON_R_P256TO511_COUNT_SHIFT 0

#define	ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)

#define	ENET_RMON_R_P512TO1023_COUNT_MASK 0xFFFFu

#define	ENET_RMON_R_P512TO1023_COUNT_SHIFT 0

#define	ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)

#define	ENET_RMON_R_P1024TO2047_COUNT_MASK 0xFFFFu

#define	ENET_RMON_R_P1024TO2047_COUNT_SHIFT 0

#define	ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)

#define	ENET_RMON_R_P_GTE2048_COUNT_MASK 0xFFFFu

#define	ENET_RMON_R_P_GTE2048_COUNT_SHIFT 0

#define	ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)

#define	ENET_RMON_R_OCTETS_COUNT_MASK 0xFFFFFFFFu

#define	ENET_RMON_R_OCTETS_COUNT_SHIFT 0

#define	ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)

#define	ENET_IEEE_R_DROP_COUNT_MASK 0xFFFFu

#define	ENET_IEEE_R_DROP_COUNT_SHIFT 0

#define	ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)

#define	ENET_IEEE_R_FRAME_OK_COUNT_MASK 0xFFFFu

#define	ENET_IEEE_R_FRAME_OK_COUNT_SHIFT 0

#define	ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)

#define	ENET_IEEE_R_CRC_COUNT_MASK 0xFFFFu

#define	ENET_IEEE_R_CRC_COUNT_SHIFT 0

#define	ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)

#define	ENET_IEEE_R_ALIGN_COUNT_MASK 0xFFFFu

#define	ENET_IEEE_R_ALIGN_COUNT_SHIFT 0

#define	ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)

#define	ENET_IEEE_R_MACERR_COUNT_MASK 0xFFFFu

#define	ENET_IEEE_R_MACERR_COUNT_SHIFT 0

#define	ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)

#define	ENET_IEEE_R_FDXFC_COUNT_MASK 0xFFFFu

#define	ENET_IEEE_R_FDXFC_COUNT_SHIFT 0

#define	ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)

#define	ENET_IEEE_R_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu

#define	ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT 0

#define	ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)

#define	ENET_ATCR_EN_MASK 0x1u

#define	ENET_ATCR_EN_SHIFT 0

#define	ENET_ATCR_OFFEN_MASK 0x4u

#define	ENET_ATCR_OFFEN_SHIFT 2

#define	ENET_ATCR_OFFRST_MASK 0x8u

#define	ENET_ATCR_OFFRST_SHIFT 3

#define	ENET_ATCR_PEREN_MASK 0x10u

#define	ENET_ATCR_PEREN_SHIFT 4

#define	ENET_ATCR_PINPER_MASK 0x80u

#define	ENET_ATCR_PINPER_SHIFT 7

#define	ENET_ATCR_RESTART_MASK 0x200u

#define	ENET_ATCR_RESTART_SHIFT 9

#define	ENET_ATCR_CAPTURE_MASK 0x800u

#define	ENET_ATCR_CAPTURE_SHIFT 11

#define	ENET_ATCR_SLAVE_MASK 0x2000u

#define	ENET_ATCR_SLAVE_SHIFT 13

#define	ENET_ATVR_ATIME_MASK 0xFFFFFFFFu

#define	ENET_ATVR_ATIME_SHIFT 0

#define	ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)

#define	ENET_ATOFF_OFFSET_MASK 0xFFFFFFFFu

#define	ENET_ATOFF_OFFSET_SHIFT 0

#define	ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)

#define	ENET_ATPER_PERIOD_MASK 0xFFFFFFFFu

#define	ENET_ATPER_PERIOD_SHIFT 0

#define	ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)

#define	ENET_ATCOR_COR_MASK 0x7FFFFFFFu

#define	ENET_ATCOR_COR_SHIFT 0

#define	ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)

#define	ENET_ATINC_INC_MASK 0x7Fu

#define	ENET_ATINC_INC_SHIFT 0

#define	ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)

#define	ENET_ATINC_INC_CORR_MASK 0x7F00u

#define	ENET_ATINC_INC_CORR_SHIFT 8

#define	ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)

#define	ENET_ATSTMP_TIMESTAMP_MASK 0xFFFFFFFFu

#define	ENET_ATSTMP_TIMESTAMP_SHIFT 0

#define	ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)

#define	ENET_TGSR_TF0_MASK 0x1u

#define	ENET_TGSR_TF0_SHIFT 0

#define	ENET_TGSR_TF1_MASK 0x2u

#define	ENET_TGSR_TF1_SHIFT 1

#define	ENET_TGSR_TF2_MASK 0x4u

#define	ENET_TGSR_TF2_SHIFT 2

#define	ENET_TGSR_TF3_MASK 0x8u

#define	ENET_TGSR_TF3_SHIFT 3

#define	ENET_TCSR_TDRE_MASK 0x1u

#define	ENET_TCSR_TDRE_SHIFT 0

#define	ENET_TCSR_TMODE_MASK 0x3Cu

#define	ENET_TCSR_TMODE_SHIFT 2

#define	ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)

#define	ENET_TCSR_TIE_MASK 0x40u

#define	ENET_TCSR_TIE_SHIFT 6

#define	ENET_TCSR_TF_MASK 0x80u

#define	ENET_TCSR_TF_SHIFT 7

#define	ENET_TCCR_TCC_MASK 0xFFFFFFFFu

#define	ENET_TCCR_TCC_SHIFT 0

#define	ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)

#define	ENET_BASE_PTR ((ENET_MemMapPtr)0x400C0000u)

#define	ENET_BASE_PTRS { ENET_BASE_PTR }

#define	ENET_EIR ENET_EIR_REG(ENET_BASE_PTR)

#define	ENET_EIMR ENET_EIMR_REG(ENET_BASE_PTR)

#define	ENET_RDAR ENET_RDAR_REG(ENET_BASE_PTR)

#define	ENET_TDAR ENET_TDAR_REG(ENET_BASE_PTR)

#define	ENET_ECR ENET_ECR_REG(ENET_BASE_PTR)

#define	ENET_MMFR ENET_MMFR_REG(ENET_BASE_PTR)

#define	ENET_MSCR ENET_MSCR_REG(ENET_BASE_PTR)

#define	ENET_MIBC ENET_MIBC_REG(ENET_BASE_PTR)

#define	ENET_RCR ENET_RCR_REG(ENET_BASE_PTR)

#define	ENET_TCR ENET_TCR_REG(ENET_BASE_PTR)

#define	ENET_PALR ENET_PALR_REG(ENET_BASE_PTR)

#define	ENET_PAUR ENET_PAUR_REG(ENET_BASE_PTR)

#define	ENET_OPD ENET_OPD_REG(ENET_BASE_PTR)

#define	ENET_IAUR ENET_IAUR_REG(ENET_BASE_PTR)

#define	ENET_IALR ENET_IALR_REG(ENET_BASE_PTR)

#define	ENET_GAUR ENET_GAUR_REG(ENET_BASE_PTR)

#define	ENET_GALR ENET_GALR_REG(ENET_BASE_PTR)

#define	ENET_TFWR ENET_TFWR_REG(ENET_BASE_PTR)

#define	ENET_RDSR ENET_RDSR_REG(ENET_BASE_PTR)

#define	ENET_TDSR ENET_TDSR_REG(ENET_BASE_PTR)

#define	ENET_MRBR ENET_MRBR_REG(ENET_BASE_PTR)

#define	ENET_RSFL ENET_RSFL_REG(ENET_BASE_PTR)

#define	ENET_RSEM ENET_RSEM_REG(ENET_BASE_PTR)

#define	ENET_RAEM ENET_RAEM_REG(ENET_BASE_PTR)

#define	ENET_RAFL ENET_RAFL_REG(ENET_BASE_PTR)

#define	ENET_TSEM ENET_TSEM_REG(ENET_BASE_PTR)

#define	ENET_TAEM ENET_TAEM_REG(ENET_BASE_PTR)

#define	ENET_TAFL ENET_TAFL_REG(ENET_BASE_PTR)

#define	ENET_TIPG ENET_TIPG_REG(ENET_BASE_PTR)

#define	ENET_FTRL ENET_FTRL_REG(ENET_BASE_PTR)

#define	ENET_TACC ENET_TACC_REG(ENET_BASE_PTR)

#define	ENET_RACC ENET_RACC_REG(ENET_BASE_PTR)

#define	ENET_RMON_T_DROP ENET_RMON_T_DROP_REG(ENET_BASE_PTR)

#define	ENET_RMON_T_PACKETS ENET_RMON_T_PACKETS_REG(ENET_BASE_PTR)

#define	ENET_RMON_T_BC_PKT ENET_RMON_T_BC_PKT_REG(ENET_BASE_PTR)

#define	ENET_RMON_T_MC_PKT ENET_RMON_T_MC_PKT_REG(ENET_BASE_PTR)

#define	ENET_RMON_T_CRC_ALIGN ENET_RMON_T_CRC_ALIGN_REG(ENET_BASE_PTR)

#define	ENET_RMON_T_UNDERSIZE ENET_RMON_T_UNDERSIZE_REG(ENET_BASE_PTR)

#define	ENET_RMON_T_OVERSIZE ENET_RMON_T_OVERSIZE_REG(ENET_BASE_PTR)

#define	ENET_RMON_T_FRAG ENET_RMON_T_FRAG_REG(ENET_BASE_PTR)

#define	ENET_RMON_T_JAB ENET_RMON_T_JAB_REG(ENET_BASE_PTR)

#define	ENET_RMON_T_COL ENET_RMON_T_COL_REG(ENET_BASE_PTR)

#define	ENET_RMON_T_P64 ENET_RMON_T_P64_REG(ENET_BASE_PTR)

#define	ENET_RMON_T_P65TO127 ENET_RMON_T_P65TO127_REG(ENET_BASE_PTR)

#define	ENET_RMON_T_P128TO255 ENET_RMON_T_P128TO255_REG(ENET_BASE_PTR)

#define	ENET_RMON_T_P256TO511 ENET_RMON_T_P256TO511_REG(ENET_BASE_PTR)

#define	ENET_RMON_T_P512TO1023 ENET_RMON_T_P512TO1023_REG(ENET_BASE_PTR)

#define	ENET_RMON_T_P1024TO2047 ENET_RMON_T_P1024TO2047_REG(ENET_BASE_PTR)

#define	ENET_RMON_T_P_GTE2048 ENET_RMON_T_P_GTE2048_REG(ENET_BASE_PTR)

#define	ENET_RMON_T_OCTETS ENET_RMON_T_OCTETS_REG(ENET_BASE_PTR)

#define	ENET_IEEE_T_DROP ENET_IEEE_T_DROP_REG(ENET_BASE_PTR)

#define	ENET_IEEE_T_FRAME_OK ENET_IEEE_T_FRAME_OK_REG(ENET_BASE_PTR)

#define	ENET_IEEE_T_1COL ENET_IEEE_T_1COL_REG(ENET_BASE_PTR)

#define	ENET_IEEE_T_MCOL ENET_IEEE_T_MCOL_REG(ENET_BASE_PTR)

#define	ENET_IEEE_T_DEF ENET_IEEE_T_DEF_REG(ENET_BASE_PTR)

#define	ENET_IEEE_T_LCOL ENET_IEEE_T_LCOL_REG(ENET_BASE_PTR)

#define	ENET_IEEE_T_EXCOL ENET_IEEE_T_EXCOL_REG(ENET_BASE_PTR)

#define	ENET_IEEE_T_MACERR ENET_IEEE_T_MACERR_REG(ENET_BASE_PTR)

#define	ENET_IEEE_T_CSERR ENET_IEEE_T_CSERR_REG(ENET_BASE_PTR)

#define	ENET_IEEE_T_SQE ENET_IEEE_T_SQE_REG(ENET_BASE_PTR)

#define	ENET_IEEE_T_FDXFC ENET_IEEE_T_FDXFC_REG(ENET_BASE_PTR)

#define	ENET_IEEE_T_OCTETS_OK ENET_IEEE_T_OCTETS_OK_REG(ENET_BASE_PTR)

#define	ENET_RMON_R_PACKETS ENET_RMON_R_PACKETS_REG(ENET_BASE_PTR)

#define	ENET_RMON_R_BC_PKT ENET_RMON_R_BC_PKT_REG(ENET_BASE_PTR)

#define	ENET_RMON_R_MC_PKT ENET_RMON_R_MC_PKT_REG(ENET_BASE_PTR)

#define	ENET_RMON_R_CRC_ALIGN ENET_RMON_R_CRC_ALIGN_REG(ENET_BASE_PTR)

#define	ENET_RMON_R_UNDERSIZE ENET_RMON_R_UNDERSIZE_REG(ENET_BASE_PTR)

#define	ENET_RMON_R_OVERSIZE ENET_RMON_R_OVERSIZE_REG(ENET_BASE_PTR)

#define	ENET_RMON_R_FRAG ENET_RMON_R_FRAG_REG(ENET_BASE_PTR)

#define	ENET_RMON_R_JAB ENET_RMON_R_JAB_REG(ENET_BASE_PTR)

#define	ENET_RMON_R_RESVD_0 ENET_RMON_R_RESVD_0_REG(ENET_BASE_PTR)

#define	ENET_RMON_R_P64 ENET_RMON_R_P64_REG(ENET_BASE_PTR)

#define	ENET_RMON_R_P65TO127 ENET_RMON_R_P65TO127_REG(ENET_BASE_PTR)

#define	ENET_RMON_R_P128TO255 ENET_RMON_R_P128TO255_REG(ENET_BASE_PTR)

#define	ENET_RMON_R_P256TO511 ENET_RMON_R_P256TO511_REG(ENET_BASE_PTR)

#define	ENET_RMON_R_P512TO1023 ENET_RMON_R_P512TO1023_REG(ENET_BASE_PTR)

#define	ENET_RMON_R_P1024TO2047 ENET_RMON_R_P1024TO2047_REG(ENET_BASE_PTR)

#define	ENET_RMON_R_P_GTE2048 ENET_RMON_R_P_GTE2048_REG(ENET_BASE_PTR)

#define	ENET_RMON_R_OCTETS ENET_RMON_R_OCTETS_REG(ENET_BASE_PTR)

#define	ENET_IEEE_R_DROP ENET_IEEE_R_DROP_REG(ENET_BASE_PTR)

#define	ENET_IEEE_R_FRAME_OK ENET_IEEE_R_FRAME_OK_REG(ENET_BASE_PTR)

#define	ENET_IEEE_R_CRC ENET_IEEE_R_CRC_REG(ENET_BASE_PTR)

#define	ENET_IEEE_R_ALIGN ENET_IEEE_R_ALIGN_REG(ENET_BASE_PTR)

#define	ENET_IEEE_R_MACERR ENET_IEEE_R_MACERR_REG(ENET_BASE_PTR)

#define	ENET_IEEE_R_FDXFC ENET_IEEE_R_FDXFC_REG(ENET_BASE_PTR)

#define	ENET_IEEE_R_OCTETS_OK ENET_IEEE_R_OCTETS_OK_REG(ENET_BASE_PTR)

#define	ENET_ATCR ENET_ATCR_REG(ENET_BASE_PTR)

#define	ENET_ATVR ENET_ATVR_REG(ENET_BASE_PTR)

#define	ENET_ATOFF ENET_ATOFF_REG(ENET_BASE_PTR)

#define	ENET_ATPER ENET_ATPER_REG(ENET_BASE_PTR)

#define	ENET_ATCOR ENET_ATCOR_REG(ENET_BASE_PTR)

#define	ENET_ATINC ENET_ATINC_REG(ENET_BASE_PTR)

#define	ENET_ATSTMP ENET_ATSTMP_REG(ENET_BASE_PTR)

#define	ENET_TGSR ENET_TGSR_REG(ENET_BASE_PTR)

#define	ENET_TCSR0 ENET_TCSR_REG(ENET_BASE_PTR,0)

#define	ENET_TCCR0 ENET_TCCR_REG(ENET_BASE_PTR,0)

#define	ENET_TCSR1 ENET_TCSR_REG(ENET_BASE_PTR,1)

#define	ENET_TCCR1 ENET_TCCR_REG(ENET_BASE_PTR,1)

#define	ENET_TCSR2 ENET_TCSR_REG(ENET_BASE_PTR,2)

#define	ENET_TCCR2 ENET_TCCR_REG(ENET_BASE_PTR,2)

#define	ENET_TCSR3 ENET_TCSR_REG(ENET_BASE_PTR,3)

#define	ENET_TCCR3 ENET_TCCR_REG(ENET_BASE_PTR,3)

#define	ENET_TCSR(index) ENET_TCSR_REG(ENET_BASE_PTR,index)

#define	ENET_TCCR(index) ENET_TCCR_REG(ENET_BASE_PTR,index)

#define	ETB_RDP_REG(base) ((base)->RDP)

#define	ETB_STS_REG(base) ((base)->STS)

#define	ETB_RRD_REG(base) ((base)->RRD)

#define	ETB_RRP_REG(base) ((base)->RRP)

#define	ETB_RWP_REG(base) ((base)->RWP)

#define	ETB_TRG_REG(base) ((base)->TRG)

#define	ETB_CTL_REG(base) ((base)->CTL)

#define	ETB_RWD_REG(base) ((base)->RWD)

#define	ETB_FFSR_REG(base) ((base)->FFSR)

#define	ETB_FFCR_REG(base) ((base)->FFCR)

#define	ETB_ITMISCOP0_REG(base) ((base)->ITMISCOP0)

#define	ETB_ITTRFLINACK_REG(base) ((base)->ITTRFLINACK)

#define	ETB_ITTRFLIN_REG(base) ((base)->ITTRFLIN)

#define	ETB_ITATBDATA0_REG(base) ((base)->ITATBDATA0)

#define	ETB_ITATBCTR2_REG(base) ((base)->ITATBCTR2)

#define	ETB_ITATBCTR1_REG(base) ((base)->ITATBCTR1)

#define	ETB_ITATBCTR0_REG(base) ((base)->ITATBCTR0)

#define	ETB_ITCTRL_REG(base) ((base)->ITCTRL)

#define	ETB_CLAIMSET_REG(base) ((base)->CLAIMSET)

#define	ETB_CLAIMCLR_REG(base) ((base)->CLAIMCLR)

#define	ETB_LAR_REG(base) ((base)->LAR)

#define	ETB_LSR_REG(base) ((base)->LSR)

#define	ETB_AUTHSTATUS_REG(base) ((base)->AUTHSTATUS)

#define	ETB_DEVID_REG(base) ((base)->DEVID)

#define	ETB_DEVTYPE_REG(base) ((base)->DEVTYPE)

#define	ETB_PIDR4_REG(base) ((base)->PIDR4)

#define	ETB_PIDR5_REG(base) ((base)->PIDR5)

#define	ETB_PIDR6_REG(base) ((base)->PIDR6)

#define	ETB_PIDR7_REG(base) ((base)->PIDR7)

#define	ETB_PIDR0_REG(base) ((base)->PIDR0)

#define	ETB_PIDR1_REG(base) ((base)->PIDR1)

#define	ETB_PIDR2_REG(base) ((base)->PIDR2)

#define	ETB_PIDR3_REG(base) ((base)->PIDR3)

#define	ETB_CIDR0_REG(base) ((base)->CIDR0)

#define	ETB_CIDR1_REG(base) ((base)->CIDR1)

#define	ETB_CIDR2_REG(base) ((base)->CIDR2)

#define	ETB_CIDR3_REG(base) ((base)->CIDR3)

#define	ETB_BASE_PTR ((ETB_MemMapPtr)0xE0042000u)

#define	ETB_BASE_PTRS { ETB_BASE_PTR }

#define	ETB_RDP ETB_RDP_REG(ETB_BASE_PTR)

#define	ETB_STS ETB_STS_REG(ETB_BASE_PTR)

#define	ETB_RRD ETB_RRD_REG(ETB_BASE_PTR)

#define	ETB_RRP ETB_RRP_REG(ETB_BASE_PTR)

#define	ETB_RWP ETB_RWP_REG(ETB_BASE_PTR)

#define	ETB_TRG ETB_TRG_REG(ETB_BASE_PTR)

#define	ETB_CTL ETB_CTL_REG(ETB_BASE_PTR)

#define	ETB_RWD ETB_RWD_REG(ETB_BASE_PTR)

#define	ETB_FFSR ETB_FFSR_REG(ETB_BASE_PTR)

#define	ETB_FFCR ETB_FFCR_REG(ETB_BASE_PTR)

#define	ETB_ITMISCOP0 ETB_ITMISCOP0_REG(ETB_BASE_PTR)

#define	ETB_ITTRFLINACK ETB_ITTRFLINACK_REG(ETB_BASE_PTR)

#define	ETB_ITTRFLIN ETB_ITTRFLIN_REG(ETB_BASE_PTR)

#define	ETB_ITATBDATA0 ETB_ITATBDATA0_REG(ETB_BASE_PTR)

#define	ETB_ITATBCTR2 ETB_ITATBCTR2_REG(ETB_BASE_PTR)

#define	ETB_ITATBCTR1 ETB_ITATBCTR1_REG(ETB_BASE_PTR)

#define	ETB_ITATBCTR0 ETB_ITATBCTR0_REG(ETB_BASE_PTR)

#define	ETB_ITCTRL ETB_ITCTRL_REG(ETB_BASE_PTR)

#define	ETB_CLAIMSET ETB_CLAIMSET_REG(ETB_BASE_PTR)

#define	ETB_CLAIMCLR ETB_CLAIMCLR_REG(ETB_BASE_PTR)

#define	ETB_LAR ETB_LAR_REG(ETB_BASE_PTR)

#define	ETB_LSR ETB_LSR_REG(ETB_BASE_PTR)

#define	ETB_AUTHSTATUS ETB_AUTHSTATUS_REG(ETB_BASE_PTR)

#define	ETB_DEVID ETB_DEVID_REG(ETB_BASE_PTR)

#define	ETB_DEVTYPE ETB_DEVTYPE_REG(ETB_BASE_PTR)

#define	ETB_PIDR4 ETB_PIDR4_REG(ETB_BASE_PTR)

#define	ETB_PIDR5 ETB_PIDR5_REG(ETB_BASE_PTR)

#define	ETB_PIDR6 ETB_PIDR6_REG(ETB_BASE_PTR)

#define	ETB_PIDR7 ETB_PIDR7_REG(ETB_BASE_PTR)

#define	ETB_PIDR0 ETB_PIDR0_REG(ETB_BASE_PTR)

#define	ETB_PIDR1 ETB_PIDR1_REG(ETB_BASE_PTR)

#define	ETB_PIDR2 ETB_PIDR2_REG(ETB_BASE_PTR)

#define	ETB_PIDR3 ETB_PIDR3_REG(ETB_BASE_PTR)

#define	ETB_CIDR0 ETB_CIDR0_REG(ETB_BASE_PTR)

#define	ETB_CIDR1 ETB_CIDR1_REG(ETB_BASE_PTR)

#define	ETB_CIDR2 ETB_CIDR2_REG(ETB_BASE_PTR)

#define	ETB_CIDR3 ETB_CIDR3_REG(ETB_BASE_PTR)

#define	ETF_FCR_REG(base) ((base)->FCR)

#define	ETF_PCR_REG(base) ((base)->PCR)

#define	ETF_ITATBDATA0_REG(base) ((base)->ITATBDATA0)

#define	ETF_ITATBCTR2_REG(base) ((base)->ITATBCTR2)

#define	ETF_ITATBCTR1_REG(base) ((base)->ITATBCTR1)

#define	ETF_ITATBCTR0_REG(base) ((base)->ITATBCTR0)

#define	ETF_ITCTRL_REG(base) ((base)->ITCTRL)

#define	ETF_CLAIMSET_REG(base) ((base)->CLAIMSET)

#define	ETF_CLAIMCLR_REG(base) ((base)->CLAIMCLR)

#define	ETF_LAR_REG(base) ((base)->LAR)

#define	ETF_LSR_REG(base) ((base)->LSR)

#define	ETF_AUTHSTATUS_REG(base) ((base)->AUTHSTATUS)

#define	ETF_DEVID_REG(base) ((base)->DEVID)

#define	ETF_DEVTYPE_REG(base) ((base)->DEVTYPE)

#define	ETF_PIDR4_REG(base) ((base)->PIDR4)

#define	ETF_PIDR5_REG(base) ((base)->PIDR5)

#define	ETF_PIDR6_REG(base) ((base)->PIDR6)

#define	ETF_PIDR7_REG(base) ((base)->PIDR7)

#define	ETF_PIDR0_REG(base) ((base)->PIDR0)

#define	ETF_PIDR1_REG(base) ((base)->PIDR1)

#define	ETF_PIDR2_REG(base) ((base)->PIDR2)

#define	ETF_PIDR3_REG(base) ((base)->PIDR3)

#define	ETF_CIDR0_REG(base) ((base)->CIDR0)

#define	ETF_CIDR1_REG(base) ((base)->CIDR1)

#define	ETF_CIDR2_REG(base) ((base)->CIDR2)

#define	ETF_CIDR3_REG(base) ((base)->CIDR3)

#define	ETF_BASE_PTR ((ETF_MemMapPtr)0xE0043000u)

#define	ETF_BASE_PTRS { ETF_BASE_PTR }

#define	ETF_FCR ETF_FCR_REG(ETF_BASE_PTR)

#define	ETF_PCR ETF_PCR_REG(ETF_BASE_PTR)

#define	ETF_ITATBDATA0 ETF_ITATBDATA0_REG(ETF_BASE_PTR)

#define	ETF_ITATBCTR2 ETF_ITATBCTR2_REG(ETF_BASE_PTR)

#define	ETF_ITATBCTR1 ETF_ITATBCTR1_REG(ETF_BASE_PTR)

#define	ETF_ITATBCTR0 ETF_ITATBCTR0_REG(ETF_BASE_PTR)

#define	ETF_ITCTRL ETF_ITCTRL_REG(ETF_BASE_PTR)

#define	ETF_CLAIMSET ETF_CLAIMSET_REG(ETF_BASE_PTR)

#define	ETF_CLAIMCLR ETF_CLAIMCLR_REG(ETF_BASE_PTR)

#define	ETF_LAR ETF_LAR_REG(ETF_BASE_PTR)

#define	ETF_LSR ETF_LSR_REG(ETF_BASE_PTR)

#define	ETF_AUTHSTATUS ETF_AUTHSTATUS_REG(ETF_BASE_PTR)

#define	ETF_DEVID ETF_DEVID_REG(ETF_BASE_PTR)

#define	ETF_DEVTYPE ETF_DEVTYPE_REG(ETF_BASE_PTR)

#define	ETF_PIDR4 ETF_PIDR4_REG(ETF_BASE_PTR)

#define	ETF_PIDR5 ETF_PIDR5_REG(ETF_BASE_PTR)

#define	ETF_PIDR6 ETF_PIDR6_REG(ETF_BASE_PTR)

#define	ETF_PIDR7 ETF_PIDR7_REG(ETF_BASE_PTR)

#define	ETF_PIDR0 ETF_PIDR0_REG(ETF_BASE_PTR)

#define	ETF_PIDR1 ETF_PIDR1_REG(ETF_BASE_PTR)

#define	ETF_PIDR2 ETF_PIDR2_REG(ETF_BASE_PTR)

#define	ETF_PIDR3 ETF_PIDR3_REG(ETF_BASE_PTR)

#define	ETF_CIDR0 ETF_CIDR0_REG(ETF_BASE_PTR)

#define	ETF_CIDR1 ETF_CIDR1_REG(ETF_BASE_PTR)

#define	ETF_CIDR2 ETF_CIDR2_REG(ETF_BASE_PTR)

#define	ETF_CIDR3 ETF_CIDR3_REG(ETF_BASE_PTR)

#define	ETM_CR_REG(base) ((base)->CR)

#define	ETM_CCR_REG(base) ((base)->CCR)

#define	ETM_TRIGGER_REG(base) ((base)->TRIGGER)

#define	ETM_SR_REG(base) ((base)->SR)

#define	ETM_SCR_REG(base) ((base)->SCR)

#define	ETM_EEVR_REG(base) ((base)->EEVR)

#define	ETM_TECR1_REG(base) ((base)->TECR1)

#define	ETM_FFLR_REG(base) ((base)->FFLR)

#define	ETM_CNTRLDVR1_REG(base) ((base)->CNTRLDVR1)

#define	ETM_SYNCFR_REG(base) ((base)->SYNCFR)

#define	ETM_IDR_REG(base) ((base)->IDR)

#define	ETM_CCER_REG(base) ((base)->CCER)

#define	ETM_TESSEICR_REG(base) ((base)->TESSEICR)

#define	ETM_TSEVR_REG(base) ((base)->TSEVR)

#define	ETM_TRACEIDR_REG(base) ((base)->TRACEIDR)

#define	ETM_IDR2_REG(base) ((base)->IDR2)

#define	ETM_PDSR_REG(base) ((base)->PDSR)

#define	ETM_ITMISCIN_REG(base) ((base)->ITMISCIN)

#define	ETM_ITTRIGOUT_REG(base) ((base)->ITTRIGOUT)

#define	ETM_ITATBCTR2_REG(base) ((base)->ITATBCTR2)

#define	ETM_ITATBCTR0_REG(base) ((base)->ITATBCTR0)

#define	ETM_ITCTRL_REG(base) ((base)->ITCTRL)

#define	ETM_CLAIMSET_REG(base) ((base)->CLAIMSET)

#define	ETM_CLAIMCLR_REG(base) ((base)->CLAIMCLR)

#define	ETM_LAR_REG(base) ((base)->LAR)

#define	ETM_LSR_REG(base) ((base)->LSR)

#define	ETM_AUTHSTATUS_REG(base) ((base)->AUTHSTATUS)

#define	ETM_DEVTYPE_REG(base) ((base)->DEVTYPE)

#define	ETM_PIDR4_REG(base) ((base)->PIDR4)

#define	ETM_PIDR5_REG(base) ((base)->PIDR5)

#define	ETM_PIDR6_REG(base) ((base)->PIDR6)

#define	ETM_PIDR7_REG(base) ((base)->PIDR7)

#define	ETM_PIDR0_REG(base) ((base)->PIDR0)

#define	ETM_PIDR1_REG(base) ((base)->PIDR1)

#define	ETM_PIDR2_REG(base) ((base)->PIDR2)

#define	ETM_PIDR3_REG(base) ((base)->PIDR3)

#define	ETM_CIDR0_REG(base) ((base)->CIDR0)

#define	ETM_CIDR1_REG(base) ((base)->CIDR1)

#define	ETM_CIDR2_REG(base) ((base)->CIDR2)

#define	ETM_CIDR3_REG(base) ((base)->CIDR3)

#define	ETM_BASE_PTR ((ETM_MemMapPtr)0xE0041000u)

#define	ETM_BASE_PTRS { ETM_BASE_PTR }

#define	ETMCR ETM_CR_REG(ETM_BASE_PTR)

#define	ETMCCR ETM_CCR_REG(ETM_BASE_PTR)

#define	ETMTRIGGER ETM_TRIGGER_REG(ETM_BASE_PTR)

#define	ETMSR ETM_SR_REG(ETM_BASE_PTR)

#define	ETMSCR ETM_SCR_REG(ETM_BASE_PTR)

#define	ETMEEVR ETM_EEVR_REG(ETM_BASE_PTR)

#define	ETMTECR1 ETM_TECR1_REG(ETM_BASE_PTR)

#define	ETMFFLR ETM_FFLR_REG(ETM_BASE_PTR)

#define	ETMCNTRLDVR1 ETM_CNTRLDVR1_REG(ETM_BASE_PTR)

#define	ETMSYNCFR ETM_SYNCFR_REG(ETM_BASE_PTR)

#define	ETMIDR ETM_IDR_REG(ETM_BASE_PTR)

#define	ETMCCER ETM_CCER_REG(ETM_BASE_PTR)

#define	ETMTESSEICR ETM_TESSEICR_REG(ETM_BASE_PTR)

#define	ETMTSEVR ETM_TSEVR_REG(ETM_BASE_PTR)

#define	ETMTRACEIDR ETM_TRACEIDR_REG(ETM_BASE_PTR)

#define	ETMIDR2 ETM_IDR2_REG(ETM_BASE_PTR)

#define	ETMPDSR ETM_PDSR_REG(ETM_BASE_PTR)

#define	ETM_ITMISCIN ETM_ITMISCIN_REG(ETM_BASE_PTR)

#define	ETM_ITTRIGOUT ETM_ITTRIGOUT_REG(ETM_BASE_PTR)

#define	ETM_ITATBCTR2 ETM_ITATBCTR2_REG(ETM_BASE_PTR)

#define	ETM_ITATBCTR0 ETM_ITATBCTR0_REG(ETM_BASE_PTR)

#define	ETMITCTRL ETM_ITCTRL_REG(ETM_BASE_PTR)

#define	ETMCLAIMSET ETM_CLAIMSET_REG(ETM_BASE_PTR)

#define	ETMCLAIMCLR ETM_CLAIMCLR_REG(ETM_BASE_PTR)

#define	ETMLAR ETM_LAR_REG(ETM_BASE_PTR)

#define	ETMLSR ETM_LSR_REG(ETM_BASE_PTR)

#define	ETMAUTHSTATUS ETM_AUTHSTATUS_REG(ETM_BASE_PTR)

#define	ETMDEVTYPE ETM_DEVTYPE_REG(ETM_BASE_PTR)

#define	ETMPIDR4 ETM_PIDR4_REG(ETM_BASE_PTR)

#define	ETMPIDR5 ETM_PIDR5_REG(ETM_BASE_PTR)

#define	ETMPIDR6 ETM_PIDR6_REG(ETM_BASE_PTR)

#define	ETMPIDR7 ETM_PIDR7_REG(ETM_BASE_PTR)

#define	ETMPIDR0 ETM_PIDR0_REG(ETM_BASE_PTR)

#define	ETMPIDR1 ETM_PIDR1_REG(ETM_BASE_PTR)

#define	ETMPIDR2 ETM_PIDR2_REG(ETM_BASE_PTR)

#define	ETMPIDR3 ETM_PIDR3_REG(ETM_BASE_PTR)

#define	ETMCIDR0 ETM_CIDR0_REG(ETM_BASE_PTR)

#define	ETMCIDR1 ETM_CIDR1_REG(ETM_BASE_PTR)

#define	ETMCIDR2 ETM_CIDR2_REG(ETM_BASE_PTR)

#define	ETMCIDR3 ETM_CIDR3_REG(ETM_BASE_PTR)

#define	EWM_CTRL_REG(base) ((base)->CTRL)

#define	EWM_SERV_REG(base) ((base)->SERV)

#define	EWM_CMPL_REG(base) ((base)->CMPL)

#define	EWM_CMPH_REG(base) ((base)->CMPH)

#define	EWM_CTRL_EWMEN_MASK 0x1u

#define	EWM_CTRL_EWMEN_SHIFT 0

#define	EWM_CTRL_ASSIN_MASK 0x2u

#define	EWM_CTRL_ASSIN_SHIFT 1

#define	EWM_CTRL_INEN_MASK 0x4u

#define	EWM_CTRL_INEN_SHIFT 2

#define	EWM_CTRL_INTEN_MASK 0x8u

#define	EWM_CTRL_INTEN_SHIFT 3

#define	EWM_SERV_SERVICE_MASK 0xFFu

#define	EWM_SERV_SERVICE_SHIFT 0

#define	EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)

#define	EWM_CMPL_COMPAREL_MASK 0xFFu

#define	EWM_CMPL_COMPAREL_SHIFT 0

#define	EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)

#define	EWM_CMPH_COMPAREH_MASK 0xFFu

#define	EWM_CMPH_COMPAREH_SHIFT 0

#define	EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)

#define	EWM_BASE_PTR ((EWM_MemMapPtr)0x40061000u)

#define	EWM_BASE_PTRS { EWM_BASE_PTR }

#define	EWM_CTRL EWM_CTRL_REG(EWM_BASE_PTR)

#define	EWM_SERV EWM_SERV_REG(EWM_BASE_PTR)

#define	EWM_CMPL EWM_CMPL_REG(EWM_BASE_PTR)

#define	EWM_CMPH EWM_CMPH_REG(EWM_BASE_PTR)

#define	FB_CSAR_REG(base, index) ((base)->CS[index].CSAR)

#define	FB_CSMR_REG(base, index) ((base)->CS[index].CSMR)

#define	FB_CSCR_REG(base, index) ((base)->CS[index].CSCR)

#define	FB_CSPMCR_REG(base) ((base)->CSPMCR)

#define	FB_CSAR_BA_MASK 0xFFFF0000u

#define	FB_CSAR_BA_SHIFT 16

#define	FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)

#define	FB_CSMR_V_MASK 0x1u

#define	FB_CSMR_V_SHIFT 0

#define	FB_CSMR_WP_MASK 0x100u

#define	FB_CSMR_WP_SHIFT 8

#define	FB_CSMR_BAM_MASK 0xFFFF0000u

#define	FB_CSMR_BAM_SHIFT 16

#define	FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)

#define	FB_CSCR_BSTW_MASK 0x8u

#define	FB_CSCR_BSTW_SHIFT 3

#define	FB_CSCR_BSTR_MASK 0x10u

#define	FB_CSCR_BSTR_SHIFT 4

#define	FB_CSCR_BEM_MASK 0x20u

#define	FB_CSCR_BEM_SHIFT 5

#define	FB_CSCR_PS_MASK 0xC0u

#define	FB_CSCR_PS_SHIFT 6

#define	FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)

#define	FB_CSCR_AA_MASK 0x100u

#define	FB_CSCR_AA_SHIFT 8

#define	FB_CSCR_BLS_MASK 0x200u

#define	FB_CSCR_BLS_SHIFT 9

#define	FB_CSCR_WS_MASK 0xFC00u

#define	FB_CSCR_WS_SHIFT 10

#define	FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)

#define	FB_CSCR_WRAH_MASK 0x30000u

#define	FB_CSCR_WRAH_SHIFT 16

#define	FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)

#define	FB_CSCR_RDAH_MASK 0xC0000u

#define	FB_CSCR_RDAH_SHIFT 18

#define	FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)

#define	FB_CSCR_ASET_MASK 0x300000u

#define	FB_CSCR_ASET_SHIFT 20

#define	FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)

#define	FB_CSCR_EXTS_MASK 0x400000u

#define	FB_CSCR_EXTS_SHIFT 22

#define	FB_CSCR_SWSEN_MASK 0x800000u

#define	FB_CSCR_SWSEN_SHIFT 23

#define	FB_CSCR_SWS_MASK 0xFC000000u

#define	FB_CSCR_SWS_SHIFT 26

#define	FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)

#define	FB_CSPMCR_GROUP5_MASK 0xF000u

#define	FB_CSPMCR_GROUP5_SHIFT 12

#define	FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)

#define	FB_CSPMCR_GROUP4_MASK 0xF0000u

#define	FB_CSPMCR_GROUP4_SHIFT 16

#define	FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)

#define	FB_CSPMCR_GROUP3_MASK 0xF00000u

#define	FB_CSPMCR_GROUP3_SHIFT 20

#define	FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)

#define	FB_CSPMCR_GROUP2_MASK 0xF000000u

#define	FB_CSPMCR_GROUP2_SHIFT 24

#define	FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)

#define	FB_CSPMCR_GROUP1_MASK 0xF0000000u

#define	FB_CSPMCR_GROUP1_SHIFT 28

#define	FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)

#define	FB_BASE_PTR ((FB_MemMapPtr)0x4000C000u)

#define	FB_BASE_PTRS { FB_BASE_PTR }

#define	FB_CSAR0 FB_CSAR_REG(FB_BASE_PTR,0)

#define	FB_CSMR0 FB_CSMR_REG(FB_BASE_PTR,0)

#define	FB_CSCR0 FB_CSCR_REG(FB_BASE_PTR,0)

#define	FB_CSAR1 FB_CSAR_REG(FB_BASE_PTR,1)

#define	FB_CSMR1 FB_CSMR_REG(FB_BASE_PTR,1)

#define	FB_CSCR1 FB_CSCR_REG(FB_BASE_PTR,1)

#define	FB_CSAR2 FB_CSAR_REG(FB_BASE_PTR,2)

#define	FB_CSMR2 FB_CSMR_REG(FB_BASE_PTR,2)

#define	FB_CSCR2 FB_CSCR_REG(FB_BASE_PTR,2)

#define	FB_CSAR3 FB_CSAR_REG(FB_BASE_PTR,3)

#define	FB_CSMR3 FB_CSMR_REG(FB_BASE_PTR,3)

#define	FB_CSCR3 FB_CSCR_REG(FB_BASE_PTR,3)

#define	FB_CSAR4 FB_CSAR_REG(FB_BASE_PTR,4)

#define	FB_CSMR4 FB_CSMR_REG(FB_BASE_PTR,4)

#define	FB_CSCR4 FB_CSCR_REG(FB_BASE_PTR,4)

#define	FB_CSAR5 FB_CSAR_REG(FB_BASE_PTR,5)

#define	FB_CSMR5 FB_CSMR_REG(FB_BASE_PTR,5)

#define	FB_CSCR5 FB_CSCR_REG(FB_BASE_PTR,5)

#define	FB_CSPMCR FB_CSPMCR_REG(FB_BASE_PTR)

#define	FB_CSAR(index) FB_CSAR_REG(FB_BASE_PTR,index)

#define	FB_CSMR(index) FB_CSMR_REG(FB_BASE_PTR,index)

#define	FB_CSCR(index) FB_CSCR_REG(FB_BASE_PTR,index)

#define	FMC_PFAPR_REG(base) ((base)->PFAPR)

#define	FMC_PFB01CR_REG(base) ((base)->PFB01CR)

#define	FMC_PFB23CR_REG(base) ((base)->PFB23CR)

#define	FMC_TAGVD_REG(base, index, index2) ((base)->TAGVD[index][index2])

#define	FMC_DATA_UM_REG(base, index, index2) ((base)->SET[index][index2].DATA_UM)

#define	FMC_DATA_MU_REG(base, index, index2) ((base)->SET[index][index2].DATA_MU)

#define	FMC_DATA_ML_REG(base, index, index2) ((base)->SET[index][index2].DATA_ML)

#define	FMC_DATA_LM_REG(base, index, index2) ((base)->SET[index][index2].DATA_LM)

#define	FMC_PFAPR_M0AP_MASK 0x3u

#define	FMC_PFAPR_M0AP_SHIFT 0

#define	FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)

#define	FMC_PFAPR_M1AP_MASK 0xCu

#define	FMC_PFAPR_M1AP_SHIFT 2

#define	FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)

#define	FMC_PFAPR_M2AP_MASK 0x30u

#define	FMC_PFAPR_M2AP_SHIFT 4

#define	FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)

#define	FMC_PFAPR_M3AP_MASK 0xC0u

#define	FMC_PFAPR_M3AP_SHIFT 6

#define	FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)

#define	FMC_PFAPR_M4AP_MASK 0x300u

#define	FMC_PFAPR_M4AP_SHIFT 8

#define	FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)

#define	FMC_PFAPR_M5AP_MASK 0xC00u

#define	FMC_PFAPR_M5AP_SHIFT 10

#define	FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)

#define	FMC_PFAPR_M6AP_MASK 0x3000u

#define	FMC_PFAPR_M6AP_SHIFT 12

#define	FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)

#define	FMC_PFAPR_M7AP_MASK 0xC000u

#define	FMC_PFAPR_M7AP_SHIFT 14

#define	FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)

#define	FMC_PFAPR_M0PFD_MASK 0x10000u

#define	FMC_PFAPR_M0PFD_SHIFT 16

#define	FMC_PFAPR_M1PFD_MASK 0x20000u

#define	FMC_PFAPR_M1PFD_SHIFT 17

#define	FMC_PFAPR_M2PFD_MASK 0x40000u

#define	FMC_PFAPR_M2PFD_SHIFT 18

#define	FMC_PFAPR_M3PFD_MASK 0x80000u

#define	FMC_PFAPR_M3PFD_SHIFT 19

#define	FMC_PFAPR_M4PFD_MASK 0x100000u

#define	FMC_PFAPR_M4PFD_SHIFT 20

#define	FMC_PFAPR_M5PFD_MASK 0x200000u

#define	FMC_PFAPR_M5PFD_SHIFT 21

#define	FMC_PFAPR_M6PFD_MASK 0x400000u

#define	FMC_PFAPR_M6PFD_SHIFT 22

#define	FMC_PFAPR_M7PFD_MASK 0x800000u

#define	FMC_PFAPR_M7PFD_SHIFT 23

#define	FMC_PFB01CR_B01SEBE_MASK 0x1u

#define	FMC_PFB01CR_B01SEBE_SHIFT 0

#define	FMC_PFB01CR_B01IPE_MASK 0x2u

#define	FMC_PFB01CR_B01IPE_SHIFT 1

#define	FMC_PFB01CR_B01DPE_MASK 0x4u

#define	FMC_PFB01CR_B01DPE_SHIFT 2

#define	FMC_PFB01CR_B01ICE_MASK 0x8u

#define	FMC_PFB01CR_B01ICE_SHIFT 3

#define	FMC_PFB01CR_B01DCE_MASK 0x10u

#define	FMC_PFB01CR_B01DCE_SHIFT 4

#define	FMC_PFB01CR_CRC_MASK 0xE0u

#define	FMC_PFB01CR_CRC_SHIFT 5

#define	FMC_PFB01CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB01CR_CRC_SHIFT))&FMC_PFB01CR_CRC_MASK)

#define	FMC_PFB01CR_B01MW_MASK 0x60000u

#define	FMC_PFB01CR_B01MW_SHIFT 17

#define	FMC_PFB01CR_B01MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB01CR_B01MW_SHIFT))&FMC_PFB01CR_B01MW_MASK)

#define	FMC_PFB01CR_S_B_INV_MASK 0x80000u

#define	FMC_PFB01CR_S_B_INV_SHIFT 19

#define	FMC_PFB01CR_CINV_WAY_MASK 0xF00000u

#define	FMC_PFB01CR_CINV_WAY_SHIFT 20

#define	FMC_PFB01CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB01CR_CINV_WAY_SHIFT))&FMC_PFB01CR_CINV_WAY_MASK)

#define	FMC_PFB01CR_CLCK_WAY_MASK 0xF000000u

#define	FMC_PFB01CR_CLCK_WAY_SHIFT 24

#define	FMC_PFB01CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB01CR_CLCK_WAY_SHIFT))&FMC_PFB01CR_CLCK_WAY_MASK)

#define	FMC_PFB01CR_B01RWSC_MASK 0xF0000000u

#define	FMC_PFB01CR_B01RWSC_SHIFT 28

#define	FMC_PFB01CR_B01RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB01CR_B01RWSC_SHIFT))&FMC_PFB01CR_B01RWSC_MASK)

#define	FMC_PFB23CR_B23SEBE_MASK 0x1u

#define	FMC_PFB23CR_B23SEBE_SHIFT 0

#define	FMC_PFB23CR_B23IPE_MASK 0x2u

#define	FMC_PFB23CR_B23IPE_SHIFT 1

#define	FMC_PFB23CR_B23DPE_MASK 0x4u

#define	FMC_PFB23CR_B23DPE_SHIFT 2

#define	FMC_PFB23CR_B23ICE_MASK 0x8u

#define	FMC_PFB23CR_B23ICE_SHIFT 3

#define	FMC_PFB23CR_B23DCE_MASK 0x10u

#define	FMC_PFB23CR_B23DCE_SHIFT 4

#define	FMC_PFB23CR_B23MW_MASK 0x60000u

#define	FMC_PFB23CR_B23MW_SHIFT 17

#define	FMC_PFB23CR_B23MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB23CR_B23MW_SHIFT))&FMC_PFB23CR_B23MW_MASK)

#define	FMC_PFB23CR_B23RWSC_MASK 0xF0000000u

#define	FMC_PFB23CR_B23RWSC_SHIFT 28

#define	FMC_PFB23CR_B23RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB23CR_B23RWSC_SHIFT))&FMC_PFB23CR_B23RWSC_MASK)

#define	FMC_TAGVD_valid_MASK 0x1u

#define	FMC_TAGVD_valid_SHIFT 0

#define	FMC_TAGVD_tag_MASK 0xFFFC0u

#define	FMC_TAGVD_tag_SHIFT 6

#define	FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)

#define	FMC_DATA_UM_data_MASK 0xFFFFFFFFu

#define	FMC_DATA_UM_data_SHIFT 0

#define	FMC_DATA_UM_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_UM_data_SHIFT))&FMC_DATA_UM_data_MASK)

#define	FMC_DATA_MU_data_MASK 0xFFFFFFFFu

#define	FMC_DATA_MU_data_SHIFT 0

#define	FMC_DATA_MU_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_MU_data_SHIFT))&FMC_DATA_MU_data_MASK)

#define	FMC_DATA_ML_data_MASK 0xFFFFFFFFu

#define	FMC_DATA_ML_data_SHIFT 0

#define	FMC_DATA_ML_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_ML_data_SHIFT))&FMC_DATA_ML_data_MASK)

#define	FMC_DATA_LM_data_MASK 0xFFFFFFFFu

#define	FMC_DATA_LM_data_SHIFT 0

#define	FMC_DATA_LM_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_LM_data_SHIFT))&FMC_DATA_LM_data_MASK)

#define	FMC_BASE_PTR ((FMC_MemMapPtr)0x4001F000u)

#define	FMC_BASE_PTRS { FMC_BASE_PTR }

#define	FMC_PFAPR FMC_PFAPR_REG(FMC_BASE_PTR)

#define	FMC_PFB01CR FMC_PFB01CR_REG(FMC_BASE_PTR)

#define	FMC_PFB23CR FMC_PFB23CR_REG(FMC_BASE_PTR)

#define	FMC_TAGVDW0S0 FMC_TAGVD_REG(FMC_BASE_PTR,0,0)

#define	FMC_TAGVDW0S1 FMC_TAGVD_REG(FMC_BASE_PTR,0,1)

#define	FMC_TAGVDW0S2 FMC_TAGVD_REG(FMC_BASE_PTR,0,2)

#define	FMC_TAGVDW0S3 FMC_TAGVD_REG(FMC_BASE_PTR,0,3)

#define	FMC_TAGVDW1S0 FMC_TAGVD_REG(FMC_BASE_PTR,1,0)

#define	FMC_TAGVDW1S1 FMC_TAGVD_REG(FMC_BASE_PTR,1,1)

#define	FMC_TAGVDW1S2 FMC_TAGVD_REG(FMC_BASE_PTR,1,2)

#define	FMC_TAGVDW1S3 FMC_TAGVD_REG(FMC_BASE_PTR,1,3)

#define	FMC_TAGVDW2S0 FMC_TAGVD_REG(FMC_BASE_PTR,2,0)

#define	FMC_TAGVDW2S1 FMC_TAGVD_REG(FMC_BASE_PTR,2,1)

#define	FMC_TAGVDW2S2 FMC_TAGVD_REG(FMC_BASE_PTR,2,2)

#define	FMC_TAGVDW2S3 FMC_TAGVD_REG(FMC_BASE_PTR,2,3)

#define	FMC_TAGVDW3S0 FMC_TAGVD_REG(FMC_BASE_PTR,3,0)

#define	FMC_TAGVDW3S1 FMC_TAGVD_REG(FMC_BASE_PTR,3,1)

#define	FMC_TAGVDW3S2 FMC_TAGVD_REG(FMC_BASE_PTR,3,2)

#define	FMC_TAGVDW3S3 FMC_TAGVD_REG(FMC_BASE_PTR,3,3)

#define	FMC_DATAW0S0UM FMC_DATA_UM_REG(FMC_BASE_PTR,0,0)

#define	FMC_DATAW0S0MU FMC_DATA_MU_REG(FMC_BASE_PTR,0,0)

#define	FMC_DATAW0S0ML FMC_DATA_ML_REG(FMC_BASE_PTR,0,0)

#define	FMC_DATAW0S0LM FMC_DATA_LM_REG(FMC_BASE_PTR,0,0)

#define	FMC_DATAW0S1UM FMC_DATA_UM_REG(FMC_BASE_PTR,0,1)

#define	FMC_DATAW0S1MU FMC_DATA_MU_REG(FMC_BASE_PTR,0,1)

#define	FMC_DATAW0S1ML FMC_DATA_ML_REG(FMC_BASE_PTR,0,1)

#define	FMC_DATAW0S1LM FMC_DATA_LM_REG(FMC_BASE_PTR,0,1)

#define	FMC_DATAW0S2UM FMC_DATA_UM_REG(FMC_BASE_PTR,0,2)

#define	FMC_DATAW0S2MU FMC_DATA_MU_REG(FMC_BASE_PTR,0,2)

#define	FMC_DATAW0S2ML FMC_DATA_ML_REG(FMC_BASE_PTR,0,2)

#define	FMC_DATAW0S2LM FMC_DATA_LM_REG(FMC_BASE_PTR,0,2)

#define	FMC_DATAW0S3UM FMC_DATA_UM_REG(FMC_BASE_PTR,0,3)

#define	FMC_DATAW0S3MU FMC_DATA_MU_REG(FMC_BASE_PTR,0,3)

#define	FMC_DATAW0S3ML FMC_DATA_ML_REG(FMC_BASE_PTR,0,3)

#define	FMC_DATAW0S3LM FMC_DATA_LM_REG(FMC_BASE_PTR,0,3)

#define	FMC_DATAW1S0UM FMC_DATA_UM_REG(FMC_BASE_PTR,1,0)

#define	FMC_DATAW1S0MU FMC_DATA_MU_REG(FMC_BASE_PTR,1,0)

#define	FMC_DATAW1S0ML FMC_DATA_ML_REG(FMC_BASE_PTR,1,0)

#define	FMC_DATAW1S0LM FMC_DATA_LM_REG(FMC_BASE_PTR,1,0)

#define	FMC_DATAW1S1UM FMC_DATA_UM_REG(FMC_BASE_PTR,1,1)

#define	FMC_DATAW1S1MU FMC_DATA_MU_REG(FMC_BASE_PTR,1,1)

#define	FMC_DATAW1S1ML FMC_DATA_ML_REG(FMC_BASE_PTR,1,1)

#define	FMC_DATAW1S1LM FMC_DATA_LM_REG(FMC_BASE_PTR,1,1)

#define	FMC_DATAW1S2UM FMC_DATA_UM_REG(FMC_BASE_PTR,1,2)

#define	FMC_DATAW1S2MU FMC_DATA_MU_REG(FMC_BASE_PTR,1,2)

#define	FMC_DATAW1S2ML FMC_DATA_ML_REG(FMC_BASE_PTR,1,2)

#define	FMC_DATAW1S2LM FMC_DATA_LM_REG(FMC_BASE_PTR,1,2)

#define	FMC_DATAW1S3UM FMC_DATA_UM_REG(FMC_BASE_PTR,1,3)

#define	FMC_DATAW1S3MU FMC_DATA_MU_REG(FMC_BASE_PTR,1,3)

#define	FMC_DATAW1S3ML FMC_DATA_ML_REG(FMC_BASE_PTR,1,3)

#define	FMC_DATAW1S3LM FMC_DATA_LM_REG(FMC_BASE_PTR,1,3)

#define	FMC_DATAW2S0UM FMC_DATA_UM_REG(FMC_BASE_PTR,2,0)

#define	FMC_DATAW2S0MU FMC_DATA_MU_REG(FMC_BASE_PTR,2,0)

#define	FMC_DATAW2S0ML FMC_DATA_ML_REG(FMC_BASE_PTR,2,0)

#define	FMC_DATAW2S0LM FMC_DATA_LM_REG(FMC_BASE_PTR,2,0)

#define	FMC_DATAW2S1UM FMC_DATA_UM_REG(FMC_BASE_PTR,2,1)

#define	FMC_DATAW2S1MU FMC_DATA_MU_REG(FMC_BASE_PTR,2,1)

#define	FMC_DATAW2S1ML FMC_DATA_ML_REG(FMC_BASE_PTR,2,1)

#define	FMC_DATAW2S1LM FMC_DATA_LM_REG(FMC_BASE_PTR,2,1)

#define	FMC_DATAW2S2UM FMC_DATA_UM_REG(FMC_BASE_PTR,2,2)

#define	FMC_DATAW2S2MU FMC_DATA_MU_REG(FMC_BASE_PTR,2,2)

#define	FMC_DATAW2S2ML FMC_DATA_ML_REG(FMC_BASE_PTR,2,2)

#define	FMC_DATAW2S2LM FMC_DATA_LM_REG(FMC_BASE_PTR,2,2)

#define	FMC_DATAW2S3UM FMC_DATA_UM_REG(FMC_BASE_PTR,2,3)

#define	FMC_DATAW2S3MU FMC_DATA_MU_REG(FMC_BASE_PTR,2,3)

#define	FMC_DATAW2S3ML FMC_DATA_ML_REG(FMC_BASE_PTR,2,3)

#define	FMC_DATAW2S3LM FMC_DATA_LM_REG(FMC_BASE_PTR,2,3)

#define	FMC_DATAW3S0UM FMC_DATA_UM_REG(FMC_BASE_PTR,3,0)

#define	FMC_DATAW3S0MU FMC_DATA_MU_REG(FMC_BASE_PTR,3,0)

#define	FMC_DATAW3S0ML FMC_DATA_ML_REG(FMC_BASE_PTR,3,0)

#define	FMC_DATAW3S0LM FMC_DATA_LM_REG(FMC_BASE_PTR,3,0)

#define	FMC_DATAW3S1UM FMC_DATA_UM_REG(FMC_BASE_PTR,3,1)

#define	FMC_DATAW3S1MU FMC_DATA_MU_REG(FMC_BASE_PTR,3,1)

#define	FMC_DATAW3S1ML FMC_DATA_ML_REG(FMC_BASE_PTR,3,1)

#define	FMC_DATAW3S1LM FMC_DATA_LM_REG(FMC_BASE_PTR,3,1)

#define	FMC_DATAW3S2UM FMC_DATA_UM_REG(FMC_BASE_PTR,3,2)

#define	FMC_DATAW3S2MU FMC_DATA_MU_REG(FMC_BASE_PTR,3,2)

#define	FMC_DATAW3S2ML FMC_DATA_ML_REG(FMC_BASE_PTR,3,2)

#define	FMC_DATAW3S2LM FMC_DATA_LM_REG(FMC_BASE_PTR,3,2)

#define	FMC_DATAW3S3UM FMC_DATA_UM_REG(FMC_BASE_PTR,3,3)

#define	FMC_DATAW3S3MU FMC_DATA_MU_REG(FMC_BASE_PTR,3,3)

#define	FMC_DATAW3S3ML FMC_DATA_ML_REG(FMC_BASE_PTR,3,3)

#define	FMC_DATAW3S3LM FMC_DATA_LM_REG(FMC_BASE_PTR,3,3)

#define	FMC_TAGVD(index, index2) FMC_TAGVD_REG(FMC_BASE_PTR,index,index2)

#define	FMC_DATA_UM(index, index2) FMC_DATA_UM_REG(FMC_BASE_PTR,index,index2)

#define	FMC_DATA_MU(index, index2) FMC_DATA_MU_REG(FMC_BASE_PTR,index,index2)

#define	FMC_DATA_ML(index, index2) FMC_DATA_ML_REG(FMC_BASE_PTR,index,index2)

#define	FMC_DATA_LM(index, index2) FMC_DATA_LM_REG(FMC_BASE_PTR,index,index2)

#define	FPB_CTRL_REG(base) ((base)->CTRL)

#define	FPB_REMAP_REG(base) ((base)->REMAP)

#define	FPB_COMP_REG(base, index) ((base)->COMP[index])

#define	FPB_PID4_REG(base) ((base)->PID4)

#define	FPB_PID5_REG(base) ((base)->PID5)

#define	FPB_PID6_REG(base) ((base)->PID6)

#define	FPB_PID7_REG(base) ((base)->PID7)

#define	FPB_PID0_REG(base) ((base)->PID0)

#define	FPB_PID1_REG(base) ((base)->PID1)

#define	FPB_PID2_REG(base) ((base)->PID2)

#define	FPB_PID3_REG(base) ((base)->PID3)

#define	FPB_CID0_REG(base) ((base)->CID0)

#define	FPB_CID1_REG(base) ((base)->CID1)

#define	FPB_CID2_REG(base) ((base)->CID2)

#define	FPB_CID3_REG(base) ((base)->CID3)

#define	FPB_BASE_PTR ((FPB_MemMapPtr)0xE0002000u)

#define	FPB_BASE_PTRS { FPB_BASE_PTR }

#define	FP_CTRL FPB_CTRL_REG(FPB_BASE_PTR)

#define	FP_REMAP FPB_REMAP_REG(FPB_BASE_PTR)

#define	FP_COMP0 FPB_COMP_REG(FPB_BASE_PTR,0)

#define	FP_COMP1 FPB_COMP_REG(FPB_BASE_PTR,1)

#define	FP_COMP2 FPB_COMP_REG(FPB_BASE_PTR,2)

#define	FP_COMP3 FPB_COMP_REG(FPB_BASE_PTR,3)

#define	FP_COMP4 FPB_COMP_REG(FPB_BASE_PTR,4)

#define	FP_COMP5 FPB_COMP_REG(FPB_BASE_PTR,5)

#define	FP_COMP6 FPB_COMP_REG(FPB_BASE_PTR,6)

#define	FP_COMP7 FPB_COMP_REG(FPB_BASE_PTR,7)

#define	FP_PID4 FPB_PID4_REG(FPB_BASE_PTR)

#define	FP_PID5 FPB_PID5_REG(FPB_BASE_PTR)

#define	FP_PID6 FPB_PID6_REG(FPB_BASE_PTR)

#define	FP_PID7 FPB_PID7_REG(FPB_BASE_PTR)

#define	FP_PID0 FPB_PID0_REG(FPB_BASE_PTR)

#define	FP_PID1 FPB_PID1_REG(FPB_BASE_PTR)

#define	FP_PID2 FPB_PID2_REG(FPB_BASE_PTR)

#define	FP_PID3 FPB_PID3_REG(FPB_BASE_PTR)

#define	FP_CID0 FPB_CID0_REG(FPB_BASE_PTR)

#define	FP_CID1 FPB_CID1_REG(FPB_BASE_PTR)

#define	FP_CID2 FPB_CID2_REG(FPB_BASE_PTR)

#define	FP_CID3 FPB_CID3_REG(FPB_BASE_PTR)

#define	FPB_COMP(index) FPB_COMP_REG(FPB_BASE_PTR,index)

#define	FTFE_FSTAT_REG(base) ((base)->FSTAT)

#define	FTFE_FCNFG_REG(base) ((base)->FCNFG)

#define	FTFE_FSEC_REG(base) ((base)->FSEC)

#define	FTFE_FOPT_REG(base) ((base)->FOPT)

#define	FTFE_FCCOB3_REG(base) ((base)->FCCOB3)

#define	FTFE_FCCOB2_REG(base) ((base)->FCCOB2)

#define	FTFE_FCCOB1_REG(base) ((base)->FCCOB1)

#define	FTFE_FCCOB0_REG(base) ((base)->FCCOB0)

#define	FTFE_FCCOB7_REG(base) ((base)->FCCOB7)

#define	FTFE_FCCOB6_REG(base) ((base)->FCCOB6)

#define	FTFE_FCCOB5_REG(base) ((base)->FCCOB5)

#define	FTFE_FCCOB4_REG(base) ((base)->FCCOB4)

#define	FTFE_FCCOBB_REG(base) ((base)->FCCOBB)

#define	FTFE_FCCOBA_REG(base) ((base)->FCCOBA)

#define	FTFE_FCCOB9_REG(base) ((base)->FCCOB9)

#define	FTFE_FCCOB8_REG(base) ((base)->FCCOB8)

#define	FTFE_FPROT3_REG(base) ((base)->FPROT3)

#define	FTFE_FPROT2_REG(base) ((base)->FPROT2)

#define	FTFE_FPROT1_REG(base) ((base)->FPROT1)

#define	FTFE_FPROT0_REG(base) ((base)->FPROT0)

#define	FTFE_FEPROT_REG(base) ((base)->FEPROT)

#define	FTFE_FDPROT_REG(base) ((base)->FDPROT)

#define	FTFE_FSTAT_MGSTAT0_MASK 0x1u

#define	FTFE_FSTAT_MGSTAT0_SHIFT 0

#define	FTFE_FSTAT_FPVIOL_MASK 0x10u

#define	FTFE_FSTAT_FPVIOL_SHIFT 4

#define	FTFE_FSTAT_ACCERR_MASK 0x20u

#define	FTFE_FSTAT_ACCERR_SHIFT 5

#define	FTFE_FSTAT_RDCOLERR_MASK 0x40u

#define	FTFE_FSTAT_RDCOLERR_SHIFT 6

#define	FTFE_FSTAT_CCIF_MASK 0x80u

#define	FTFE_FSTAT_CCIF_SHIFT 7

#define	FTFE_FCNFG_EEERDY_MASK 0x1u

#define	FTFE_FCNFG_EEERDY_SHIFT 0

#define	FTFE_FCNFG_RAMRDY_MASK 0x2u

#define	FTFE_FCNFG_RAMRDY_SHIFT 1

#define	FTFE_FCNFG_PFLSH_MASK 0x4u

#define	FTFE_FCNFG_PFLSH_SHIFT 2

#define	FTFE_FCNFG_SWAP_MASK 0x8u

#define	FTFE_FCNFG_SWAP_SHIFT 3

#define	FTFE_FCNFG_ERSSUSP_MASK 0x10u

#define	FTFE_FCNFG_ERSSUSP_SHIFT 4

#define	FTFE_FCNFG_ERSAREQ_MASK 0x20u

#define	FTFE_FCNFG_ERSAREQ_SHIFT 5

#define	FTFE_FCNFG_RDCOLLIE_MASK 0x40u

#define	FTFE_FCNFG_RDCOLLIE_SHIFT 6

#define	FTFE_FCNFG_CCIE_MASK 0x80u

#define	FTFE_FCNFG_CCIE_SHIFT 7

#define	FTFE_FSEC_SEC_MASK 0x3u

#define	FTFE_FSEC_SEC_SHIFT 0

#define	FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)

#define	FTFE_FSEC_FSLACC_MASK 0xCu

#define	FTFE_FSEC_FSLACC_SHIFT 2

#define	FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)

#define	FTFE_FSEC_MEEN_MASK 0x30u

#define	FTFE_FSEC_MEEN_SHIFT 4

#define	FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)

#define	FTFE_FSEC_KEYEN_MASK 0xC0u

#define	FTFE_FSEC_KEYEN_SHIFT 6

#define	FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)

#define	FTFE_FOPT_OPT_MASK 0xFFu

#define	FTFE_FOPT_OPT_SHIFT 0

#define	FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)

#define	FTFE_FCCOB3_CCOBn_MASK 0xFFu

#define	FTFE_FCCOB3_CCOBn_SHIFT 0

#define	FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)

#define	FTFE_FCCOB2_CCOBn_MASK 0xFFu

#define	FTFE_FCCOB2_CCOBn_SHIFT 0

#define	FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)

#define	FTFE_FCCOB1_CCOBn_MASK 0xFFu

#define	FTFE_FCCOB1_CCOBn_SHIFT 0

#define	FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)

#define	FTFE_FCCOB0_CCOBn_MASK 0xFFu

#define	FTFE_FCCOB0_CCOBn_SHIFT 0

#define	FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)

#define	FTFE_FCCOB7_CCOBn_MASK 0xFFu

#define	FTFE_FCCOB7_CCOBn_SHIFT 0

#define	FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)

#define	FTFE_FCCOB6_CCOBn_MASK 0xFFu

#define	FTFE_FCCOB6_CCOBn_SHIFT 0

#define	FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)

#define	FTFE_FCCOB5_CCOBn_MASK 0xFFu

#define	FTFE_FCCOB5_CCOBn_SHIFT 0

#define	FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)

#define	FTFE_FCCOB4_CCOBn_MASK 0xFFu

#define	FTFE_FCCOB4_CCOBn_SHIFT 0

#define	FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)

#define	FTFE_FCCOBB_CCOBn_MASK 0xFFu

#define	FTFE_FCCOBB_CCOBn_SHIFT 0

#define	FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)

#define	FTFE_FCCOBA_CCOBn_MASK 0xFFu

#define	FTFE_FCCOBA_CCOBn_SHIFT 0

#define	FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)

#define	FTFE_FCCOB9_CCOBn_MASK 0xFFu

#define	FTFE_FCCOB9_CCOBn_SHIFT 0

#define	FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)

#define	FTFE_FCCOB8_CCOBn_MASK 0xFFu

#define	FTFE_FCCOB8_CCOBn_SHIFT 0

#define	FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)

#define	FTFE_FPROT3_PROT_MASK 0xFFu

#define	FTFE_FPROT3_PROT_SHIFT 0

#define	FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)

#define	FTFE_FPROT2_PROT_MASK 0xFFu

#define	FTFE_FPROT2_PROT_SHIFT 0

#define	FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)

#define	FTFE_FPROT1_PROT_MASK 0xFFu

#define	FTFE_FPROT1_PROT_SHIFT 0

#define	FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)

#define	FTFE_FPROT0_PROT_MASK 0xFFu

#define	FTFE_FPROT0_PROT_SHIFT 0

#define	FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)

#define	FTFE_FEPROT_EPROT_MASK 0xFFu

#define	FTFE_FEPROT_EPROT_SHIFT 0

#define	FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)

#define	FTFE_FDPROT_DPROT_MASK 0xFFu

#define	FTFE_FDPROT_DPROT_SHIFT 0

#define	FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)

#define	FTFE_BASE_PTR ((FTFE_MemMapPtr)0x40020000u)

#define	FTFE_BASE_PTRS { FTFE_BASE_PTR }

#define	FTFE_FSTAT FTFE_FSTAT_REG(FTFE_BASE_PTR)

#define	FTFE_FCNFG FTFE_FCNFG_REG(FTFE_BASE_PTR)

#define	FTFE_FSEC FTFE_FSEC_REG(FTFE_BASE_PTR)

#define	FTFE_FOPT FTFE_FOPT_REG(FTFE_BASE_PTR)

#define	FTFE_FCCOB3 FTFE_FCCOB3_REG(FTFE_BASE_PTR)

#define	FTFE_FCCOB2 FTFE_FCCOB2_REG(FTFE_BASE_PTR)

#define	FTFE_FCCOB1 FTFE_FCCOB1_REG(FTFE_BASE_PTR)

#define	FTFE_FCCOB0 FTFE_FCCOB0_REG(FTFE_BASE_PTR)

#define	FTFE_FCCOB7 FTFE_FCCOB7_REG(FTFE_BASE_PTR)

#define	FTFE_FCCOB6 FTFE_FCCOB6_REG(FTFE_BASE_PTR)

#define	FTFE_FCCOB5 FTFE_FCCOB5_REG(FTFE_BASE_PTR)

#define	FTFE_FCCOB4 FTFE_FCCOB4_REG(FTFE_BASE_PTR)

#define	FTFE_FCCOBB FTFE_FCCOBB_REG(FTFE_BASE_PTR)

#define	FTFE_FCCOBA FTFE_FCCOBA_REG(FTFE_BASE_PTR)

#define	FTFE_FCCOB9 FTFE_FCCOB9_REG(FTFE_BASE_PTR)

#define	FTFE_FCCOB8 FTFE_FCCOB8_REG(FTFE_BASE_PTR)

#define	FTFE_FPROT3 FTFE_FPROT3_REG(FTFE_BASE_PTR)

#define	FTFE_FPROT2 FTFE_FPROT2_REG(FTFE_BASE_PTR)

#define	FTFE_FPROT1 FTFE_FPROT1_REG(FTFE_BASE_PTR)

#define	FTFE_FPROT0 FTFE_FPROT0_REG(FTFE_BASE_PTR)

#define	FTFE_FEPROT FTFE_FEPROT_REG(FTFE_BASE_PTR)

#define	FTFE_FDPROT FTFE_FDPROT_REG(FTFE_BASE_PTR)

#define	FTM_SC_REG(base) ((base)->SC)

#define	FTM_CNT_REG(base) ((base)->CNT)

#define	FTM_MOD_REG(base) ((base)->MOD)

#define	FTM_CnSC_REG(base, index) ((base)->CONTROLS[index].CnSC)

#define	FTM_CnV_REG(base, index) ((base)->CONTROLS[index].CnV)

#define	FTM_CNTIN_REG(base) ((base)->CNTIN)

#define	FTM_STATUS_REG(base) ((base)->STATUS)

#define	FTM_MODE_REG(base) ((base)->MODE)

#define	FTM_SYNC_REG(base) ((base)->SYNC)

#define	FTM_OUTINIT_REG(base) ((base)->OUTINIT)

#define	FTM_OUTMASK_REG(base) ((base)->OUTMASK)

#define	FTM_COMBINE_REG(base) ((base)->COMBINE)

#define	FTM_DEADTIME_REG(base) ((base)->DEADTIME)

#define	FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)

#define	FTM_POL_REG(base) ((base)->POL)

#define	FTM_FMS_REG(base) ((base)->FMS)

#define	FTM_FILTER_REG(base) ((base)->FILTER)

#define	FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)

#define	FTM_QDCTRL_REG(base) ((base)->QDCTRL)

#define	FTM_CONF_REG(base) ((base)->CONF)

#define	FTM_FLTPOL_REG(base) ((base)->FLTPOL)

#define	FTM_SYNCONF_REG(base) ((base)->SYNCONF)

#define	FTM_INVCTRL_REG(base) ((base)->INVCTRL)

#define	FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)

#define	FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)

#define	FTM_SC_PS_MASK 0x7u

#define	FTM_SC_PS_SHIFT 0

#define	FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)

#define	FTM_SC_CLKS_MASK 0x18u

#define	FTM_SC_CLKS_SHIFT 3

#define	FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)

#define	FTM_SC_CPWMS_MASK 0x20u

#define	FTM_SC_CPWMS_SHIFT 5

#define	FTM_SC_TOIE_MASK 0x40u

#define	FTM_SC_TOIE_SHIFT 6

#define	FTM_SC_TOF_MASK 0x80u

#define	FTM_SC_TOF_SHIFT 7

#define	FTM_CNT_COUNT_MASK 0xFFFFu

#define	FTM_CNT_COUNT_SHIFT 0

#define	FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)

#define	FTM_MOD_MOD_MASK 0xFFFFu

#define	FTM_MOD_MOD_SHIFT 0

#define	FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)

#define	FTM_CnSC_DMA_MASK 0x1u

#define	FTM_CnSC_DMA_SHIFT 0

#define	FTM_CnSC_ELSA_MASK 0x4u

#define	FTM_CnSC_ELSA_SHIFT 2

#define	FTM_CnSC_ELSB_MASK 0x8u

#define	FTM_CnSC_ELSB_SHIFT 3

#define	FTM_CnSC_MSA_MASK 0x10u

#define	FTM_CnSC_MSA_SHIFT 4

#define	FTM_CnSC_MSB_MASK 0x20u

#define	FTM_CnSC_MSB_SHIFT 5

#define	FTM_CnSC_CHIE_MASK 0x40u

#define	FTM_CnSC_CHIE_SHIFT 6

#define	FTM_CnSC_CHF_MASK 0x80u

#define	FTM_CnSC_CHF_SHIFT 7

#define	FTM_CnV_VAL_MASK 0xFFFFu

#define	FTM_CnV_VAL_SHIFT 0

#define	FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)

#define	FTM_CNTIN_INIT_MASK 0xFFFFu

#define	FTM_CNTIN_INIT_SHIFT 0

#define	FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)

#define	FTM_STATUS_CH0F_MASK 0x1u

#define	FTM_STATUS_CH0F_SHIFT 0

#define	FTM_STATUS_CH1F_MASK 0x2u

#define	FTM_STATUS_CH1F_SHIFT 1

#define	FTM_STATUS_CH2F_MASK 0x4u

#define	FTM_STATUS_CH2F_SHIFT 2

#define	FTM_STATUS_CH3F_MASK 0x8u

#define	FTM_STATUS_CH3F_SHIFT 3

#define	FTM_STATUS_CH4F_MASK 0x10u

#define	FTM_STATUS_CH4F_SHIFT 4

#define	FTM_STATUS_CH5F_MASK 0x20u

#define	FTM_STATUS_CH5F_SHIFT 5

#define	FTM_STATUS_CH6F_MASK 0x40u

#define	FTM_STATUS_CH6F_SHIFT 6

#define	FTM_STATUS_CH7F_MASK 0x80u

#define	FTM_STATUS_CH7F_SHIFT 7

#define	FTM_MODE_FTMEN_MASK 0x1u

#define	FTM_MODE_FTMEN_SHIFT 0

#define	FTM_MODE_INIT_MASK 0x2u

#define	FTM_MODE_INIT_SHIFT 1

#define	FTM_MODE_WPDIS_MASK 0x4u

#define	FTM_MODE_WPDIS_SHIFT 2

#define	FTM_MODE_PWMSYNC_MASK 0x8u

#define	FTM_MODE_PWMSYNC_SHIFT 3

#define	FTM_MODE_CAPTEST_MASK 0x10u

#define	FTM_MODE_CAPTEST_SHIFT 4

#define	FTM_MODE_FAULTM_MASK 0x60u

#define	FTM_MODE_FAULTM_SHIFT 5

#define	FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)

#define	FTM_MODE_FAULTIE_MASK 0x80u

#define	FTM_MODE_FAULTIE_SHIFT 7

#define	FTM_SYNC_CNTMIN_MASK 0x1u

#define	FTM_SYNC_CNTMIN_SHIFT 0

#define	FTM_SYNC_CNTMAX_MASK 0x2u

#define	FTM_SYNC_CNTMAX_SHIFT 1

#define	FTM_SYNC_REINIT_MASK 0x4u

#define	FTM_SYNC_REINIT_SHIFT 2

#define	FTM_SYNC_SYNCHOM_MASK 0x8u

#define	FTM_SYNC_SYNCHOM_SHIFT 3

#define	FTM_SYNC_TRIG0_MASK 0x10u

#define	FTM_SYNC_TRIG0_SHIFT 4

#define	FTM_SYNC_TRIG1_MASK 0x20u

#define	FTM_SYNC_TRIG1_SHIFT 5

#define	FTM_SYNC_TRIG2_MASK 0x40u

#define	FTM_SYNC_TRIG2_SHIFT 6

#define	FTM_SYNC_SWSYNC_MASK 0x80u

#define	FTM_SYNC_SWSYNC_SHIFT 7

#define	FTM_OUTINIT_CH0OI_MASK 0x1u

#define	FTM_OUTINIT_CH0OI_SHIFT 0

#define	FTM_OUTINIT_CH1OI_MASK 0x2u

#define	FTM_OUTINIT_CH1OI_SHIFT 1

#define	FTM_OUTINIT_CH2OI_MASK 0x4u

#define	FTM_OUTINIT_CH2OI_SHIFT 2

#define	FTM_OUTINIT_CH3OI_MASK 0x8u

#define	FTM_OUTINIT_CH3OI_SHIFT 3

#define	FTM_OUTINIT_CH4OI_MASK 0x10u

#define	FTM_OUTINIT_CH4OI_SHIFT 4

#define	FTM_OUTINIT_CH5OI_MASK 0x20u

#define	FTM_OUTINIT_CH5OI_SHIFT 5

#define	FTM_OUTINIT_CH6OI_MASK 0x40u

#define	FTM_OUTINIT_CH6OI_SHIFT 6

#define	FTM_OUTINIT_CH7OI_MASK 0x80u

#define	FTM_OUTINIT_CH7OI_SHIFT 7

#define	FTM_OUTMASK_CH0OM_MASK 0x1u

#define	FTM_OUTMASK_CH0OM_SHIFT 0

#define	FTM_OUTMASK_CH1OM_MASK 0x2u

#define	FTM_OUTMASK_CH1OM_SHIFT 1

#define	FTM_OUTMASK_CH2OM_MASK 0x4u

#define	FTM_OUTMASK_CH2OM_SHIFT 2

#define	FTM_OUTMASK_CH3OM_MASK 0x8u

#define	FTM_OUTMASK_CH3OM_SHIFT 3

#define	FTM_OUTMASK_CH4OM_MASK 0x10u

#define	FTM_OUTMASK_CH4OM_SHIFT 4

#define	FTM_OUTMASK_CH5OM_MASK 0x20u

#define	FTM_OUTMASK_CH5OM_SHIFT 5

#define	FTM_OUTMASK_CH6OM_MASK 0x40u

#define	FTM_OUTMASK_CH6OM_SHIFT 6

#define	FTM_OUTMASK_CH7OM_MASK 0x80u

#define	FTM_OUTMASK_CH7OM_SHIFT 7

#define	FTM_COMBINE_COMBINE0_MASK 0x1u

#define	FTM_COMBINE_COMBINE0_SHIFT 0

#define	FTM_COMBINE_COMP0_MASK 0x2u

#define	FTM_COMBINE_COMP0_SHIFT 1

#define	FTM_COMBINE_DECAPEN0_MASK 0x4u

#define	FTM_COMBINE_DECAPEN0_SHIFT 2

#define	FTM_COMBINE_DECAP0_MASK 0x8u

#define	FTM_COMBINE_DECAP0_SHIFT 3

#define	FTM_COMBINE_DTEN0_MASK 0x10u

#define	FTM_COMBINE_DTEN0_SHIFT 4

#define	FTM_COMBINE_SYNCEN0_MASK 0x20u

#define	FTM_COMBINE_SYNCEN0_SHIFT 5

#define	FTM_COMBINE_FAULTEN0_MASK 0x40u

#define	FTM_COMBINE_FAULTEN0_SHIFT 6

#define	FTM_COMBINE_COMBINE1_MASK 0x100u

#define	FTM_COMBINE_COMBINE1_SHIFT 8

#define	FTM_COMBINE_COMP1_MASK 0x200u

#define	FTM_COMBINE_COMP1_SHIFT 9

#define	FTM_COMBINE_DECAPEN1_MASK 0x400u

#define	FTM_COMBINE_DECAPEN1_SHIFT 10

#define	FTM_COMBINE_DECAP1_MASK 0x800u

#define	FTM_COMBINE_DECAP1_SHIFT 11

#define	FTM_COMBINE_DTEN1_MASK 0x1000u

#define	FTM_COMBINE_DTEN1_SHIFT 12

#define	FTM_COMBINE_SYNCEN1_MASK 0x2000u

#define	FTM_COMBINE_SYNCEN1_SHIFT 13

#define	FTM_COMBINE_FAULTEN1_MASK 0x4000u

#define	FTM_COMBINE_FAULTEN1_SHIFT 14

#define	FTM_COMBINE_COMBINE2_MASK 0x10000u

#define	FTM_COMBINE_COMBINE2_SHIFT 16

#define	FTM_COMBINE_COMP2_MASK 0x20000u

#define	FTM_COMBINE_COMP2_SHIFT 17

#define	FTM_COMBINE_DECAPEN2_MASK 0x40000u

#define	FTM_COMBINE_DECAPEN2_SHIFT 18

#define	FTM_COMBINE_DECAP2_MASK 0x80000u

#define	FTM_COMBINE_DECAP2_SHIFT 19

#define	FTM_COMBINE_DTEN2_MASK 0x100000u

#define	FTM_COMBINE_DTEN2_SHIFT 20

#define	FTM_COMBINE_SYNCEN2_MASK 0x200000u

#define	FTM_COMBINE_SYNCEN2_SHIFT 21

#define	FTM_COMBINE_FAULTEN2_MASK 0x400000u

#define	FTM_COMBINE_FAULTEN2_SHIFT 22

#define	FTM_COMBINE_COMBINE3_MASK 0x1000000u

#define	FTM_COMBINE_COMBINE3_SHIFT 24

#define	FTM_COMBINE_COMP3_MASK 0x2000000u

#define	FTM_COMBINE_COMP3_SHIFT 25

#define	FTM_COMBINE_DECAPEN3_MASK 0x4000000u

#define	FTM_COMBINE_DECAPEN3_SHIFT 26

#define	FTM_COMBINE_DECAP3_MASK 0x8000000u

#define	FTM_COMBINE_DECAP3_SHIFT 27

#define	FTM_COMBINE_DTEN3_MASK 0x10000000u

#define	FTM_COMBINE_DTEN3_SHIFT 28

#define	FTM_COMBINE_SYNCEN3_MASK 0x20000000u

#define	FTM_COMBINE_SYNCEN3_SHIFT 29

#define	FTM_COMBINE_FAULTEN3_MASK 0x40000000u

#define	FTM_COMBINE_FAULTEN3_SHIFT 30

#define	FTM_DEADTIME_DTVAL_MASK 0x3Fu

#define	FTM_DEADTIME_DTVAL_SHIFT 0

#define	FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)

#define	FTM_DEADTIME_DTPS_MASK 0xC0u

#define	FTM_DEADTIME_DTPS_SHIFT 6

#define	FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)

#define	FTM_EXTTRIG_CH2TRIG_MASK 0x1u

#define	FTM_EXTTRIG_CH2TRIG_SHIFT 0

#define	FTM_EXTTRIG_CH3TRIG_MASK 0x2u

#define	FTM_EXTTRIG_CH3TRIG_SHIFT 1

#define	FTM_EXTTRIG_CH4TRIG_MASK 0x4u

#define	FTM_EXTTRIG_CH4TRIG_SHIFT 2

#define	FTM_EXTTRIG_CH5TRIG_MASK 0x8u

#define	FTM_EXTTRIG_CH5TRIG_SHIFT 3

#define	FTM_EXTTRIG_CH0TRIG_MASK 0x10u

#define	FTM_EXTTRIG_CH0TRIG_SHIFT 4

#define	FTM_EXTTRIG_CH1TRIG_MASK 0x20u

#define	FTM_EXTTRIG_CH1TRIG_SHIFT 5

#define	FTM_EXTTRIG_INITTRIGEN_MASK 0x40u

#define	FTM_EXTTRIG_INITTRIGEN_SHIFT 6

#define	FTM_EXTTRIG_TRIGF_MASK 0x80u

#define	FTM_EXTTRIG_TRIGF_SHIFT 7

#define	FTM_POL_POL0_MASK 0x1u

#define	FTM_POL_POL0_SHIFT 0

#define	FTM_POL_POL1_MASK 0x2u

#define	FTM_POL_POL1_SHIFT 1

#define	FTM_POL_POL2_MASK 0x4u

#define	FTM_POL_POL2_SHIFT 2

#define	FTM_POL_POL3_MASK 0x8u

#define	FTM_POL_POL3_SHIFT 3

#define	FTM_POL_POL4_MASK 0x10u

#define	FTM_POL_POL4_SHIFT 4

#define	FTM_POL_POL5_MASK 0x20u

#define	FTM_POL_POL5_SHIFT 5

#define	FTM_POL_POL6_MASK 0x40u

#define	FTM_POL_POL6_SHIFT 6

#define	FTM_POL_POL7_MASK 0x80u

#define	FTM_POL_POL7_SHIFT 7

#define	FTM_FMS_FAULTF0_MASK 0x1u

#define	FTM_FMS_FAULTF0_SHIFT 0

#define	FTM_FMS_FAULTF1_MASK 0x2u

#define	FTM_FMS_FAULTF1_SHIFT 1

#define	FTM_FMS_FAULTF2_MASK 0x4u

#define	FTM_FMS_FAULTF2_SHIFT 2

#define	FTM_FMS_FAULTF3_MASK 0x8u

#define	FTM_FMS_FAULTF3_SHIFT 3

#define	FTM_FMS_FAULTIN_MASK 0x20u

#define	FTM_FMS_FAULTIN_SHIFT 5

#define	FTM_FMS_WPEN_MASK 0x40u

#define	FTM_FMS_WPEN_SHIFT 6

#define	FTM_FMS_FAULTF_MASK 0x80u

#define	FTM_FMS_FAULTF_SHIFT 7

#define	FTM_FILTER_CH0FVAL_MASK 0xFu

#define	FTM_FILTER_CH0FVAL_SHIFT 0

#define	FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)

#define	FTM_FILTER_CH1FVAL_MASK 0xF0u

#define	FTM_FILTER_CH1FVAL_SHIFT 4

#define	FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)

#define	FTM_FILTER_CH2FVAL_MASK 0xF00u

#define	FTM_FILTER_CH2FVAL_SHIFT 8

#define	FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)

#define	FTM_FILTER_CH3FVAL_MASK 0xF000u

#define	FTM_FILTER_CH3FVAL_SHIFT 12

#define	FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)

#define	FTM_FLTCTRL_FAULT0EN_MASK 0x1u

#define	FTM_FLTCTRL_FAULT0EN_SHIFT 0

#define	FTM_FLTCTRL_FAULT1EN_MASK 0x2u

#define	FTM_FLTCTRL_FAULT1EN_SHIFT 1

#define	FTM_FLTCTRL_FAULT2EN_MASK 0x4u

#define	FTM_FLTCTRL_FAULT2EN_SHIFT 2

#define	FTM_FLTCTRL_FAULT3EN_MASK 0x8u

#define	FTM_FLTCTRL_FAULT3EN_SHIFT 3

#define	FTM_FLTCTRL_FFLTR0EN_MASK 0x10u

#define	FTM_FLTCTRL_FFLTR0EN_SHIFT 4

#define	FTM_FLTCTRL_FFLTR1EN_MASK 0x20u

#define	FTM_FLTCTRL_FFLTR1EN_SHIFT 5

#define	FTM_FLTCTRL_FFLTR2EN_MASK 0x40u

#define	FTM_FLTCTRL_FFLTR2EN_SHIFT 6

#define	FTM_FLTCTRL_FFLTR3EN_MASK 0x80u

#define	FTM_FLTCTRL_FFLTR3EN_SHIFT 7

#define	FTM_FLTCTRL_FFVAL_MASK 0xF00u

#define	FTM_FLTCTRL_FFVAL_SHIFT 8

#define	FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)

#define	FTM_QDCTRL_QUADEN_MASK 0x1u

#define	FTM_QDCTRL_QUADEN_SHIFT 0

#define	FTM_QDCTRL_TOFDIR_MASK 0x2u

#define	FTM_QDCTRL_TOFDIR_SHIFT 1

#define	FTM_QDCTRL_QUADIR_MASK 0x4u

#define	FTM_QDCTRL_QUADIR_SHIFT 2

#define	FTM_QDCTRL_QUADMODE_MASK 0x8u

#define	FTM_QDCTRL_QUADMODE_SHIFT 3

#define	FTM_QDCTRL_PHBPOL_MASK 0x10u

#define	FTM_QDCTRL_PHBPOL_SHIFT 4

#define	FTM_QDCTRL_PHAPOL_MASK 0x20u

#define	FTM_QDCTRL_PHAPOL_SHIFT 5

#define	FTM_QDCTRL_PHBFLTREN_MASK 0x40u

#define	FTM_QDCTRL_PHBFLTREN_SHIFT 6

#define	FTM_QDCTRL_PHAFLTREN_MASK 0x80u

#define	FTM_QDCTRL_PHAFLTREN_SHIFT 7

#define	FTM_CONF_NUMTOF_MASK 0x1Fu

#define	FTM_CONF_NUMTOF_SHIFT 0

#define	FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)

#define	FTM_CONF_BDMMODE_MASK 0xC0u

#define	FTM_CONF_BDMMODE_SHIFT 6

#define	FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)

#define	FTM_CONF_GTBEEN_MASK 0x200u

#define	FTM_CONF_GTBEEN_SHIFT 9

#define	FTM_CONF_GTBEOUT_MASK 0x400u

#define	FTM_CONF_GTBEOUT_SHIFT 10

#define	FTM_FLTPOL_FLT0POL_MASK 0x1u

#define	FTM_FLTPOL_FLT0POL_SHIFT 0

#define	FTM_FLTPOL_FLT1POL_MASK 0x2u

#define	FTM_FLTPOL_FLT1POL_SHIFT 1

#define	FTM_FLTPOL_FLT2POL_MASK 0x4u

#define	FTM_FLTPOL_FLT2POL_SHIFT 2

#define	FTM_FLTPOL_FLT3POL_MASK 0x8u

#define	FTM_FLTPOL_FLT3POL_SHIFT 3

#define	FTM_SYNCONF_HWTRIGMODE_MASK 0x1u

#define	FTM_SYNCONF_HWTRIGMODE_SHIFT 0

#define	FTM_SYNCONF_CNTINC_MASK 0x4u

#define	FTM_SYNCONF_CNTINC_SHIFT 2

#define	FTM_SYNCONF_INVC_MASK 0x10u

#define	FTM_SYNCONF_INVC_SHIFT 4

#define	FTM_SYNCONF_SWOC_MASK 0x20u

#define	FTM_SYNCONF_SWOC_SHIFT 5

#define	FTM_SYNCONF_SYNCMODE_MASK 0x80u

#define	FTM_SYNCONF_SYNCMODE_SHIFT 7

#define	FTM_SYNCONF_SWRSTCNT_MASK 0x100u

#define	FTM_SYNCONF_SWRSTCNT_SHIFT 8

#define	FTM_SYNCONF_SWWRBUF_MASK 0x200u

#define	FTM_SYNCONF_SWWRBUF_SHIFT 9

#define	FTM_SYNCONF_SWOM_MASK 0x400u

#define	FTM_SYNCONF_SWOM_SHIFT 10

#define	FTM_SYNCONF_SWINVC_MASK 0x800u

#define	FTM_SYNCONF_SWINVC_SHIFT 11

#define	FTM_SYNCONF_SWSOC_MASK 0x1000u

#define	FTM_SYNCONF_SWSOC_SHIFT 12

#define	FTM_SYNCONF_HWRSTCNT_MASK 0x10000u

#define	FTM_SYNCONF_HWRSTCNT_SHIFT 16

#define	FTM_SYNCONF_HWWRBUF_MASK 0x20000u

#define	FTM_SYNCONF_HWWRBUF_SHIFT 17

#define	FTM_SYNCONF_HWOM_MASK 0x40000u

#define	FTM_SYNCONF_HWOM_SHIFT 18

#define	FTM_SYNCONF_HWINVC_MASK 0x80000u

#define	FTM_SYNCONF_HWINVC_SHIFT 19

#define	FTM_SYNCONF_HWSOC_MASK 0x100000u

#define	FTM_SYNCONF_HWSOC_SHIFT 20

#define	FTM_INVCTRL_INV0EN_MASK 0x1u

#define	FTM_INVCTRL_INV0EN_SHIFT 0

#define	FTM_INVCTRL_INV1EN_MASK 0x2u

#define	FTM_INVCTRL_INV1EN_SHIFT 1

#define	FTM_INVCTRL_INV2EN_MASK 0x4u

#define	FTM_INVCTRL_INV2EN_SHIFT 2

#define	FTM_INVCTRL_INV3EN_MASK 0x8u

#define	FTM_INVCTRL_INV3EN_SHIFT 3

#define	FTM_SWOCTRL_CH0OC_MASK 0x1u

#define	FTM_SWOCTRL_CH0OC_SHIFT 0

#define	FTM_SWOCTRL_CH1OC_MASK 0x2u

#define	FTM_SWOCTRL_CH1OC_SHIFT 1

#define	FTM_SWOCTRL_CH2OC_MASK 0x4u

#define	FTM_SWOCTRL_CH2OC_SHIFT 2

#define	FTM_SWOCTRL_CH3OC_MASK 0x8u

#define	FTM_SWOCTRL_CH3OC_SHIFT 3

#define	FTM_SWOCTRL_CH4OC_MASK 0x10u

#define	FTM_SWOCTRL_CH4OC_SHIFT 4

#define	FTM_SWOCTRL_CH5OC_MASK 0x20u

#define	FTM_SWOCTRL_CH5OC_SHIFT 5

#define	FTM_SWOCTRL_CH6OC_MASK 0x40u

#define	FTM_SWOCTRL_CH6OC_SHIFT 6

#define	FTM_SWOCTRL_CH7OC_MASK 0x80u

#define	FTM_SWOCTRL_CH7OC_SHIFT 7

#define	FTM_SWOCTRL_CH0OCV_MASK 0x100u

#define	FTM_SWOCTRL_CH0OCV_SHIFT 8

#define	FTM_SWOCTRL_CH1OCV_MASK 0x200u

#define	FTM_SWOCTRL_CH1OCV_SHIFT 9

#define	FTM_SWOCTRL_CH2OCV_MASK 0x400u

#define	FTM_SWOCTRL_CH2OCV_SHIFT 10

#define	FTM_SWOCTRL_CH3OCV_MASK 0x800u

#define	FTM_SWOCTRL_CH3OCV_SHIFT 11

#define	FTM_SWOCTRL_CH4OCV_MASK 0x1000u

#define	FTM_SWOCTRL_CH4OCV_SHIFT 12

#define	FTM_SWOCTRL_CH5OCV_MASK 0x2000u

#define	FTM_SWOCTRL_CH5OCV_SHIFT 13

#define	FTM_SWOCTRL_CH6OCV_MASK 0x4000u

#define	FTM_SWOCTRL_CH6OCV_SHIFT 14

#define	FTM_SWOCTRL_CH7OCV_MASK 0x8000u

#define	FTM_SWOCTRL_CH7OCV_SHIFT 15

#define	FTM_PWMLOAD_CH0SEL_MASK 0x1u

#define	FTM_PWMLOAD_CH0SEL_SHIFT 0

#define	FTM_PWMLOAD_CH1SEL_MASK 0x2u

#define	FTM_PWMLOAD_CH1SEL_SHIFT 1

#define	FTM_PWMLOAD_CH2SEL_MASK 0x4u

#define	FTM_PWMLOAD_CH2SEL_SHIFT 2

#define	FTM_PWMLOAD_CH3SEL_MASK 0x8u

#define	FTM_PWMLOAD_CH3SEL_SHIFT 3

#define	FTM_PWMLOAD_CH4SEL_MASK 0x10u

#define	FTM_PWMLOAD_CH4SEL_SHIFT 4

#define	FTM_PWMLOAD_CH5SEL_MASK 0x20u

#define	FTM_PWMLOAD_CH5SEL_SHIFT 5

#define	FTM_PWMLOAD_CH6SEL_MASK 0x40u

#define	FTM_PWMLOAD_CH6SEL_SHIFT 6

#define	FTM_PWMLOAD_CH7SEL_MASK 0x80u

#define	FTM_PWMLOAD_CH7SEL_SHIFT 7

#define	FTM_PWMLOAD_LDOK_MASK 0x200u

#define	FTM_PWMLOAD_LDOK_SHIFT 9

#define	FTM0_BASE_PTR ((FTM_MemMapPtr)0x40038000u)

#define	FTM1_BASE_PTR ((FTM_MemMapPtr)0x40039000u)

#define	FTM2_BASE_PTR ((FTM_MemMapPtr)0x400B8000u)

#define	FTM3_BASE_PTR ((FTM_MemMapPtr)0x400B9000u)

#define	FTM_BASE_PTRS { FTM0_BASE_PTR, FTM1_BASE_PTR, FTM2_BASE_PTR, FTM3_BASE_PTR }

#define	FTM0_SC FTM_SC_REG(FTM0_BASE_PTR)

#define	FTM0_CNT FTM_CNT_REG(FTM0_BASE_PTR)

#define	FTM0_MOD FTM_MOD_REG(FTM0_BASE_PTR)

#define	FTM0_C0SC FTM_CnSC_REG(FTM0_BASE_PTR,0)

#define	FTM0_C0V FTM_CnV_REG(FTM0_BASE_PTR,0)

#define	FTM0_C1SC FTM_CnSC_REG(FTM0_BASE_PTR,1)

#define	FTM0_C1V FTM_CnV_REG(FTM0_BASE_PTR,1)

#define	FTM0_C2SC FTM_CnSC_REG(FTM0_BASE_PTR,2)

#define	FTM0_C2V FTM_CnV_REG(FTM0_BASE_PTR,2)

#define	FTM0_C3SC FTM_CnSC_REG(FTM0_BASE_PTR,3)

#define	FTM0_C3V FTM_CnV_REG(FTM0_BASE_PTR,3)

#define	FTM0_C4SC FTM_CnSC_REG(FTM0_BASE_PTR,4)

#define	FTM0_C4V FTM_CnV_REG(FTM0_BASE_PTR,4)

#define	FTM0_C5SC FTM_CnSC_REG(FTM0_BASE_PTR,5)

#define	FTM0_C5V FTM_CnV_REG(FTM0_BASE_PTR,5)

#define	FTM0_C6SC FTM_CnSC_REG(FTM0_BASE_PTR,6)

#define	FTM0_C6V FTM_CnV_REG(FTM0_BASE_PTR,6)

#define	FTM0_C7SC FTM_CnSC_REG(FTM0_BASE_PTR,7)

#define	FTM0_C7V FTM_CnV_REG(FTM0_BASE_PTR,7)

#define	FTM0_CNTIN FTM_CNTIN_REG(FTM0_BASE_PTR)

#define	FTM0_STATUS FTM_STATUS_REG(FTM0_BASE_PTR)

#define	FTM0_MODE FTM_MODE_REG(FTM0_BASE_PTR)

#define	FTM0_SYNC FTM_SYNC_REG(FTM0_BASE_PTR)

#define	FTM0_OUTINIT FTM_OUTINIT_REG(FTM0_BASE_PTR)

#define	FTM0_OUTMASK FTM_OUTMASK_REG(FTM0_BASE_PTR)

#define	FTM0_COMBINE FTM_COMBINE_REG(FTM0_BASE_PTR)

#define	FTM0_DEADTIME FTM_DEADTIME_REG(FTM0_BASE_PTR)

#define	FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0_BASE_PTR)

#define	FTM0_POL FTM_POL_REG(FTM0_BASE_PTR)

#define	FTM0_FMS FTM_FMS_REG(FTM0_BASE_PTR)

#define	FTM0_FILTER FTM_FILTER_REG(FTM0_BASE_PTR)

#define	FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0_BASE_PTR)

#define	FTM0_QDCTRL FTM_QDCTRL_REG(FTM0_BASE_PTR)

#define	FTM0_CONF FTM_CONF_REG(FTM0_BASE_PTR)

#define	FTM0_FLTPOL FTM_FLTPOL_REG(FTM0_BASE_PTR)

#define	FTM0_SYNCONF FTM_SYNCONF_REG(FTM0_BASE_PTR)

#define	FTM0_INVCTRL FTM_INVCTRL_REG(FTM0_BASE_PTR)

#define	FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0_BASE_PTR)

#define	FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0_BASE_PTR)

#define	FTM1_SC FTM_SC_REG(FTM1_BASE_PTR)

#define	FTM1_CNT FTM_CNT_REG(FTM1_BASE_PTR)

#define	FTM1_MOD FTM_MOD_REG(FTM1_BASE_PTR)

#define	FTM1_C0SC FTM_CnSC_REG(FTM1_BASE_PTR,0)

#define	FTM1_C0V FTM_CnV_REG(FTM1_BASE_PTR,0)

#define	FTM1_C1SC FTM_CnSC_REG(FTM1_BASE_PTR,1)

#define	FTM1_C1V FTM_CnV_REG(FTM1_BASE_PTR,1)

#define	FTM1_CNTIN FTM_CNTIN_REG(FTM1_BASE_PTR)

#define	FTM1_STATUS FTM_STATUS_REG(FTM1_BASE_PTR)

#define	FTM1_MODE FTM_MODE_REG(FTM1_BASE_PTR)

#define	FTM1_SYNC FTM_SYNC_REG(FTM1_BASE_PTR)

#define	FTM1_OUTINIT FTM_OUTINIT_REG(FTM1_BASE_PTR)

#define	FTM1_OUTMASK FTM_OUTMASK_REG(FTM1_BASE_PTR)

#define	FTM1_COMBINE FTM_COMBINE_REG(FTM1_BASE_PTR)

#define	FTM1_DEADTIME FTM_DEADTIME_REG(FTM1_BASE_PTR)

#define	FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1_BASE_PTR)

#define	FTM1_POL FTM_POL_REG(FTM1_BASE_PTR)

#define	FTM1_FMS FTM_FMS_REG(FTM1_BASE_PTR)

#define	FTM1_FILTER FTM_FILTER_REG(FTM1_BASE_PTR)

#define	FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1_BASE_PTR)

#define	FTM1_QDCTRL FTM_QDCTRL_REG(FTM1_BASE_PTR)

#define	FTM1_CONF FTM_CONF_REG(FTM1_BASE_PTR)

#define	FTM1_FLTPOL FTM_FLTPOL_REG(FTM1_BASE_PTR)

#define	FTM1_SYNCONF FTM_SYNCONF_REG(FTM1_BASE_PTR)

#define	FTM1_INVCTRL FTM_INVCTRL_REG(FTM1_BASE_PTR)

#define	FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1_BASE_PTR)

#define	FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1_BASE_PTR)

#define	FTM2_SC FTM_SC_REG(FTM2_BASE_PTR)

#define	FTM2_CNT FTM_CNT_REG(FTM2_BASE_PTR)

#define	FTM2_MOD FTM_MOD_REG(FTM2_BASE_PTR)

#define	FTM2_C0SC FTM_CnSC_REG(FTM2_BASE_PTR,0)

#define	FTM2_C0V FTM_CnV_REG(FTM2_BASE_PTR,0)

#define	FTM2_C1SC FTM_CnSC_REG(FTM2_BASE_PTR,1)

#define	FTM2_C1V FTM_CnV_REG(FTM2_BASE_PTR,1)

#define	FTM2_CNTIN FTM_CNTIN_REG(FTM2_BASE_PTR)

#define	FTM2_STATUS FTM_STATUS_REG(FTM2_BASE_PTR)

#define	FTM2_MODE FTM_MODE_REG(FTM2_BASE_PTR)

#define	FTM2_SYNC FTM_SYNC_REG(FTM2_BASE_PTR)

#define	FTM2_OUTINIT FTM_OUTINIT_REG(FTM2_BASE_PTR)

#define	FTM2_OUTMASK FTM_OUTMASK_REG(FTM2_BASE_PTR)

#define	FTM2_COMBINE FTM_COMBINE_REG(FTM2_BASE_PTR)

#define	FTM2_DEADTIME FTM_DEADTIME_REG(FTM2_BASE_PTR)

#define	FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2_BASE_PTR)

#define	FTM2_POL FTM_POL_REG(FTM2_BASE_PTR)

#define	FTM2_FMS FTM_FMS_REG(FTM2_BASE_PTR)

#define	FTM2_FILTER FTM_FILTER_REG(FTM2_BASE_PTR)

#define	FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2_BASE_PTR)

#define	FTM2_QDCTRL FTM_QDCTRL_REG(FTM2_BASE_PTR)

#define	FTM2_CONF FTM_CONF_REG(FTM2_BASE_PTR)

#define	FTM2_FLTPOL FTM_FLTPOL_REG(FTM2_BASE_PTR)

#define	FTM2_SYNCONF FTM_SYNCONF_REG(FTM2_BASE_PTR)

#define	FTM2_INVCTRL FTM_INVCTRL_REG(FTM2_BASE_PTR)

#define	FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2_BASE_PTR)

#define	FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2_BASE_PTR)

#define	FTM3_SC FTM_SC_REG(FTM3_BASE_PTR)

#define	FTM3_CNT FTM_CNT_REG(FTM3_BASE_PTR)

#define	FTM3_MOD FTM_MOD_REG(FTM3_BASE_PTR)

#define	FTM3_C0SC FTM_CnSC_REG(FTM3_BASE_PTR,0)

#define	FTM3_C0V FTM_CnV_REG(FTM3_BASE_PTR,0)

#define	FTM3_C1SC FTM_CnSC_REG(FTM3_BASE_PTR,1)

#define	FTM3_C1V FTM_CnV_REG(FTM3_BASE_PTR,1)

#define	FTM3_C2SC FTM_CnSC_REG(FTM3_BASE_PTR,2)

#define	FTM3_C2V FTM_CnV_REG(FTM3_BASE_PTR,2)

#define	FTM3_C3SC FTM_CnSC_REG(FTM3_BASE_PTR,3)

#define	FTM3_C3V FTM_CnV_REG(FTM3_BASE_PTR,3)

#define	FTM3_C4SC FTM_CnSC_REG(FTM3_BASE_PTR,4)

#define	FTM3_C4V FTM_CnV_REG(FTM3_BASE_PTR,4)

#define	FTM3_C5SC FTM_CnSC_REG(FTM3_BASE_PTR,5)

#define	FTM3_C5V FTM_CnV_REG(FTM3_BASE_PTR,5)

#define	FTM3_C6SC FTM_CnSC_REG(FTM3_BASE_PTR,6)

#define	FTM3_C6V FTM_CnV_REG(FTM3_BASE_PTR,6)

#define	FTM3_C7SC FTM_CnSC_REG(FTM3_BASE_PTR,7)

#define	FTM3_C7V FTM_CnV_REG(FTM3_BASE_PTR,7)

#define	FTM3_CNTIN FTM_CNTIN_REG(FTM3_BASE_PTR)

#define	FTM3_STATUS FTM_STATUS_REG(FTM3_BASE_PTR)

#define	FTM3_MODE FTM_MODE_REG(FTM3_BASE_PTR)

#define	FTM3_SYNC FTM_SYNC_REG(FTM3_BASE_PTR)

#define	FTM3_OUTINIT FTM_OUTINIT_REG(FTM3_BASE_PTR)

#define	FTM3_OUTMASK FTM_OUTMASK_REG(FTM3_BASE_PTR)

#define	FTM3_COMBINE FTM_COMBINE_REG(FTM3_BASE_PTR)

#define	FTM3_DEADTIME FTM_DEADTIME_REG(FTM3_BASE_PTR)

#define	FTM3_EXTTRIG FTM_EXTTRIG_REG(FTM3_BASE_PTR)

#define	FTM3_POL FTM_POL_REG(FTM3_BASE_PTR)

#define	FTM3_FMS FTM_FMS_REG(FTM3_BASE_PTR)

#define	FTM3_FILTER FTM_FILTER_REG(FTM3_BASE_PTR)

#define	FTM3_FLTCTRL FTM_FLTCTRL_REG(FTM3_BASE_PTR)

#define	FTM3_QDCTRL FTM_QDCTRL_REG(FTM3_BASE_PTR)

#define	FTM3_CONF FTM_CONF_REG(FTM3_BASE_PTR)

#define	FTM3_FLTPOL FTM_FLTPOL_REG(FTM3_BASE_PTR)

#define	FTM3_SYNCONF FTM_SYNCONF_REG(FTM3_BASE_PTR)

#define	FTM3_INVCTRL FTM_INVCTRL_REG(FTM3_BASE_PTR)

#define	FTM3_SWOCTRL FTM_SWOCTRL_REG(FTM3_BASE_PTR)

#define	FTM3_PWMLOAD FTM_PWMLOAD_REG(FTM3_BASE_PTR)

#define	FTM0_CnSC(index) FTM_CnSC_REG(FTM0_BASE_PTR,index)

#define	FTM1_CnSC(index) FTM_CnSC_REG(FTM1_BASE_PTR,index)

#define	FTM2_CnSC(index) FTM_CnSC_REG(FTM2_BASE_PTR,index)

#define	FTM3_CnSC(index) FTM_CnSC_REG(FTM3_BASE_PTR,index)

#define	FTM0_CnV(index) FTM_CnV_REG(FTM0_BASE_PTR,index)

#define	FTM1_CnV(index) FTM_CnV_REG(FTM1_BASE_PTR,index)

#define	FTM2_CnV(index) FTM_CnV_REG(FTM2_BASE_PTR,index)

#define	FTM3_CnV(index) FTM_CnV_REG(FTM3_BASE_PTR,index)

#define	GPIO_PDOR_REG(base) ((base)->PDOR)

#define	GPIO_PSOR_REG(base) ((base)->PSOR)

#define	GPIO_PCOR_REG(base) ((base)->PCOR)

#define	GPIO_PTOR_REG(base) ((base)->PTOR)

#define	GPIO_PDIR_REG(base) ((base)->PDIR)

#define	GPIO_PDDR_REG(base) ((base)->PDDR)

#define	GPIO_PDOR_PDO_MASK 0xFFFFFFFFu

#define	GPIO_PDOR_PDO_SHIFT 0

#define	GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)

#define	GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu

#define	GPIO_PSOR_PTSO_SHIFT 0

#define	GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)

#define	GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu

#define	GPIO_PCOR_PTCO_SHIFT 0

#define	GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)

#define	GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu

#define	GPIO_PTOR_PTTO_SHIFT 0

#define	GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)

#define	GPIO_PDIR_PDI_MASK 0xFFFFFFFFu

#define	GPIO_PDIR_PDI_SHIFT 0

#define	GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)

#define	GPIO_PDDR_PDD_MASK 0xFFFFFFFFu

#define	GPIO_PDDR_PDD_SHIFT 0

#define	GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)

#define	PTA_BASE_PTR ((GPIO_MemMapPtr)0x400FF000u)

#define	PTB_BASE_PTR ((GPIO_MemMapPtr)0x400FF040u)

#define	PTC_BASE_PTR ((GPIO_MemMapPtr)0x400FF080u)

#define	PTD_BASE_PTR ((GPIO_MemMapPtr)0x400FF0C0u)

#define	PTE_BASE_PTR ((GPIO_MemMapPtr)0x400FF100u)

#define	PTF_BASE_PTR ((GPIO_MemMapPtr)0x400FF140u)

#define	GPIO_BASE_PTRS { PTA_BASE_PTR, PTB_BASE_PTR, PTC_BASE_PTR, PTD_BASE_PTR, PTE_BASE_PTR, PTF_BASE_PTR }

#define	GPIOA_PDOR GPIO_PDOR_REG(PTA_BASE_PTR)

#define	GPIOA_PSOR GPIO_PSOR_REG(PTA_BASE_PTR)

#define	GPIOA_PCOR GPIO_PCOR_REG(PTA_BASE_PTR)

#define	GPIOA_PTOR GPIO_PTOR_REG(PTA_BASE_PTR)

#define	GPIOA_PDIR GPIO_PDIR_REG(PTA_BASE_PTR)

#define	GPIOA_PDDR GPIO_PDDR_REG(PTA_BASE_PTR)

#define	GPIOB_PDOR GPIO_PDOR_REG(PTB_BASE_PTR)

#define	GPIOB_PSOR GPIO_PSOR_REG(PTB_BASE_PTR)

#define	GPIOB_PCOR GPIO_PCOR_REG(PTB_BASE_PTR)

#define	GPIOB_PTOR GPIO_PTOR_REG(PTB_BASE_PTR)

#define	GPIOB_PDIR GPIO_PDIR_REG(PTB_BASE_PTR)

#define	GPIOB_PDDR GPIO_PDDR_REG(PTB_BASE_PTR)

#define	GPIOC_PDOR GPIO_PDOR_REG(PTC_BASE_PTR)

#define	GPIOC_PSOR GPIO_PSOR_REG(PTC_BASE_PTR)

#define	GPIOC_PCOR GPIO_PCOR_REG(PTC_BASE_PTR)

#define	GPIOC_PTOR GPIO_PTOR_REG(PTC_BASE_PTR)

#define	GPIOC_PDIR GPIO_PDIR_REG(PTC_BASE_PTR)

#define	GPIOC_PDDR GPIO_PDDR_REG(PTC_BASE_PTR)

#define	GPIOD_PDOR GPIO_PDOR_REG(PTD_BASE_PTR)

#define	GPIOD_PSOR GPIO_PSOR_REG(PTD_BASE_PTR)

#define	GPIOD_PCOR GPIO_PCOR_REG(PTD_BASE_PTR)

#define	GPIOD_PTOR GPIO_PTOR_REG(PTD_BASE_PTR)

#define	GPIOD_PDIR GPIO_PDIR_REG(PTD_BASE_PTR)

#define	GPIOD_PDDR GPIO_PDDR_REG(PTD_BASE_PTR)

#define	GPIOE_PDOR GPIO_PDOR_REG(PTE_BASE_PTR)

#define	GPIOE_PSOR GPIO_PSOR_REG(PTE_BASE_PTR)

#define	GPIOE_PCOR GPIO_PCOR_REG(PTE_BASE_PTR)

#define	GPIOE_PTOR GPIO_PTOR_REG(PTE_BASE_PTR)

#define	GPIOE_PDIR GPIO_PDIR_REG(PTE_BASE_PTR)

#define	GPIOE_PDDR GPIO_PDDR_REG(PTE_BASE_PTR)

#define	GPIOF_PDOR GPIO_PDOR_REG(PTF_BASE_PTR)

#define	GPIOF_PSOR GPIO_PSOR_REG(PTF_BASE_PTR)

#define	GPIOF_PCOR GPIO_PCOR_REG(PTF_BASE_PTR)

#define	GPIOF_PTOR GPIO_PTOR_REG(PTF_BASE_PTR)

#define	GPIOF_PDIR GPIO_PDIR_REG(PTF_BASE_PTR)

#define	GPIOF_PDDR GPIO_PDDR_REG(PTF_BASE_PTR)

#define	I2C_A1_REG(base) ((base)->A1)

#define	I2C_F_REG(base) ((base)->F)

#define	I2C_C1_REG(base) ((base)->C1)

#define	I2C_S_REG(base) ((base)->S)

#define	I2C_D_REG(base) ((base)->D)

#define	I2C_C2_REG(base) ((base)->C2)

#define	I2C_FLT_REG(base) ((base)->FLT)

#define	I2C_RA_REG(base) ((base)->RA)

#define	I2C_SMB_REG(base) ((base)->SMB)

#define	I2C_A2_REG(base) ((base)->A2)

#define	I2C_SLTH_REG(base) ((base)->SLTH)

#define	I2C_SLTL_REG(base) ((base)->SLTL)

#define	I2C_A1_AD_MASK 0xFEu

#define	I2C_A1_AD_SHIFT 1

#define	I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)

#define	I2C_F_ICR_MASK 0x3Fu

#define	I2C_F_ICR_SHIFT 0

#define	I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)

#define	I2C_F_MULT_MASK 0xC0u

#define	I2C_F_MULT_SHIFT 6

#define	I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)

#define	I2C_C1_DMAEN_MASK 0x1u

#define	I2C_C1_DMAEN_SHIFT 0

#define	I2C_C1_WUEN_MASK 0x2u

#define	I2C_C1_WUEN_SHIFT 1

#define	I2C_C1_RSTA_MASK 0x4u

#define	I2C_C1_RSTA_SHIFT 2

#define	I2C_C1_TXAK_MASK 0x8u

#define	I2C_C1_TXAK_SHIFT 3

#define	I2C_C1_TX_MASK 0x10u

#define	I2C_C1_TX_SHIFT 4

#define	I2C_C1_MST_MASK 0x20u

#define	I2C_C1_MST_SHIFT 5

#define	I2C_C1_IICIE_MASK 0x40u

#define	I2C_C1_IICIE_SHIFT 6

#define	I2C_C1_IICEN_MASK 0x80u

#define	I2C_C1_IICEN_SHIFT 7

#define	I2C_S_RXAK_MASK 0x1u

#define	I2C_S_RXAK_SHIFT 0

#define	I2C_S_IICIF_MASK 0x2u

#define	I2C_S_IICIF_SHIFT 1

#define	I2C_S_SRW_MASK 0x4u

#define	I2C_S_SRW_SHIFT 2

#define	I2C_S_RAM_MASK 0x8u

#define	I2C_S_RAM_SHIFT 3

#define	I2C_S_ARBL_MASK 0x10u

#define	I2C_S_ARBL_SHIFT 4

#define	I2C_S_BUSY_MASK 0x20u

#define	I2C_S_BUSY_SHIFT 5

#define	I2C_S_IAAS_MASK 0x40u

#define	I2C_S_IAAS_SHIFT 6

#define	I2C_S_TCF_MASK 0x80u

#define	I2C_S_TCF_SHIFT 7

#define	I2C_D_DATA_MASK 0xFFu

#define	I2C_D_DATA_SHIFT 0

#define	I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)

#define	I2C_C2_AD_MASK 0x7u

#define	I2C_C2_AD_SHIFT 0

#define	I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)

#define	I2C_C2_RMEN_MASK 0x8u

#define	I2C_C2_RMEN_SHIFT 3

#define	I2C_C2_SBRC_MASK 0x10u

#define	I2C_C2_SBRC_SHIFT 4

#define	I2C_C2_HDRS_MASK 0x20u

#define	I2C_C2_HDRS_SHIFT 5

#define	I2C_C2_ADEXT_MASK 0x40u

#define	I2C_C2_ADEXT_SHIFT 6

#define	I2C_C2_GCAEN_MASK 0x80u

#define	I2C_C2_GCAEN_SHIFT 7

#define	I2C_FLT_FLT_MASK 0x1Fu

#define	I2C_FLT_FLT_SHIFT 0

#define	I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)

#define	I2C_RA_RAD_MASK 0xFEu

#define	I2C_RA_RAD_SHIFT 1

#define	I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)

#define	I2C_SMB_SHTF2IE_MASK 0x1u

#define	I2C_SMB_SHTF2IE_SHIFT 0

#define	I2C_SMB_SHTF2_MASK 0x2u

#define	I2C_SMB_SHTF2_SHIFT 1

#define	I2C_SMB_SHTF1_MASK 0x4u

#define	I2C_SMB_SHTF1_SHIFT 2

#define	I2C_SMB_SLTF_MASK 0x8u

#define	I2C_SMB_SLTF_SHIFT 3

#define	I2C_SMB_TCKSEL_MASK 0x10u

#define	I2C_SMB_TCKSEL_SHIFT 4

#define	I2C_SMB_SIICAEN_MASK 0x20u

#define	I2C_SMB_SIICAEN_SHIFT 5

#define	I2C_SMB_ALERTEN_MASK 0x40u

#define	I2C_SMB_ALERTEN_SHIFT 6

#define	I2C_SMB_FACK_MASK 0x80u

#define	I2C_SMB_FACK_SHIFT 7

#define	I2C_A2_SAD_MASK 0xFEu

#define	I2C_A2_SAD_SHIFT 1

#define	I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)

#define	I2C_SLTH_SSLT_MASK 0xFFu

#define	I2C_SLTH_SSLT_SHIFT 0

#define	I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)

#define	I2C_SLTL_SSLT_MASK 0xFFu

#define	I2C_SLTL_SSLT_SHIFT 0

#define	I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)

#define	I2C0_BASE_PTR ((I2C_MemMapPtr)0x40066000u)

#define	I2C1_BASE_PTR ((I2C_MemMapPtr)0x40067000u)

#define	I2C_BASE_PTRS { I2C0_BASE_PTR, I2C1_BASE_PTR }

#define	I2C0_A1 I2C_A1_REG(I2C0_BASE_PTR)

#define	I2C0_F I2C_F_REG(I2C0_BASE_PTR)

#define	I2C0_C1 I2C_C1_REG(I2C0_BASE_PTR)

#define	I2C0_S I2C_S_REG(I2C0_BASE_PTR)

#define	I2C0_D I2C_D_REG(I2C0_BASE_PTR)

#define	I2C0_C2 I2C_C2_REG(I2C0_BASE_PTR)

#define	I2C0_FLT I2C_FLT_REG(I2C0_BASE_PTR)

#define	I2C0_RA I2C_RA_REG(I2C0_BASE_PTR)

#define	I2C0_SMB I2C_SMB_REG(I2C0_BASE_PTR)

#define	I2C0_A2 I2C_A2_REG(I2C0_BASE_PTR)

#define	I2C0_SLTH I2C_SLTH_REG(I2C0_BASE_PTR)

#define	I2C0_SLTL I2C_SLTL_REG(I2C0_BASE_PTR)

#define	I2C1_A1 I2C_A1_REG(I2C1_BASE_PTR)

#define	I2C1_F I2C_F_REG(I2C1_BASE_PTR)

#define	I2C1_C1 I2C_C1_REG(I2C1_BASE_PTR)

#define	I2C1_S I2C_S_REG(I2C1_BASE_PTR)

#define	I2C1_D I2C_D_REG(I2C1_BASE_PTR)

#define	I2C1_C2 I2C_C2_REG(I2C1_BASE_PTR)

#define	I2C1_FLT I2C_FLT_REG(I2C1_BASE_PTR)

#define	I2C1_RA I2C_RA_REG(I2C1_BASE_PTR)

#define	I2C1_SMB I2C_SMB_REG(I2C1_BASE_PTR)

#define	I2C1_A2 I2C_A2_REG(I2C1_BASE_PTR)

#define	I2C1_SLTH I2C_SLTH_REG(I2C1_BASE_PTR)

#define	I2C1_SLTL I2C_SLTL_REG(I2C1_BASE_PTR)

#define	I2S_TCSR_REG(base) ((base)->TCSR)

#define	I2S_TCR1_REG(base) ((base)->TCR1)

#define	I2S_TCR2_REG(base) ((base)->TCR2)

#define	I2S_TCR3_REG(base) ((base)->TCR3)

#define	I2S_TCR4_REG(base) ((base)->TCR4)

#define	I2S_TCR5_REG(base) ((base)->TCR5)

#define	I2S_TDR_REG(base, index) ((base)->TDR[index])

#define	I2S_TFR_REG(base, index) ((base)->TFR[index])

#define	I2S_TMR_REG(base) ((base)->TMR)

#define	I2S_RCSR_REG(base) ((base)->RCSR)

#define	I2S_RCR1_REG(base) ((base)->RCR1)

#define	I2S_RCR2_REG(base) ((base)->RCR2)

#define	I2S_RCR3_REG(base) ((base)->RCR3)

#define	I2S_RCR4_REG(base) ((base)->RCR4)

#define	I2S_RCR5_REG(base) ((base)->RCR5)

#define	I2S_RDR_REG(base, index) ((base)->RDR[index])

#define	I2S_RFR_REG(base, index) ((base)->RFR[index])

#define	I2S_RMR_REG(base) ((base)->RMR)

#define	I2S_MCR_REG(base) ((base)->MCR)

#define	I2S_MDR_REG(base) ((base)->MDR)

#define	I2S_TCSR_FRDE_MASK 0x1u

#define	I2S_TCSR_FRDE_SHIFT 0

#define	I2S_TCSR_FWDE_MASK 0x2u

#define	I2S_TCSR_FWDE_SHIFT 1

#define	I2S_TCSR_FRIE_MASK 0x100u

#define	I2S_TCSR_FRIE_SHIFT 8

#define	I2S_TCSR_FWIE_MASK 0x200u

#define	I2S_TCSR_FWIE_SHIFT 9

#define	I2S_TCSR_FEIE_MASK 0x400u

#define	I2S_TCSR_FEIE_SHIFT 10

#define	I2S_TCSR_SEIE_MASK 0x800u

#define	I2S_TCSR_SEIE_SHIFT 11

#define	I2S_TCSR_WSIE_MASK 0x1000u

#define	I2S_TCSR_WSIE_SHIFT 12

#define	I2S_TCSR_FRF_MASK 0x10000u

#define	I2S_TCSR_FRF_SHIFT 16

#define	I2S_TCSR_FWF_MASK 0x20000u

#define	I2S_TCSR_FWF_SHIFT 17

#define	I2S_TCSR_FEF_MASK 0x40000u

#define	I2S_TCSR_FEF_SHIFT 18

#define	I2S_TCSR_SEF_MASK 0x80000u

#define	I2S_TCSR_SEF_SHIFT 19

#define	I2S_TCSR_WSF_MASK 0x100000u

#define	I2S_TCSR_WSF_SHIFT 20

#define	I2S_TCSR_SR_MASK 0x1000000u

#define	I2S_TCSR_SR_SHIFT 24

#define	I2S_TCSR_FR_MASK 0x2000000u

#define	I2S_TCSR_FR_SHIFT 25

#define	I2S_TCSR_BCE_MASK 0x10000000u

#define	I2S_TCSR_BCE_SHIFT 28

#define	I2S_TCSR_DBGE_MASK 0x20000000u

#define	I2S_TCSR_DBGE_SHIFT 29

#define	I2S_TCSR_STOPE_MASK 0x40000000u

#define	I2S_TCSR_STOPE_SHIFT 30

#define	I2S_TCSR_TE_MASK 0x80000000u

#define	I2S_TCSR_TE_SHIFT 31

#define	I2S_TCR1_TFW_MASK 0x7u

#define	I2S_TCR1_TFW_SHIFT 0

#define	I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)

#define	I2S_TCR2_DIV_MASK 0xFFu

#define	I2S_TCR2_DIV_SHIFT 0

#define	I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)

#define	I2S_TCR2_BCD_MASK 0x1000000u

#define	I2S_TCR2_BCD_SHIFT 24

#define	I2S_TCR2_BCP_MASK 0x2000000u

#define	I2S_TCR2_BCP_SHIFT 25

#define	I2S_TCR2_MSEL_MASK 0xC000000u

#define	I2S_TCR2_MSEL_SHIFT 26

#define	I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)

#define	I2S_TCR2_BCI_MASK 0x10000000u

#define	I2S_TCR2_BCI_SHIFT 28

#define	I2S_TCR2_BCS_MASK 0x20000000u

#define	I2S_TCR2_BCS_SHIFT 29

#define	I2S_TCR2_SYNC_MASK 0xC0000000u

#define	I2S_TCR2_SYNC_SHIFT 30

#define	I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)

#define	I2S_TCR3_WDFL_MASK 0x1Fu

#define	I2S_TCR3_WDFL_SHIFT 0

#define	I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)

#define	I2S_TCR3_TCE_MASK 0x30000u

#define	I2S_TCR3_TCE_SHIFT 16

#define	I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)

#define	I2S_TCR4_FSD_MASK 0x1u

#define	I2S_TCR4_FSD_SHIFT 0

#define	I2S_TCR4_FSP_MASK 0x2u

#define	I2S_TCR4_FSP_SHIFT 1

#define	I2S_TCR4_FSE_MASK 0x8u

#define	I2S_TCR4_FSE_SHIFT 3

#define	I2S_TCR4_MF_MASK 0x10u

#define	I2S_TCR4_MF_SHIFT 4

#define	I2S_TCR4_SYWD_MASK 0x1F00u

#define	I2S_TCR4_SYWD_SHIFT 8

#define	I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)

#define	I2S_TCR4_FRSZ_MASK 0x1F0000u

#define	I2S_TCR4_FRSZ_SHIFT 16

#define	I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)

#define	I2S_TCR5_FBT_MASK 0x1F00u

#define	I2S_TCR5_FBT_SHIFT 8

#define	I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)

#define	I2S_TCR5_W0W_MASK 0x1F0000u

#define	I2S_TCR5_W0W_SHIFT 16

#define	I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)

#define	I2S_TCR5_WNW_MASK 0x1F000000u

#define	I2S_TCR5_WNW_SHIFT 24

#define	I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)

#define	I2S_TDR_TDR_MASK 0xFFFFFFFFu

#define	I2S_TDR_TDR_SHIFT 0

#define	I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)

#define	I2S_TFR_RFP_MASK 0xFu

#define	I2S_TFR_RFP_SHIFT 0

#define	I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)

#define	I2S_TFR_WFP_MASK 0xF0000u

#define	I2S_TFR_WFP_SHIFT 16

#define	I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)

#define	I2S_TMR_TWM_MASK 0xFFFFFFFFu

#define	I2S_TMR_TWM_SHIFT 0

#define	I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)

#define	I2S_RCSR_FRDE_MASK 0x1u

#define	I2S_RCSR_FRDE_SHIFT 0

#define	I2S_RCSR_FWDE_MASK 0x2u

#define	I2S_RCSR_FWDE_SHIFT 1

#define	I2S_RCSR_FRIE_MASK 0x100u

#define	I2S_RCSR_FRIE_SHIFT 8

#define	I2S_RCSR_FWIE_MASK 0x200u

#define	I2S_RCSR_FWIE_SHIFT 9

#define	I2S_RCSR_FEIE_MASK 0x400u

#define	I2S_RCSR_FEIE_SHIFT 10

#define	I2S_RCSR_SEIE_MASK 0x800u

#define	I2S_RCSR_SEIE_SHIFT 11

#define	I2S_RCSR_WSIE_MASK 0x1000u

#define	I2S_RCSR_WSIE_SHIFT 12

#define	I2S_RCSR_FRF_MASK 0x10000u

#define	I2S_RCSR_FRF_SHIFT 16

#define	I2S_RCSR_FWF_MASK 0x20000u

#define	I2S_RCSR_FWF_SHIFT 17

#define	I2S_RCSR_FEF_MASK 0x40000u

#define	I2S_RCSR_FEF_SHIFT 18

#define	I2S_RCSR_SEF_MASK 0x80000u

#define	I2S_RCSR_SEF_SHIFT 19

#define	I2S_RCSR_WSF_MASK 0x100000u

#define	I2S_RCSR_WSF_SHIFT 20

#define	I2S_RCSR_SR_MASK 0x1000000u

#define	I2S_RCSR_SR_SHIFT 24

#define	I2S_RCSR_FR_MASK 0x2000000u

#define	I2S_RCSR_FR_SHIFT 25

#define	I2S_RCSR_BCE_MASK 0x10000000u

#define	I2S_RCSR_BCE_SHIFT 28

#define	I2S_RCSR_DBGE_MASK 0x20000000u

#define	I2S_RCSR_DBGE_SHIFT 29

#define	I2S_RCSR_STOPE_MASK 0x40000000u

#define	I2S_RCSR_STOPE_SHIFT 30

#define	I2S_RCSR_RE_MASK 0x80000000u

#define	I2S_RCSR_RE_SHIFT 31

#define	I2S_RCR1_RFW_MASK 0x7u

#define	I2S_RCR1_RFW_SHIFT 0

#define	I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)

#define	I2S_RCR2_DIV_MASK 0xFFu

#define	I2S_RCR2_DIV_SHIFT 0

#define	I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)

#define	I2S_RCR2_BCD_MASK 0x1000000u

#define	I2S_RCR2_BCD_SHIFT 24

#define	I2S_RCR2_BCP_MASK 0x2000000u

#define	I2S_RCR2_BCP_SHIFT 25

#define	I2S_RCR2_MSEL_MASK 0xC000000u

#define	I2S_RCR2_MSEL_SHIFT 26

#define	I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)

#define	I2S_RCR2_BCI_MASK 0x10000000u

#define	I2S_RCR2_BCI_SHIFT 28

#define	I2S_RCR2_BCS_MASK 0x20000000u

#define	I2S_RCR2_BCS_SHIFT 29

#define	I2S_RCR2_SYNC_MASK 0xC0000000u

#define	I2S_RCR2_SYNC_SHIFT 30

#define	I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)

#define	I2S_RCR3_WDFL_MASK 0x1Fu

#define	I2S_RCR3_WDFL_SHIFT 0

#define	I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)

#define	I2S_RCR3_RCE_MASK 0x30000u

#define	I2S_RCR3_RCE_SHIFT 16

#define	I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)

#define	I2S_RCR4_FSD_MASK 0x1u

#define	I2S_RCR4_FSD_SHIFT 0

#define	I2S_RCR4_FSP_MASK 0x2u

#define	I2S_RCR4_FSP_SHIFT 1

#define	I2S_RCR4_FSE_MASK 0x8u

#define	I2S_RCR4_FSE_SHIFT 3

#define	I2S_RCR4_MF_MASK 0x10u

#define	I2S_RCR4_MF_SHIFT 4

#define	I2S_RCR4_SYWD_MASK 0x1F00u

#define	I2S_RCR4_SYWD_SHIFT 8

#define	I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)

#define	I2S_RCR4_FRSZ_MASK 0x1F0000u

#define	I2S_RCR4_FRSZ_SHIFT 16

#define	I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)

#define	I2S_RCR5_FBT_MASK 0x1F00u

#define	I2S_RCR5_FBT_SHIFT 8

#define	I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)

#define	I2S_RCR5_W0W_MASK 0x1F0000u

#define	I2S_RCR5_W0W_SHIFT 16

#define	I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)

#define	I2S_RCR5_WNW_MASK 0x1F000000u

#define	I2S_RCR5_WNW_SHIFT 24

#define	I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)

#define	I2S_RDR_RDR_MASK 0xFFFFFFFFu

#define	I2S_RDR_RDR_SHIFT 0

#define	I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)

#define	I2S_RFR_RFP_MASK 0xFu

#define	I2S_RFR_RFP_SHIFT 0

#define	I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)

#define	I2S_RFR_WFP_MASK 0xF0000u

#define	I2S_RFR_WFP_SHIFT 16

#define	I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)

#define	I2S_RMR_RWM_MASK 0xFFFFFFFFu

#define	I2S_RMR_RWM_SHIFT 0

#define	I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)

#define	I2S_MCR_MICS_MASK 0x3000000u

#define	I2S_MCR_MICS_SHIFT 24

#define	I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)

#define	I2S_MCR_MOE_MASK 0x40000000u

#define	I2S_MCR_MOE_SHIFT 30

#define	I2S_MCR_DUF_MASK 0x80000000u

#define	I2S_MCR_DUF_SHIFT 31

#define	I2S_MDR_DIVIDE_MASK 0xFFFu

#define	I2S_MDR_DIVIDE_SHIFT 0

#define	I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)

#define	I2S_MDR_FRACT_MASK 0xFF000u

#define	I2S_MDR_FRACT_SHIFT 12

#define	I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)

#define	I2S0_BASE_PTR ((I2S_MemMapPtr)0x4002F000u)

#define	I2S1_BASE_PTR ((I2S_MemMapPtr)0x400AF000u)

#define	I2S_BASE_PTRS { I2S0_BASE_PTR, I2S1_BASE_PTR }

#define	I2S0_TCSR I2S_TCSR_REG(I2S0_BASE_PTR)

#define	I2S0_TCR1 I2S_TCR1_REG(I2S0_BASE_PTR)

#define	I2S0_TCR2 I2S_TCR2_REG(I2S0_BASE_PTR)

#define	I2S0_TCR3 I2S_TCR3_REG(I2S0_BASE_PTR)

#define	I2S0_TCR4 I2S_TCR4_REG(I2S0_BASE_PTR)

#define	I2S0_TCR5 I2S_TCR5_REG(I2S0_BASE_PTR)

#define	I2S0_TDR0 I2S_TDR_REG(I2S0_BASE_PTR,0)

#define	I2S0_TDR1 I2S_TDR_REG(I2S0_BASE_PTR,1)

#define	I2S0_TFR0 I2S_TFR_REG(I2S0_BASE_PTR,0)

#define	I2S0_TFR1 I2S_TFR_REG(I2S0_BASE_PTR,1)

#define	I2S0_TMR I2S_TMR_REG(I2S0_BASE_PTR)

#define	I2S0_RCSR I2S_RCSR_REG(I2S0_BASE_PTR)

#define	I2S0_RCR1 I2S_RCR1_REG(I2S0_BASE_PTR)

#define	I2S0_RCR2 I2S_RCR2_REG(I2S0_BASE_PTR)

#define	I2S0_RCR3 I2S_RCR3_REG(I2S0_BASE_PTR)

#define	I2S0_RCR4 I2S_RCR4_REG(I2S0_BASE_PTR)

#define	I2S0_RCR5 I2S_RCR5_REG(I2S0_BASE_PTR)

#define	I2S0_RDR0 I2S_RDR_REG(I2S0_BASE_PTR,0)

#define	I2S0_RDR1 I2S_RDR_REG(I2S0_BASE_PTR,1)

#define	I2S0_RFR0 I2S_RFR_REG(I2S0_BASE_PTR,0)

#define	I2S0_RFR1 I2S_RFR_REG(I2S0_BASE_PTR,1)

#define	I2S0_RMR I2S_RMR_REG(I2S0_BASE_PTR)

#define	I2S0_MCR I2S_MCR_REG(I2S0_BASE_PTR)

#define	I2S0_MDR I2S_MDR_REG(I2S0_BASE_PTR)

#define	I2S1_TCSR I2S_TCSR_REG(I2S1_BASE_PTR)

#define	I2S1_TCR1 I2S_TCR1_REG(I2S1_BASE_PTR)

#define	I2S1_TCR2 I2S_TCR2_REG(I2S1_BASE_PTR)

#define	I2S1_TCR3 I2S_TCR3_REG(I2S1_BASE_PTR)

#define	I2S1_TCR4 I2S_TCR4_REG(I2S1_BASE_PTR)

#define	I2S1_TCR5 I2S_TCR5_REG(I2S1_BASE_PTR)

#define	I2S1_TDR0 I2S_TDR_REG(I2S1_BASE_PTR,0)

#define	I2S1_TDR1 I2S_TDR_REG(I2S1_BASE_PTR,1)

#define	I2S1_TFR0 I2S_TFR_REG(I2S1_BASE_PTR,0)

#define	I2S1_TFR1 I2S_TFR_REG(I2S1_BASE_PTR,1)

#define	I2S1_TMR I2S_TMR_REG(I2S1_BASE_PTR)

#define	I2S1_RCSR I2S_RCSR_REG(I2S1_BASE_PTR)

#define	I2S1_RCR1 I2S_RCR1_REG(I2S1_BASE_PTR)

#define	I2S1_RCR2 I2S_RCR2_REG(I2S1_BASE_PTR)

#define	I2S1_RCR3 I2S_RCR3_REG(I2S1_BASE_PTR)

#define	I2S1_RCR4 I2S_RCR4_REG(I2S1_BASE_PTR)

#define	I2S1_RCR5 I2S_RCR5_REG(I2S1_BASE_PTR)

#define	I2S1_RDR0 I2S_RDR_REG(I2S1_BASE_PTR,0)

#define	I2S1_RDR1 I2S_RDR_REG(I2S1_BASE_PTR,1)

#define	I2S1_RFR0 I2S_RFR_REG(I2S1_BASE_PTR,0)

#define	I2S1_RFR1 I2S_RFR_REG(I2S1_BASE_PTR,1)

#define	I2S1_RMR I2S_RMR_REG(I2S1_BASE_PTR)

#define	I2S1_MCR I2S_MCR_REG(I2S1_BASE_PTR)

#define	I2S1_MDR I2S_MDR_REG(I2S1_BASE_PTR)

#define	I2S0_TDR(index) I2S_TDR_REG(I2S0_BASE_PTR,index)

#define	I2S1_TDR(index) I2S_TDR_REG(I2S1_BASE_PTR,index)

#define	I2S0_TFR(index) I2S_TFR_REG(I2S0_BASE_PTR,index)

#define	I2S1_TFR(index) I2S_TFR_REG(I2S1_BASE_PTR,index)

#define	I2S0_RDR(index) I2S_RDR_REG(I2S0_BASE_PTR,index)

#define	I2S1_RDR(index) I2S_RDR_REG(I2S1_BASE_PTR,index)

#define	I2S0_RFR(index) I2S_RFR_REG(I2S0_BASE_PTR,index)

#define	I2S1_RFR(index) I2S_RFR_REG(I2S1_BASE_PTR,index)

#define	ITM_STIM_READ_REG(base, index2) ((base)->STIM_READ[index2])

#define	ITM_STIM_WRITE_REG(base, index2) ((base)->STIM_WRITE[index2])

#define	ITM_TER_REG(base) ((base)->TER)

#define	ITM_TPR_REG(base) ((base)->TPR)

#define	ITM_TCR_REG(base) ((base)->TCR)

#define	ITM_LAR_REG(base) ((base)->LAR)

#define	ITM_LSR_REG(base) ((base)->LSR)

#define	ITM_PID4_REG(base) ((base)->PID4)

#define	ITM_PID5_REG(base) ((base)->PID5)

#define	ITM_PID6_REG(base) ((base)->PID6)

#define	ITM_PID7_REG(base) ((base)->PID7)

#define	ITM_PID0_REG(base) ((base)->PID0)

#define	ITM_PID1_REG(base) ((base)->PID1)

#define	ITM_PID2_REG(base) ((base)->PID2)

#define	ITM_PID3_REG(base) ((base)->PID3)

#define	ITM_CID0_REG(base) ((base)->CID0)

#define	ITM_CID1_REG(base) ((base)->CID1)

#define	ITM_CID2_REG(base) ((base)->CID2)

#define	ITM_CID3_REG(base) ((base)->CID3)

#define	ITM_BASE_PTR ((ITM_MemMapPtr)0xE0000000u)

#define	ITM_BASE_PTRS { ITM_BASE_PTR }

#define	ITM_STIM0_READ ITM_STIM_READ_REG(ITM_BASE_PTR,0)

#define	ITM_STIM0_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,0)

#define	ITM_STIM1_READ ITM_STIM_READ_REG(ITM_BASE_PTR,1)

#define	ITM_STIM1_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,1)

#define	ITM_STIM2_READ ITM_STIM_READ_REG(ITM_BASE_PTR,2)

#define	ITM_STIM2_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,2)

#define	ITM_STIM3_READ ITM_STIM_READ_REG(ITM_BASE_PTR,3)

#define	ITM_STIM3_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,3)

#define	ITM_STIM4_READ ITM_STIM_READ_REG(ITM_BASE_PTR,4)

#define	ITM_STIM4_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,4)

#define	ITM_STIM5_READ ITM_STIM_READ_REG(ITM_BASE_PTR,5)

#define	ITM_STIM5_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,5)

#define	ITM_STIM6_READ ITM_STIM_READ_REG(ITM_BASE_PTR,6)

#define	ITM_STIM6_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,6)

#define	ITM_STIM7_READ ITM_STIM_READ_REG(ITM_BASE_PTR,7)

#define	ITM_STIM7_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,7)

#define	ITM_STIM8_READ ITM_STIM_READ_REG(ITM_BASE_PTR,8)

#define	ITM_STIM8_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,8)

#define	ITM_STIM9_READ ITM_STIM_READ_REG(ITM_BASE_PTR,9)

#define	ITM_STIM9_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,9)

#define	ITM_STIM10_READ ITM_STIM_READ_REG(ITM_BASE_PTR,10)

#define	ITM_STIM10_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,10)

#define	ITM_STIM11_READ ITM_STIM_READ_REG(ITM_BASE_PTR,11)

#define	ITM_STIM11_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,11)

#define	ITM_STIM12_READ ITM_STIM_READ_REG(ITM_BASE_PTR,12)

#define	ITM_STIM12_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,12)

#define	ITM_STIM13_READ ITM_STIM_READ_REG(ITM_BASE_PTR,13)

#define	ITM_STIM13_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,13)

#define	ITM_STIM14_READ ITM_STIM_READ_REG(ITM_BASE_PTR,14)

#define	ITM_STIM14_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,14)

#define	ITM_STIM15_READ ITM_STIM_READ_REG(ITM_BASE_PTR,15)

#define	ITM_STIM15_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,15)

#define	ITM_STIM16_READ ITM_STIM_READ_REG(ITM_BASE_PTR,16)

#define	ITM_STIM16_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,16)

#define	ITM_STIM17_READ ITM_STIM_READ_REG(ITM_BASE_PTR,17)

#define	ITM_STIM17_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,17)

#define	ITM_STIM18_READ ITM_STIM_READ_REG(ITM_BASE_PTR,18)

#define	ITM_STIM18_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,18)

#define	ITM_STIM19_READ ITM_STIM_READ_REG(ITM_BASE_PTR,19)

#define	ITM_STIM19_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,19)

#define	ITM_STIM20_READ ITM_STIM_READ_REG(ITM_BASE_PTR,20)

#define	ITM_STIM20_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,20)

#define	ITM_STIM21_READ ITM_STIM_READ_REG(ITM_BASE_PTR,21)

#define	ITM_STIM21_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,21)

#define	ITM_STIM22_READ ITM_STIM_READ_REG(ITM_BASE_PTR,22)

#define	ITM_STIM22_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,22)

#define	ITM_STIM23_READ ITM_STIM_READ_REG(ITM_BASE_PTR,23)

#define	ITM_STIM23_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,23)

#define	ITM_STIM24_READ ITM_STIM_READ_REG(ITM_BASE_PTR,24)

#define	ITM_STIM24_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,24)

#define	ITM_STIM25_READ ITM_STIM_READ_REG(ITM_BASE_PTR,25)

#define	ITM_STIM25_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,25)

#define	ITM_STIM26_READ ITM_STIM_READ_REG(ITM_BASE_PTR,26)

#define	ITM_STIM26_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,26)

#define	ITM_STIM27_READ ITM_STIM_READ_REG(ITM_BASE_PTR,27)

#define	ITM_STIM27_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,27)

#define	ITM_STIM28_READ ITM_STIM_READ_REG(ITM_BASE_PTR,28)

#define	ITM_STIM28_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,28)

#define	ITM_STIM29_READ ITM_STIM_READ_REG(ITM_BASE_PTR,29)

#define	ITM_STIM29_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,29)

#define	ITM_STIM30_READ ITM_STIM_READ_REG(ITM_BASE_PTR,30)

#define	ITM_STIM30_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,30)

#define	ITM_STIM31_READ ITM_STIM_READ_REG(ITM_BASE_PTR,31)

#define	ITM_STIM31_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,31)

#define	ITM_TER ITM_TER_REG(ITM_BASE_PTR)

#define	ITM_TPR ITM_TPR_REG(ITM_BASE_PTR)

#define	ITM_TCR ITM_TCR_REG(ITM_BASE_PTR)

#define	ITM_LAR ITM_LAR_REG(ITM_BASE_PTR)

#define	ITM_LSR ITM_LSR_REG(ITM_BASE_PTR)

#define	ITM_PID4 ITM_PID4_REG(ITM_BASE_PTR)

#define	ITM_PID5 ITM_PID5_REG(ITM_BASE_PTR)

#define	ITM_PID6 ITM_PID6_REG(ITM_BASE_PTR)

#define	ITM_PID7 ITM_PID7_REG(ITM_BASE_PTR)

#define	ITM_PID0 ITM_PID0_REG(ITM_BASE_PTR)

#define	ITM_PID1 ITM_PID1_REG(ITM_BASE_PTR)

#define	ITM_PID2 ITM_PID2_REG(ITM_BASE_PTR)

#define	ITM_PID3 ITM_PID3_REG(ITM_BASE_PTR)

#define	ITM_CID0 ITM_CID0_REG(ITM_BASE_PTR)

#define	ITM_CID1 ITM_CID1_REG(ITM_BASE_PTR)

#define	ITM_CID2 ITM_CID2_REG(ITM_BASE_PTR)

#define	ITM_CID3 ITM_CID3_REG(ITM_BASE_PTR)

#define	ITM_STIM_READ(index2) ITM_STIM_READ_REG(ITM_BASE_PTR,index2)

#define	ITM_STIM_WRITE(index2) ITM_STIM_WRITE_REG(ITM_BASE_PTR,index2)

#define	LCDC_LSSAR_REG(base) ((base)->LSSAR)

#define	LCDC_LSR_REG(base) ((base)->LSR)

#define	LCDC_LVPWR_REG(base) ((base)->LVPWR)

#define	LCDC_LCPR_REG(base) ((base)->LCPR)

#define	LCDC_LCWHB_REG(base) ((base)->LCWHB)

#define	LCDC_LCCMR_REG(base) ((base)->LCCMR)

#define	LCDC_LPCR_REG(base) ((base)->LPCR)

#define	LCDC_LHCR_REG(base) ((base)->LHCR)

#define	LCDC_LVCR_REG(base) ((base)->LVCR)

#define	LCDC_LPOR_REG(base) ((base)->LPOR)

#define	LCDC_LPCCR_REG(base) ((base)->LPCCR)

#define	LCDC_LDCR_REG(base) ((base)->LDCR)

#define	LCDC_LRMCR_REG(base) ((base)->LRMCR)

#define	LCDC_LICR_REG(base) ((base)->LICR)

#define	LCDC_LIER_REG(base) ((base)->LIER)

#define	LCDC_LISR_REG(base) ((base)->LISR)

#define	LCDC_LGWSAR_REG(base) ((base)->LGWSAR)

#define	LCDC_LGWSR_REG(base) ((base)->LGWSR)

#define	LCDC_LGWVPWR_REG(base) ((base)->LGWVPWR)

#define	LCDC_LGWPOR_REG(base) ((base)->LGWPOR)

#define	LCDC_LGWPR_REG(base) ((base)->LGWPR)

#define	LCDC_LGWCR_REG(base) ((base)->LGWCR)

#define	LCDC_LGWDCR_REG(base) ((base)->LGWDCR)

#define	LCDC_LAUSCR_REG(base) ((base)->LAUSCR)

#define	LCDC_LAUSCCR_REG(base) ((base)->LAUSCCR)

#define	LCDC_LSSAR_SSA_MASK 0xFFFFFFFCu

#define	LCDC_LSSAR_SSA_SHIFT 2

#define	LCDC_LSSAR_SSA(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LSSAR_SSA_SHIFT))&LCDC_LSSAR_SSA_MASK)

#define	LCDC_LSR_YMAX_MASK 0x3FFu

#define	LCDC_LSR_YMAX_SHIFT 0

#define	LCDC_LSR_YMAX(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LSR_YMAX_SHIFT))&LCDC_LSR_YMAX_MASK)

#define	LCDC_LSR_XMAX_MASK 0x7F00000u

#define	LCDC_LSR_XMAX_SHIFT 20

#define	LCDC_LSR_XMAX(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LSR_XMAX_SHIFT))&LCDC_LSR_XMAX_MASK)

#define	LCDC_LVPWR_VPW_MASK 0x7FFu

#define	LCDC_LVPWR_VPW_SHIFT 0

#define	LCDC_LVPWR_VPW(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LVPWR_VPW_SHIFT))&LCDC_LVPWR_VPW_MASK)

#define	LCDC_LCPR_CYP_MASK 0x3FFu

#define	LCDC_LCPR_CYP_SHIFT 0

#define	LCDC_LCPR_CYP(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LCPR_CYP_SHIFT))&LCDC_LCPR_CYP_MASK)

#define	LCDC_LCPR_CXP_MASK 0x3FF0000u

#define	LCDC_LCPR_CXP_SHIFT 16

#define	LCDC_LCPR_CXP(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LCPR_CXP_SHIFT))&LCDC_LCPR_CXP_MASK)

#define	LCDC_LCPR_OP_MASK 0x10000000u

#define	LCDC_LCPR_OP_SHIFT 28

#define	LCDC_LCPR_CC_MASK 0xC0000000u

#define	LCDC_LCPR_CC_SHIFT 30

#define	LCDC_LCPR_CC(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LCPR_CC_SHIFT))&LCDC_LCPR_CC_MASK)

#define	LCDC_LCWHB_BD_MASK 0xFFu

#define	LCDC_LCWHB_BD_SHIFT 0

#define	LCDC_LCWHB_BD(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LCWHB_BD_SHIFT))&LCDC_LCWHB_BD_MASK)

#define	LCDC_LCWHB_CH_MASK 0x1F0000u

#define	LCDC_LCWHB_CH_SHIFT 16

#define	LCDC_LCWHB_CH(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LCWHB_CH_SHIFT))&LCDC_LCWHB_CH_MASK)

#define	LCDC_LCWHB_CW_MASK 0x1F000000u

#define	LCDC_LCWHB_CW_SHIFT 24

#define	LCDC_LCWHB_CW(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LCWHB_CW_SHIFT))&LCDC_LCWHB_CW_MASK)

#define	LCDC_LCWHB_BK_EN_MASK 0x80000000u

#define	LCDC_LCWHB_BK_EN_SHIFT 31

#define	LCDC_LCCMR_CUR_COL_B_MASK 0x3Fu

#define	LCDC_LCCMR_CUR_COL_B_SHIFT 0

#define	LCDC_LCCMR_CUR_COL_B(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LCCMR_CUR_COL_B_SHIFT))&LCDC_LCCMR_CUR_COL_B_MASK)

#define	LCDC_LCCMR_CUR_COL_G_MASK 0xFC0u

#define	LCDC_LCCMR_CUR_COL_G_SHIFT 6

#define	LCDC_LCCMR_CUR_COL_G(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LCCMR_CUR_COL_G_SHIFT))&LCDC_LCCMR_CUR_COL_G_MASK)

#define	LCDC_LCCMR_CUR_COL_R_MASK 0x3F000u

#define	LCDC_LCCMR_CUR_COL_R_SHIFT 12

#define	LCDC_LCCMR_CUR_COL_R(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LCCMR_CUR_COL_R_SHIFT))&LCDC_LCCMR_CUR_COL_R_MASK)

#define	LCDC_LPCR_PCD_MASK 0x3Fu

#define	LCDC_LPCR_PCD_SHIFT 0

#define	LCDC_LPCR_PCD(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LPCR_PCD_SHIFT))&LCDC_LPCR_PCD_MASK)

#define	LCDC_LPCR_SCLKSEL_MASK 0x80u

#define	LCDC_LPCR_SCLKSEL_SHIFT 7

#define	LCDC_LPCR_ACD_MASK 0x7F00u

#define	LCDC_LPCR_ACD_SHIFT 8

#define	LCDC_LPCR_ACD(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LPCR_ACD_SHIFT))&LCDC_LPCR_ACD_MASK)

#define	LCDC_LPCR_ACDSEL_MASK 0x8000u

#define	LCDC_LPCR_ACDSEL_SHIFT 15

#define	LCDC_LPCR_REV_VS_MASK 0x10000u

#define	LCDC_LPCR_REV_VS_SHIFT 16

#define	LCDC_LPCR_SWAP_SEL_MASK 0x20000u

#define	LCDC_LPCR_SWAP_SEL_SHIFT 17

#define	LCDC_LPCR_END_SEL_MASK 0x40000u

#define	LCDC_LPCR_END_SEL_SHIFT 18

#define	LCDC_LPCR_SCLKIDLE_MASK 0x80000u

#define	LCDC_LPCR_SCLKIDLE_SHIFT 19

#define	LCDC_LPCR_OEPOL_MASK 0x100000u

#define	LCDC_LPCR_OEPOL_SHIFT 20

#define	LCDC_LPCR_CLKPOL_MASK 0x200000u

#define	LCDC_LPCR_CLKPOL_SHIFT 21

#define	LCDC_LPCR_LPPOL_MASK 0x400000u

#define	LCDC_LPCR_LPPOL_SHIFT 22

#define	LCDC_LPCR_FLMPOL_MASK 0x800000u

#define	LCDC_LPCR_FLMPOL_SHIFT 23

#define	LCDC_LPCR_PIXPOL_MASK 0x1000000u

#define	LCDC_LPCR_PIXPOL_SHIFT 24

#define	LCDC_LPCR_BPIX_MASK 0xE000000u

#define	LCDC_LPCR_BPIX_SHIFT 25

#define	LCDC_LPCR_BPIX(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LPCR_BPIX_SHIFT))&LCDC_LPCR_BPIX_MASK)

#define	LCDC_LPCR_PBSIZ_MASK 0x30000000u

#define	LCDC_LPCR_PBSIZ_SHIFT 28

#define	LCDC_LPCR_PBSIZ(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LPCR_PBSIZ_SHIFT))&LCDC_LPCR_PBSIZ_MASK)

#define	LCDC_LPCR_COLOR_MASK 0x40000000u

#define	LCDC_LPCR_COLOR_SHIFT 30

#define	LCDC_LPCR_TFT_MASK 0x80000000u

#define	LCDC_LPCR_TFT_SHIFT 31

#define	LCDC_LHCR_H_WAIT_2_MASK 0xFFu

#define	LCDC_LHCR_H_WAIT_2_SHIFT 0

#define	LCDC_LHCR_H_WAIT_2(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LHCR_H_WAIT_2_SHIFT))&LCDC_LHCR_H_WAIT_2_MASK)

#define	LCDC_LHCR_H_WAIT_1_MASK 0xFF00u

#define	LCDC_LHCR_H_WAIT_1_SHIFT 8

#define	LCDC_LHCR_H_WAIT_1(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LHCR_H_WAIT_1_SHIFT))&LCDC_LHCR_H_WAIT_1_MASK)

#define	LCDC_LHCR_H_WIDTH_MASK 0xFC000000u

#define	LCDC_LHCR_H_WIDTH_SHIFT 26

#define	LCDC_LHCR_H_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LHCR_H_WIDTH_SHIFT))&LCDC_LHCR_H_WIDTH_MASK)

#define	LCDC_LVCR_V_WAIT_2_MASK 0xFFu

#define	LCDC_LVCR_V_WAIT_2_SHIFT 0

#define	LCDC_LVCR_V_WAIT_2(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LVCR_V_WAIT_2_SHIFT))&LCDC_LVCR_V_WAIT_2_MASK)

#define	LCDC_LVCR_V_WAIT_1_MASK 0xFF00u

#define	LCDC_LVCR_V_WAIT_1_SHIFT 8

#define	LCDC_LVCR_V_WAIT_1(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LVCR_V_WAIT_1_SHIFT))&LCDC_LVCR_V_WAIT_1_MASK)

#define	LCDC_LVCR_V_WIDTH_MASK 0xFC000000u

#define	LCDC_LVCR_V_WIDTH_SHIFT 26

#define	LCDC_LVCR_V_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LVCR_V_WIDTH_SHIFT))&LCDC_LVCR_V_WIDTH_MASK)

#define	LCDC_LPOR_POS_MASK 0x1Fu

#define	LCDC_LPOR_POS_SHIFT 0

#define	LCDC_LPOR_POS(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LPOR_POS_SHIFT))&LCDC_LPOR_POS_MASK)

#define	LCDC_LPCCR_PW_MASK 0xFFu

#define	LCDC_LPCCR_PW_SHIFT 0

#define	LCDC_LPCCR_PW(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LPCCR_PW_SHIFT))&LCDC_LPCCR_PW_MASK)

#define	LCDC_LPCCR_CC_EN_MASK 0x100u

#define	LCDC_LPCCR_CC_EN_SHIFT 8

#define	LCDC_LPCCR_SCR_MASK 0x600u

#define	LCDC_LPCCR_SCR_SHIFT 9

#define	LCDC_LPCCR_SCR(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LPCCR_SCR_SHIFT))&LCDC_LPCCR_SCR_MASK)

#define	LCDC_LPCCR_LDMSK_MASK 0x8000u

#define	LCDC_LPCCR_LDMSK_SHIFT 15

#define	LCDC_LDCR_TM_MASK 0x7Fu

#define	LCDC_LDCR_TM_SHIFT 0

#define	LCDC_LDCR_TM(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LDCR_TM_SHIFT))&LCDC_LDCR_TM_MASK)

#define	LCDC_LDCR_HM_MASK 0x7F0000u

#define	LCDC_LDCR_HM_SHIFT 16

#define	LCDC_LDCR_HM(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LDCR_HM_SHIFT))&LCDC_LDCR_HM_MASK)

#define	LCDC_LDCR_BURST_MASK 0x80000000u

#define	LCDC_LDCR_BURST_SHIFT 31

#define	LCDC_LRMCR_SELF_REF_MASK 0x1u

#define	LCDC_LRMCR_SELF_REF_SHIFT 0

#define	LCDC_LICR_INTCON_MASK 0x1u

#define	LCDC_LICR_INTCON_SHIFT 0

#define	LCDC_LICR_INTSYN_MASK 0x4u

#define	LCDC_LICR_INTSYN_SHIFT 2

#define	LCDC_LICR_GW_INT_CON_MASK 0x10u

#define	LCDC_LICR_GW_INT_CON_SHIFT 4

#define	LCDC_LIER_BOF_EN_MASK 0x1u

#define	LCDC_LIER_BOF_EN_SHIFT 0

#define	LCDC_LIER_EOF_EN_MASK 0x2u

#define	LCDC_LIER_EOF_EN_SHIFT 1

#define	LCDC_LIER_UDR_ERR_EN_MASK 0x8u

#define	LCDC_LIER_UDR_ERR_EN_SHIFT 3

#define	LCDC_LIER_GW_BOF_EN_MASK 0x10u

#define	LCDC_LIER_GW_BOF_EN_SHIFT 4

#define	LCDC_LIER_GW_EOF_EN_MASK 0x20u

#define	LCDC_LIER_GW_EOF_EN_SHIFT 5

#define	LCDC_LIER_GW_UDR_ERR_EN_MASK 0x80u

#define	LCDC_LIER_GW_UDR_ERR_EN_SHIFT 7

#define	LCDC_LISR_BOF_MASK 0x1u

#define	LCDC_LISR_BOF_SHIFT 0

#define	LCDC_LISR_EOF_MASK 0x2u

#define	LCDC_LISR_EOF_SHIFT 1

#define	LCDC_LISR_UDR_ERR_MASK 0x8u

#define	LCDC_LISR_UDR_ERR_SHIFT 3

#define	LCDC_LISR_GW_BOF_MASK 0x10u

#define	LCDC_LISR_GW_BOF_SHIFT 4

#define	LCDC_LISR_GW_EOF_MASK 0x20u

#define	LCDC_LISR_GW_EOF_SHIFT 5

#define	LCDC_LISR_GW_UDR_ERR_MASK 0x80u

#define	LCDC_LISR_GW_UDR_ERR_SHIFT 7

#define	LCDC_LGWSAR_GWSA_MASK 0xFFFFFFFCu

#define	LCDC_LGWSAR_GWSA_SHIFT 2

#define	LCDC_LGWSAR_GWSA(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LGWSAR_GWSA_SHIFT))&LCDC_LGWSAR_GWSA_MASK)

#define	LCDC_LGWSR_GWH_MASK 0x3FFu

#define	LCDC_LGWSR_GWH_SHIFT 0

#define	LCDC_LGWSR_GWH(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LGWSR_GWH_SHIFT))&LCDC_LGWSR_GWH_MASK)

#define	LCDC_LGWSR_GWW_MASK 0x7F00000u

#define	LCDC_LGWSR_GWW_SHIFT 20

#define	LCDC_LGWSR_GWW(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LGWSR_GWW_SHIFT))&LCDC_LGWSR_GWW_MASK)

#define	LCDC_LGWVPWR_GWVPW_MASK 0x7FFu

#define	LCDC_LGWVPWR_GWVPW_SHIFT 0

#define	LCDC_LGWVPWR_GWVPW(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LGWVPWR_GWVPW_SHIFT))&LCDC_LGWVPWR_GWVPW_MASK)

#define	LCDC_LGWPOR_GWPO_MASK 0x1Fu

#define	LCDC_LGWPOR_GWPO_SHIFT 0

#define	LCDC_LGWPOR_GWPO(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LGWPOR_GWPO_SHIFT))&LCDC_LGWPOR_GWPO_MASK)

#define	LCDC_LGWPR_GWYP_MASK 0x3FFu

#define	LCDC_LGWPR_GWYP_SHIFT 0

#define	LCDC_LGWPR_GWYP(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LGWPR_GWYP_SHIFT))&LCDC_LGWPR_GWYP_MASK)

#define	LCDC_LGWPR_GWXP_MASK 0x3FF0000u

#define	LCDC_LGWPR_GWXP_SHIFT 16

#define	LCDC_LGWPR_GWXP(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LGWPR_GWXP_SHIFT))&LCDC_LGWPR_GWXP_MASK)

#define	LCDC_LGWCR_GWCKB_MASK 0x3Fu

#define	LCDC_LGWCR_GWCKB_SHIFT 0

#define	LCDC_LGWCR_GWCKB(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LGWCR_GWCKB_SHIFT))&LCDC_LGWCR_GWCKB_MASK)

#define	LCDC_LGWCR_GWCKG_MASK 0xFC0u

#define	LCDC_LGWCR_GWCKG_SHIFT 6

#define	LCDC_LGWCR_GWCKG(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LGWCR_GWCKG_SHIFT))&LCDC_LGWCR_GWCKG_MASK)

#define	LCDC_LGWCR_GWCKR_MASK 0x3F000u

#define	LCDC_LGWCR_GWCKR_SHIFT 12

#define	LCDC_LGWCR_GWCKR(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LGWCR_GWCKR_SHIFT))&LCDC_LGWCR_GWCKR_MASK)

#define	LCDC_LGWCR_GW_RVS_MASK 0x200000u

#define	LCDC_LGWCR_GW_RVS_SHIFT 21

#define	LCDC_LGWCR_GWE_MASK 0x400000u

#define	LCDC_LGWCR_GWE_SHIFT 22

#define	LCDC_LGWCR_GWCKE_MASK 0x800000u

#define	LCDC_LGWCR_GWCKE_SHIFT 23

#define	LCDC_LGWCR_GWAV_MASK 0xFF000000u

#define	LCDC_LGWCR_GWAV_SHIFT 24

#define	LCDC_LGWCR_GWAV(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LGWCR_GWAV_SHIFT))&LCDC_LGWCR_GWAV_MASK)

#define	LCDC_LGWDCR_GWTM_MASK 0x7Fu

#define	LCDC_LGWDCR_GWTM_SHIFT 0

#define	LCDC_LGWDCR_GWTM(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LGWDCR_GWTM_SHIFT))&LCDC_LGWDCR_GWTM_MASK)

#define	LCDC_LGWDCR_GWHM_MASK 0x7F0000u

#define	LCDC_LGWDCR_GWHM_SHIFT 16

#define	LCDC_LGWDCR_GWHM(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LGWDCR_GWHM_SHIFT))&LCDC_LGWDCR_GWHM_MASK)

#define	LCDC_LGWDCR_GWBT_MASK 0x80000000u

#define	LCDC_LGWDCR_GWBT_SHIFT 31

#define	LCDC_LAUSCR_AGWCKB_MASK 0xFFu

#define	LCDC_LAUSCR_AGWCKB_SHIFT 0

#define	LCDC_LAUSCR_AGWCKB(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LAUSCR_AGWCKB_SHIFT))&LCDC_LAUSCR_AGWCKB_MASK)

#define	LCDC_LAUSCR_AGWCKG_MASK 0xFF00u

#define	LCDC_LAUSCR_AGWCKG_SHIFT 8

#define	LCDC_LAUSCR_AGWCKG(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LAUSCR_AGWCKG_SHIFT))&LCDC_LAUSCR_AGWCKG_MASK)

#define	LCDC_LAUSCR_AGWCKR_MASK 0xFF0000u

#define	LCDC_LAUSCR_AGWCKR_SHIFT 16

#define	LCDC_LAUSCR_AGWCKR(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LAUSCR_AGWCKR_SHIFT))&LCDC_LAUSCR_AGWCKR_MASK)

#define	LCDC_LAUSCR_AUS_Mode_MASK 0x80000000u

#define	LCDC_LAUSCR_AUS_Mode_SHIFT 31

#define	LCDC_LAUSCCR_ACUR_COL_B_MASK 0xFFu

#define	LCDC_LAUSCCR_ACUR_COL_B_SHIFT 0

#define	LCDC_LAUSCCR_ACUR_COL_B(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LAUSCCR_ACUR_COL_B_SHIFT))&LCDC_LAUSCCR_ACUR_COL_B_MASK)

#define	LCDC_LAUSCCR_ACUR_COL_G_MASK 0xFF00u

#define	LCDC_LAUSCCR_ACUR_COL_G_SHIFT 8

#define	LCDC_LAUSCCR_ACUR_COL_G(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LAUSCCR_ACUR_COL_G_SHIFT))&LCDC_LAUSCCR_ACUR_COL_G_MASK)

#define	LCDC_LAUSCCR_ACUR_COL_R_MASK 0xFF0000u

#define	LCDC_LAUSCCR_ACUR_COL_R_SHIFT 16

#define	LCDC_LAUSCCR_ACUR_COL_R(x) (((uint32_t)(((uint32_t)(x))<<LCDC_LAUSCCR_ACUR_COL_R_SHIFT))&LCDC_LAUSCCR_ACUR_COL_R_MASK)

#define	LCDC_BASE_PTR ((LCDC_MemMapPtr)0x400B6000u)

#define	LCDC_BASE_PTRS { LCDC_BASE_PTR }

#define	LCDC_LSSAR LCDC_LSSAR_REG(LCDC_BASE_PTR)

#define	LCDC_LSR LCDC_LSR_REG(LCDC_BASE_PTR)

#define	LCDC_LVPWR LCDC_LVPWR_REG(LCDC_BASE_PTR)

#define	LCDC_LCPR LCDC_LCPR_REG(LCDC_BASE_PTR)

#define	LCDC_LCWHB LCDC_LCWHB_REG(LCDC_BASE_PTR)

#define	LCDC_LCCMR LCDC_LCCMR_REG(LCDC_BASE_PTR)

#define	LCDC_LPCR LCDC_LPCR_REG(LCDC_BASE_PTR)

#define	LCDC_LHCR LCDC_LHCR_REG(LCDC_BASE_PTR)

#define	LCDC_LVCR LCDC_LVCR_REG(LCDC_BASE_PTR)

#define	LCDC_LPOR LCDC_LPOR_REG(LCDC_BASE_PTR)

#define	LCDC_LPCCR LCDC_LPCCR_REG(LCDC_BASE_PTR)

#define	LCDC_LDCR LCDC_LDCR_REG(LCDC_BASE_PTR)

#define	LCDC_LRMCR LCDC_LRMCR_REG(LCDC_BASE_PTR)

#define	LCDC_LICR LCDC_LICR_REG(LCDC_BASE_PTR)

#define	LCDC_LIER LCDC_LIER_REG(LCDC_BASE_PTR)

#define	LCDC_LISR LCDC_LISR_REG(LCDC_BASE_PTR)

#define	LCDC_LGWSAR LCDC_LGWSAR_REG(LCDC_BASE_PTR)

#define	LCDC_LGWSR LCDC_LGWSR_REG(LCDC_BASE_PTR)

#define	LCDC_LGWVPWR LCDC_LGWVPWR_REG(LCDC_BASE_PTR)

#define	LCDC_LGWPOR LCDC_LGWPOR_REG(LCDC_BASE_PTR)

#define	LCDC_LGWPR LCDC_LGWPR_REG(LCDC_BASE_PTR)

#define	LCDC_LGWCR LCDC_LGWCR_REG(LCDC_BASE_PTR)

#define	LCDC_LGWDCR LCDC_LGWDCR_REG(LCDC_BASE_PTR)

#define	LCDC_LAUSCR LCDC_LAUSCR_REG(LCDC_BASE_PTR)

#define	LCDC_LAUSCCR LCDC_LAUSCCR_REG(LCDC_BASE_PTR)

#define	LLWU_PE1_REG(base) ((base)->PE1)

#define	LLWU_PE2_REG(base) ((base)->PE2)

#define	LLWU_PE3_REG(base) ((base)->PE3)

#define	LLWU_PE4_REG(base) ((base)->PE4)

#define	LLWU_ME_REG(base) ((base)->ME)

#define	LLWU_F1_REG(base) ((base)->F1)

#define	LLWU_F2_REG(base) ((base)->F2)

#define	LLWU_F3_REG(base) ((base)->F3)

#define	LLWU_FILT1_REG(base) ((base)->FILT1)

#define	LLWU_FILT2_REG(base) ((base)->FILT2)

#define	LLWU_RST_REG(base) ((base)->RST)

#define	LLWU_PE1_WUPE0_MASK 0x3u

#define	LLWU_PE1_WUPE0_SHIFT 0

#define	LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)

#define	LLWU_PE1_WUPE1_MASK 0xCu

#define	LLWU_PE1_WUPE1_SHIFT 2

#define	LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)

#define	LLWU_PE1_WUPE2_MASK 0x30u

#define	LLWU_PE1_WUPE2_SHIFT 4

#define	LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)

#define	LLWU_PE1_WUPE3_MASK 0xC0u

#define	LLWU_PE1_WUPE3_SHIFT 6

#define	LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)

#define	LLWU_PE2_WUPE4_MASK 0x3u

#define	LLWU_PE2_WUPE4_SHIFT 0

#define	LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)

#define	LLWU_PE2_WUPE5_MASK 0xCu

#define	LLWU_PE2_WUPE5_SHIFT 2

#define	LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)

#define	LLWU_PE2_WUPE6_MASK 0x30u

#define	LLWU_PE2_WUPE6_SHIFT 4

#define	LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)

#define	LLWU_PE2_WUPE7_MASK 0xC0u

#define	LLWU_PE2_WUPE7_SHIFT 6

#define	LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)

#define	LLWU_PE3_WUPE8_MASK 0x3u

#define	LLWU_PE3_WUPE8_SHIFT 0

#define	LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)

#define	LLWU_PE3_WUPE9_MASK 0xCu

#define	LLWU_PE3_WUPE9_SHIFT 2

#define	LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)

#define	LLWU_PE3_WUPE10_MASK 0x30u

#define	LLWU_PE3_WUPE10_SHIFT 4

#define	LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)

#define	LLWU_PE3_WUPE11_MASK 0xC0u

#define	LLWU_PE3_WUPE11_SHIFT 6

#define	LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)

#define	LLWU_PE4_WUPE12_MASK 0x3u

#define	LLWU_PE4_WUPE12_SHIFT 0

#define	LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)

#define	LLWU_PE4_WUPE13_MASK 0xCu

#define	LLWU_PE4_WUPE13_SHIFT 2

#define	LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)

#define	LLWU_PE4_WUPE14_MASK 0x30u

#define	LLWU_PE4_WUPE14_SHIFT 4

#define	LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)

#define	LLWU_PE4_WUPE15_MASK 0xC0u

#define	LLWU_PE4_WUPE15_SHIFT 6

#define	LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)

#define	LLWU_ME_WUME0_MASK 0x1u

#define	LLWU_ME_WUME0_SHIFT 0

#define	LLWU_ME_WUME1_MASK 0x2u

#define	LLWU_ME_WUME1_SHIFT 1

#define	LLWU_ME_WUME2_MASK 0x4u

#define	LLWU_ME_WUME2_SHIFT 2

#define	LLWU_ME_WUME3_MASK 0x8u

#define	LLWU_ME_WUME3_SHIFT 3

#define	LLWU_ME_WUME4_MASK 0x10u

#define	LLWU_ME_WUME4_SHIFT 4

#define	LLWU_ME_WUME5_MASK 0x20u

#define	LLWU_ME_WUME5_SHIFT 5

#define	LLWU_ME_WUME6_MASK 0x40u

#define	LLWU_ME_WUME6_SHIFT 6

#define	LLWU_ME_WUME7_MASK 0x80u

#define	LLWU_ME_WUME7_SHIFT 7

#define	LLWU_F1_WUF0_MASK 0x1u

#define	LLWU_F1_WUF0_SHIFT 0

#define	LLWU_F1_WUF1_MASK 0x2u

#define	LLWU_F1_WUF1_SHIFT 1

#define	LLWU_F1_WUF2_MASK 0x4u

#define	LLWU_F1_WUF2_SHIFT 2

#define	LLWU_F1_WUF3_MASK 0x8u

#define	LLWU_F1_WUF3_SHIFT 3

#define	LLWU_F1_WUF4_MASK 0x10u

#define	LLWU_F1_WUF4_SHIFT 4

#define	LLWU_F1_WUF5_MASK 0x20u

#define	LLWU_F1_WUF5_SHIFT 5

#define	LLWU_F1_WUF6_MASK 0x40u

#define	LLWU_F1_WUF6_SHIFT 6

#define	LLWU_F1_WUF7_MASK 0x80u

#define	LLWU_F1_WUF7_SHIFT 7

#define	LLWU_F2_WUF8_MASK 0x1u

#define	LLWU_F2_WUF8_SHIFT 0

#define	LLWU_F2_WUF9_MASK 0x2u

#define	LLWU_F2_WUF9_SHIFT 1

#define	LLWU_F2_WUF10_MASK 0x4u

#define	LLWU_F2_WUF10_SHIFT 2

#define	LLWU_F2_WUF11_MASK 0x8u

#define	LLWU_F2_WUF11_SHIFT 3

#define	LLWU_F2_WUF12_MASK 0x10u

#define	LLWU_F2_WUF12_SHIFT 4

#define	LLWU_F2_WUF13_MASK 0x20u

#define	LLWU_F2_WUF13_SHIFT 5

#define	LLWU_F2_WUF14_MASK 0x40u

#define	LLWU_F2_WUF14_SHIFT 6

#define	LLWU_F2_WUF15_MASK 0x80u

#define	LLWU_F2_WUF15_SHIFT 7

#define	LLWU_F3_MWUF0_MASK 0x1u

#define	LLWU_F3_MWUF0_SHIFT 0

#define	LLWU_F3_MWUF1_MASK 0x2u

#define	LLWU_F3_MWUF1_SHIFT 1

#define	LLWU_F3_MWUF2_MASK 0x4u

#define	LLWU_F3_MWUF2_SHIFT 2

#define	LLWU_F3_MWUF3_MASK 0x8u

#define	LLWU_F3_MWUF3_SHIFT 3

#define	LLWU_F3_MWUF4_MASK 0x10u

#define	LLWU_F3_MWUF4_SHIFT 4

#define	LLWU_F3_MWUF5_MASK 0x20u

#define	LLWU_F3_MWUF5_SHIFT 5

#define	LLWU_F3_MWUF6_MASK 0x40u

#define	LLWU_F3_MWUF6_SHIFT 6

#define	LLWU_F3_MWUF7_MASK 0x80u

#define	LLWU_F3_MWUF7_SHIFT 7

#define	LLWU_FILT1_FILTSEL_MASK 0xFu

#define	LLWU_FILT1_FILTSEL_SHIFT 0

#define	LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)

#define	LLWU_FILT1_FILTE_MASK 0x60u

#define	LLWU_FILT1_FILTE_SHIFT 5

#define	LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)

#define	LLWU_FILT1_FILTF_MASK 0x80u

#define	LLWU_FILT1_FILTF_SHIFT 7

#define	LLWU_FILT2_FILTSEL_MASK 0xFu

#define	LLWU_FILT2_FILTSEL_SHIFT 0

#define	LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)

#define	LLWU_FILT2_FILTE_MASK 0x60u

#define	LLWU_FILT2_FILTE_SHIFT 5

#define	LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)

#define	LLWU_FILT2_FILTF_MASK 0x80u

#define	LLWU_FILT2_FILTF_SHIFT 7

#define	LLWU_RST_RSTFILT_MASK 0x1u

#define	LLWU_RST_RSTFILT_SHIFT 0

#define	LLWU_RST_LLRSTE_MASK 0x2u

#define	LLWU_RST_LLRSTE_SHIFT 1

#define	LLWU_BASE_PTR ((LLWU_MemMapPtr)0x4007C000u)

#define	LLWU_BASE_PTRS { LLWU_BASE_PTR }

#define	LLWU_PE1 LLWU_PE1_REG(LLWU_BASE_PTR)

#define	LLWU_PE2 LLWU_PE2_REG(LLWU_BASE_PTR)

#define	LLWU_PE3 LLWU_PE3_REG(LLWU_BASE_PTR)

#define	LLWU_PE4 LLWU_PE4_REG(LLWU_BASE_PTR)

#define	LLWU_ME LLWU_ME_REG(LLWU_BASE_PTR)

#define	LLWU_F1 LLWU_F1_REG(LLWU_BASE_PTR)

#define	LLWU_F2 LLWU_F2_REG(LLWU_BASE_PTR)

#define	LLWU_F3 LLWU_F3_REG(LLWU_BASE_PTR)

#define	LLWU_FILT1 LLWU_FILT1_REG(LLWU_BASE_PTR)

#define	LLWU_FILT2 LLWU_FILT2_REG(LLWU_BASE_PTR)

#define	LLWU_RST LLWU_RST_REG(LLWU_BASE_PTR)

#define	LMEM_PCCCR_REG(base) ((base)->PCCCR)

#define	LMEM_PCCLCR_REG(base) ((base)->PCCLCR)

#define	LMEM_PCCSAR_REG(base) ((base)->PCCSAR)

#define	LMEM_PCCCVR_REG(base) ((base)->PCCCVR)

#define	LMEM_PCCRMR_REG(base) ((base)->PCCRMR)

#define	LMEM_PSCCR_REG(base) ((base)->PSCCR)

#define	LMEM_PSCLCR_REG(base) ((base)->PSCLCR)

#define	LMEM_PSCSAR_REG(base) ((base)->PSCSAR)

#define	LMEM_PSCCVR_REG(base) ((base)->PSCCVR)

#define	LMEM_PSCRMR_REG(base) ((base)->PSCRMR)

#define	LMEM_PCCCR_ENCACHE_MASK 0x1u

#define	LMEM_PCCCR_ENCACHE_SHIFT 0

#define	LMEM_PCCCR_ENWRBUF_MASK 0x2u

#define	LMEM_PCCCR_ENWRBUF_SHIFT 1

#define	LMEM_PCCCR_INVW0_MASK 0x1000000u

#define	LMEM_PCCCR_INVW0_SHIFT 24

#define	LMEM_PCCCR_PUSHW0_MASK 0x2000000u

#define	LMEM_PCCCR_PUSHW0_SHIFT 25

#define	LMEM_PCCCR_INVW1_MASK 0x4000000u

#define	LMEM_PCCCR_INVW1_SHIFT 26

#define	LMEM_PCCCR_PUSHW1_MASK 0x8000000u

#define	LMEM_PCCCR_PUSHW1_SHIFT 27

#define	LMEM_PCCCR_GO_MASK 0x80000000u

#define	LMEM_PCCCR_GO_SHIFT 31

#define	LMEM_PCCLCR_LGO_MASK 0x1u

#define	LMEM_PCCLCR_LGO_SHIFT 0

#define	LMEM_PCCLCR_CACHEADDR_MASK 0xFFCu

#define	LMEM_PCCLCR_CACHEADDR_SHIFT 2

#define	LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_CACHEADDR_SHIFT))&LMEM_PCCLCR_CACHEADDR_MASK)

#define	LMEM_PCCLCR_WSEL_MASK 0x4000u

#define	LMEM_PCCLCR_WSEL_SHIFT 14

#define	LMEM_PCCLCR_TDSEL_MASK 0x10000u

#define	LMEM_PCCLCR_TDSEL_SHIFT 16

#define	LMEM_PCCLCR_LCIVB_MASK 0x100000u

#define	LMEM_PCCLCR_LCIVB_SHIFT 20

#define	LMEM_PCCLCR_LCIMB_MASK 0x200000u

#define	LMEM_PCCLCR_LCIMB_SHIFT 21

#define	LMEM_PCCLCR_LCWAY_MASK 0x400000u

#define	LMEM_PCCLCR_LCWAY_SHIFT 22

#define	LMEM_PCCLCR_LCMD_MASK 0x3000000u

#define	LMEM_PCCLCR_LCMD_SHIFT 24

#define	LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCMD_SHIFT))&LMEM_PCCLCR_LCMD_MASK)

#define	LMEM_PCCLCR_LADSEL_MASK 0x4000000u

#define	LMEM_PCCLCR_LADSEL_SHIFT 26

#define	LMEM_PCCLCR_LACC_MASK 0x8000000u

#define	LMEM_PCCLCR_LACC_SHIFT 27

#define	LMEM_PCCSAR_LGO_MASK 0x1u

#define	LMEM_PCCSAR_LGO_SHIFT 0

#define	LMEM_PCCSAR_PHYADDR_MASK 0xFFFFFFFCu

#define	LMEM_PCCSAR_PHYADDR_SHIFT 2

#define	LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCSAR_PHYADDR_SHIFT))&LMEM_PCCSAR_PHYADDR_MASK)

#define	LMEM_PCCCVR_DATA_MASK 0xFFFFFFFFu

#define	LMEM_PCCCVR_DATA_SHIFT 0

#define	LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCVR_DATA_SHIFT))&LMEM_PCCCVR_DATA_MASK)

#define	LMEM_PCCRMR_R15_MASK 0x3u

#define	LMEM_PCCRMR_R15_SHIFT 0

#define	LMEM_PCCRMR_R15(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R15_SHIFT))&LMEM_PCCRMR_R15_MASK)

#define	LMEM_PCCRMR_R14_MASK 0xCu

#define	LMEM_PCCRMR_R14_SHIFT 2

#define	LMEM_PCCRMR_R14(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R14_SHIFT))&LMEM_PCCRMR_R14_MASK)

#define	LMEM_PCCRMR_R13_MASK 0x30u

#define	LMEM_PCCRMR_R13_SHIFT 4

#define	LMEM_PCCRMR_R13(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R13_SHIFT))&LMEM_PCCRMR_R13_MASK)

#define	LMEM_PCCRMR_R12_MASK 0xC0u

#define	LMEM_PCCRMR_R12_SHIFT 6

#define	LMEM_PCCRMR_R12(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R12_SHIFT))&LMEM_PCCRMR_R12_MASK)

#define	LMEM_PCCRMR_R11_MASK 0x300u

#define	LMEM_PCCRMR_R11_SHIFT 8

#define	LMEM_PCCRMR_R11(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R11_SHIFT))&LMEM_PCCRMR_R11_MASK)

#define	LMEM_PCCRMR_R10_MASK 0xC00u

#define	LMEM_PCCRMR_R10_SHIFT 10

#define	LMEM_PCCRMR_R10(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R10_SHIFT))&LMEM_PCCRMR_R10_MASK)

#define	LMEM_PCCRMR_R9_MASK 0x3000u

#define	LMEM_PCCRMR_R9_SHIFT 12

#define	LMEM_PCCRMR_R9(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R9_SHIFT))&LMEM_PCCRMR_R9_MASK)

#define	LMEM_PCCRMR_R8_MASK 0xC000u

#define	LMEM_PCCRMR_R8_SHIFT 14

#define	LMEM_PCCRMR_R8(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R8_SHIFT))&LMEM_PCCRMR_R8_MASK)

#define	LMEM_PCCRMR_R7_MASK 0x30000u

#define	LMEM_PCCRMR_R7_SHIFT 16

#define	LMEM_PCCRMR_R7(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R7_SHIFT))&LMEM_PCCRMR_R7_MASK)

#define	LMEM_PCCRMR_R6_MASK 0xC0000u

#define	LMEM_PCCRMR_R6_SHIFT 18

#define	LMEM_PCCRMR_R6(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R6_SHIFT))&LMEM_PCCRMR_R6_MASK)

#define	LMEM_PCCRMR_R5_MASK 0x300000u

#define	LMEM_PCCRMR_R5_SHIFT 20

#define	LMEM_PCCRMR_R5(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R5_SHIFT))&LMEM_PCCRMR_R5_MASK)

#define	LMEM_PCCRMR_R4_MASK 0xC00000u

#define	LMEM_PCCRMR_R4_SHIFT 22

#define	LMEM_PCCRMR_R4(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R4_SHIFT))&LMEM_PCCRMR_R4_MASK)

#define	LMEM_PCCRMR_R3_MASK 0x3000000u

#define	LMEM_PCCRMR_R3_SHIFT 24

#define	LMEM_PCCRMR_R3(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R3_SHIFT))&LMEM_PCCRMR_R3_MASK)

#define	LMEM_PCCRMR_R2_MASK 0xC000000u

#define	LMEM_PCCRMR_R2_SHIFT 26

#define	LMEM_PCCRMR_R2(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R2_SHIFT))&LMEM_PCCRMR_R2_MASK)

#define	LMEM_PCCRMR_R1_MASK 0x30000000u

#define	LMEM_PCCRMR_R1_SHIFT 28

#define	LMEM_PCCRMR_R1(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R1_SHIFT))&LMEM_PCCRMR_R1_MASK)

#define	LMEM_PCCRMR_R0_MASK 0xC0000000u

#define	LMEM_PCCRMR_R0_SHIFT 30

#define	LMEM_PCCRMR_R0(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R0_SHIFT))&LMEM_PCCRMR_R0_MASK)

#define	LMEM_PSCCR_ENCACHE_MASK 0x1u

#define	LMEM_PSCCR_ENCACHE_SHIFT 0

#define	LMEM_PSCCR_ENWRBUF_MASK 0x2u

#define	LMEM_PSCCR_ENWRBUF_SHIFT 1

#define	LMEM_PSCCR_INVW0_MASK 0x1000000u

#define	LMEM_PSCCR_INVW0_SHIFT 24

#define	LMEM_PSCCR_PUSHW0_MASK 0x2000000u

#define	LMEM_PSCCR_PUSHW0_SHIFT 25

#define	LMEM_PSCCR_INVW1_MASK 0x4000000u

#define	LMEM_PSCCR_INVW1_SHIFT 26

#define	LMEM_PSCCR_PUSHW1_MASK 0x8000000u

#define	LMEM_PSCCR_PUSHW1_SHIFT 27

#define	LMEM_PSCCR_GO_MASK 0x80000000u

#define	LMEM_PSCCR_GO_SHIFT 31

#define	LMEM_PSCLCR_LGO_MASK 0x1u

#define	LMEM_PSCLCR_LGO_SHIFT 0

#define	LMEM_PSCLCR_CACHEADDR_MASK 0xFFCu

#define	LMEM_PSCLCR_CACHEADDR_SHIFT 2

#define	LMEM_PSCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCLCR_CACHEADDR_SHIFT))&LMEM_PSCLCR_CACHEADDR_MASK)

#define	LMEM_PSCLCR_WSEL_MASK 0x4000u

#define	LMEM_PSCLCR_WSEL_SHIFT 14

#define	LMEM_PSCLCR_TDSEL_MASK 0x10000u

#define	LMEM_PSCLCR_TDSEL_SHIFT 16

#define	LMEM_PSCLCR_LCIVB_MASK 0x100000u

#define	LMEM_PSCLCR_LCIVB_SHIFT 20

#define	LMEM_PSCLCR_LCIMB_MASK 0x200000u

#define	LMEM_PSCLCR_LCIMB_SHIFT 21

#define	LMEM_PSCLCR_LCWAY_MASK 0x400000u

#define	LMEM_PSCLCR_LCWAY_SHIFT 22

#define	LMEM_PSCLCR_LCMD_MASK 0x3000000u

#define	LMEM_PSCLCR_LCMD_SHIFT 24

#define	LMEM_PSCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCLCR_LCMD_SHIFT))&LMEM_PSCLCR_LCMD_MASK)

#define	LMEM_PSCLCR_LADSEL_MASK 0x4000000u

#define	LMEM_PSCLCR_LADSEL_SHIFT 26

#define	LMEM_PSCLCR_LACC_MASK 0x8000000u

#define	LMEM_PSCLCR_LACC_SHIFT 27

#define	LMEM_PSCSAR_LGO_MASK 0x1u

#define	LMEM_PSCSAR_LGO_SHIFT 0

#define	LMEM_PSCSAR_PHYADDR_MASK 0xFFFFFFFCu

#define	LMEM_PSCSAR_PHYADDR_SHIFT 2

#define	LMEM_PSCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCSAR_PHYADDR_SHIFT))&LMEM_PSCSAR_PHYADDR_MASK)

#define	LMEM_PSCCVR_DATA_MASK 0xFFFFFFFFu

#define	LMEM_PSCCVR_DATA_SHIFT 0

#define	LMEM_PSCCVR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCCVR_DATA_SHIFT))&LMEM_PSCCVR_DATA_MASK)

#define	LMEM_PSCRMR_R15_MASK 0x3u

#define	LMEM_PSCRMR_R15_SHIFT 0

#define	LMEM_PSCRMR_R15(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCRMR_R15_SHIFT))&LMEM_PSCRMR_R15_MASK)

#define	LMEM_PSCRMR_R14_MASK 0xCu

#define	LMEM_PSCRMR_R14_SHIFT 2

#define	LMEM_PSCRMR_R14(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCRMR_R14_SHIFT))&LMEM_PSCRMR_R14_MASK)

#define	LMEM_PSCRMR_R13_MASK 0x30u

#define	LMEM_PSCRMR_R13_SHIFT 4

#define	LMEM_PSCRMR_R13(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCRMR_R13_SHIFT))&LMEM_PSCRMR_R13_MASK)

#define	LMEM_PSCRMR_R12_MASK 0xC0u

#define	LMEM_PSCRMR_R12_SHIFT 6

#define	LMEM_PSCRMR_R12(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCRMR_R12_SHIFT))&LMEM_PSCRMR_R12_MASK)

#define	LMEM_PSCRMR_R11_MASK 0x300u

#define	LMEM_PSCRMR_R11_SHIFT 8

#define	LMEM_PSCRMR_R11(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCRMR_R11_SHIFT))&LMEM_PSCRMR_R11_MASK)

#define	LMEM_PSCRMR_R10_MASK 0xC00u

#define	LMEM_PSCRMR_R10_SHIFT 10

#define	LMEM_PSCRMR_R10(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCRMR_R10_SHIFT))&LMEM_PSCRMR_R10_MASK)

#define	LMEM_PSCRMR_R9_MASK 0x3000u

#define	LMEM_PSCRMR_R9_SHIFT 12

#define	LMEM_PSCRMR_R9(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCRMR_R9_SHIFT))&LMEM_PSCRMR_R9_MASK)

#define	LMEM_PSCRMR_R8_MASK 0xC000u

#define	LMEM_PSCRMR_R8_SHIFT 14

#define	LMEM_PSCRMR_R8(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCRMR_R8_SHIFT))&LMEM_PSCRMR_R8_MASK)

#define	LMEM_PSCRMR_R7_MASK 0x30000u

#define	LMEM_PSCRMR_R7_SHIFT 16

#define	LMEM_PSCRMR_R7(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCRMR_R7_SHIFT))&LMEM_PSCRMR_R7_MASK)

#define	LMEM_PSCRMR_R6_MASK 0xC0000u

#define	LMEM_PSCRMR_R6_SHIFT 18

#define	LMEM_PSCRMR_R6(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCRMR_R6_SHIFT))&LMEM_PSCRMR_R6_MASK)

#define	LMEM_PSCRMR_R5_MASK 0x300000u

#define	LMEM_PSCRMR_R5_SHIFT 20

#define	LMEM_PSCRMR_R5(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCRMR_R5_SHIFT))&LMEM_PSCRMR_R5_MASK)

#define	LMEM_PSCRMR_R4_MASK 0xC00000u

#define	LMEM_PSCRMR_R4_SHIFT 22

#define	LMEM_PSCRMR_R4(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCRMR_R4_SHIFT))&LMEM_PSCRMR_R4_MASK)

#define	LMEM_PSCRMR_R3_MASK 0x3000000u

#define	LMEM_PSCRMR_R3_SHIFT 24

#define	LMEM_PSCRMR_R3(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCRMR_R3_SHIFT))&LMEM_PSCRMR_R3_MASK)

#define	LMEM_PSCRMR_R2_MASK 0xC000000u

#define	LMEM_PSCRMR_R2_SHIFT 26

#define	LMEM_PSCRMR_R2(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCRMR_R2_SHIFT))&LMEM_PSCRMR_R2_MASK)

#define	LMEM_PSCRMR_R1_MASK 0x30000000u

#define	LMEM_PSCRMR_R1_SHIFT 28

#define	LMEM_PSCRMR_R1(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCRMR_R1_SHIFT))&LMEM_PSCRMR_R1_MASK)

#define	LMEM_PSCRMR_R0_MASK 0xC0000000u

#define	LMEM_PSCRMR_R0_SHIFT 30

#define	LMEM_PSCRMR_R0(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCRMR_R0_SHIFT))&LMEM_PSCRMR_R0_MASK)

#define	LMEM_BASE_PTR ((LMEM_MemMapPtr)0xE0082000u)

#define	LMEM_BASE_PTRS { LMEM_BASE_PTR }

#define	LMEM_PCCCR LMEM_PCCCR_REG(LMEM_BASE_PTR)

#define	LMEM_PCCLCR LMEM_PCCLCR_REG(LMEM_BASE_PTR)

#define	LMEM_PCCSAR LMEM_PCCSAR_REG(LMEM_BASE_PTR)

#define	LMEM_PCCCVR LMEM_PCCCVR_REG(LMEM_BASE_PTR)

#define	LMEM_PCCRMR LMEM_PCCRMR_REG(LMEM_BASE_PTR)

#define	LMEM_PSCCR LMEM_PSCCR_REG(LMEM_BASE_PTR)

#define	LMEM_PSCLCR LMEM_PSCLCR_REG(LMEM_BASE_PTR)

#define	LMEM_PSCSAR LMEM_PSCSAR_REG(LMEM_BASE_PTR)

#define	LMEM_PSCCVR LMEM_PSCCVR_REG(LMEM_BASE_PTR)

#define	LMEM_PSCRMR LMEM_PSCRMR_REG(LMEM_BASE_PTR)

#define	LPTMR_CSR_REG(base) ((base)->CSR)

#define	LPTMR_PSR_REG(base) ((base)->PSR)

#define	LPTMR_CMR_REG(base) ((base)->CMR)

#define	LPTMR_CNR_REG(base) ((base)->CNR)

#define	LPTMR_CSR_TEN_MASK 0x1u

#define	LPTMR_CSR_TEN_SHIFT 0

#define	LPTMR_CSR_TMS_MASK 0x2u

#define	LPTMR_CSR_TMS_SHIFT 1

#define	LPTMR_CSR_TFC_MASK 0x4u

#define	LPTMR_CSR_TFC_SHIFT 2

#define	LPTMR_CSR_TPP_MASK 0x8u

#define	LPTMR_CSR_TPP_SHIFT 3

#define	LPTMR_CSR_TPS_MASK 0x30u

#define	LPTMR_CSR_TPS_SHIFT 4

#define	LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)

#define	LPTMR_CSR_TIE_MASK 0x40u

#define	LPTMR_CSR_TIE_SHIFT 6

#define	LPTMR_CSR_TCF_MASK 0x80u

#define	LPTMR_CSR_TCF_SHIFT 7

#define	LPTMR_PSR_PCS_MASK 0x3u

#define	LPTMR_PSR_PCS_SHIFT 0

#define	LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)

#define	LPTMR_PSR_PBYP_MASK 0x4u

#define	LPTMR_PSR_PBYP_SHIFT 2

#define	LPTMR_PSR_PRESCALE_MASK 0x78u

#define	LPTMR_PSR_PRESCALE_SHIFT 3

#define	LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)

#define	LPTMR_CMR_COMPARE_MASK 0xFFFFu

#define	LPTMR_CMR_COMPARE_SHIFT 0

#define	LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)

#define	LPTMR_CNR_COUNTER_MASK 0xFFFFu

#define	LPTMR_CNR_COUNTER_SHIFT 0

#define	LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)

#define	LPTMR0_BASE_PTR ((LPTMR_MemMapPtr)0x40040000u)

#define	LPTMR_BASE_PTRS { LPTMR0_BASE_PTR }

#define	LPTMR0_CSR LPTMR_CSR_REG(LPTMR0_BASE_PTR)

#define	LPTMR0_PSR LPTMR_PSR_REG(LPTMR0_BASE_PTR)

#define	LPTMR0_CMR LPTMR_CMR_REG(LPTMR0_BASE_PTR)

#define	LPTMR0_CNR LPTMR_CNR_REG(LPTMR0_BASE_PTR)

#define	MCG_C1_REG(base) ((base)->C1)

#define	MCG_C2_REG(base) ((base)->C2)

#define	MCG_C3_REG(base) ((base)->C3)

#define	MCG_C4_REG(base) ((base)->C4)

#define	MCG_C5_REG(base) ((base)->C5)

#define	MCG_C6_REG(base) ((base)->C6)

#define	MCG_S_REG(base) ((base)->S)

#define	MCG_SC_REG(base) ((base)->SC)

#define	MCG_ATCVH_REG(base) ((base)->ATCVH)

#define	MCG_ATCVL_REG(base) ((base)->ATCVL)

#define	MCG_C7_REG(base) ((base)->C7)

#define	MCG_C8_REG(base) ((base)->C8)

#define	MCG_C10_REG(base) ((base)->C10)

#define	MCG_C11_REG(base) ((base)->C11)

#define	MCG_C12_REG(base) ((base)->C12)

#define	MCG_S2_REG(base) ((base)->S2)

#define	MCG_C1_IREFSTEN_MASK 0x1u

#define	MCG_C1_IREFSTEN_SHIFT 0

#define	MCG_C1_IRCLKEN_MASK 0x2u

#define	MCG_C1_IRCLKEN_SHIFT 1

#define	MCG_C1_IREFS_MASK 0x4u

#define	MCG_C1_IREFS_SHIFT 2

#define	MCG_C1_FRDIV_MASK 0x38u

#define	MCG_C1_FRDIV_SHIFT 3

#define	MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)

#define	MCG_C1_CLKS_MASK 0xC0u

#define	MCG_C1_CLKS_SHIFT 6

#define	MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)

#define	MCG_C2_IRCS_MASK 0x1u

#define	MCG_C2_IRCS_SHIFT 0

#define	MCG_C2_LP_MASK 0x2u

#define	MCG_C2_LP_SHIFT 1

#define	MCG_C2_EREFS0_MASK 0x4u

#define	MCG_C2_EREFS0_SHIFT 2

#define	MCG_C2_HGO0_MASK 0x8u

#define	MCG_C2_HGO0_SHIFT 3

#define	MCG_C2_RANGE0_MASK 0x30u

#define	MCG_C2_RANGE0_SHIFT 4

#define	MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)

#define	MCG_C2_LOCRE0_MASK 0x80u

#define	MCG_C2_LOCRE0_SHIFT 7

#define	MCG_C3_SCTRIM_MASK 0xFFu

#define	MCG_C3_SCTRIM_SHIFT 0

#define	MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)

#define	MCG_C4_SCFTRIM_MASK 0x1u

#define	MCG_C4_SCFTRIM_SHIFT 0

#define	MCG_C4_FCTRIM_MASK 0x1Eu

#define	MCG_C4_FCTRIM_SHIFT 1

#define	MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)

#define	MCG_C4_DRST_DRS_MASK 0x60u

#define	MCG_C4_DRST_DRS_SHIFT 5

#define	MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)

#define	MCG_C4_DMX32_MASK 0x80u

#define	MCG_C4_DMX32_SHIFT 7

#define	MCG_C5_PRDIV0_MASK 0x7u

#define	MCG_C5_PRDIV0_SHIFT 0

#define	MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)

#define	MCG_C5_PLLSTEN0_MASK 0x20u

#define	MCG_C5_PLLSTEN0_SHIFT 5

#define	MCG_C5_PLLCLKEN0_MASK 0x40u

#define	MCG_C5_PLLCLKEN0_SHIFT 6

#define	MCG_C5_PLLREFSEL0_MASK 0x80u

#define	MCG_C5_PLLREFSEL0_SHIFT 7

#define	MCG_C6_VDIV0_MASK 0x1Fu

#define	MCG_C6_VDIV0_SHIFT 0

#define	MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)

#define	MCG_C6_CME0_MASK 0x20u

#define	MCG_C6_CME0_SHIFT 5

#define	MCG_C6_PLLS_MASK 0x40u

#define	MCG_C6_PLLS_SHIFT 6

#define	MCG_C6_LOLIE0_MASK 0x80u

#define	MCG_C6_LOLIE0_SHIFT 7

#define	MCG_S_IRCST_MASK 0x1u

#define	MCG_S_IRCST_SHIFT 0

#define	MCG_S_OSCINIT0_MASK 0x2u

#define	MCG_S_OSCINIT0_SHIFT 1

#define	MCG_S_CLKST_MASK 0xCu

#define	MCG_S_CLKST_SHIFT 2

#define	MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)

#define	MCG_S_IREFST_MASK 0x10u

#define	MCG_S_IREFST_SHIFT 4

#define	MCG_S_PLLST_MASK 0x20u

#define	MCG_S_PLLST_SHIFT 5

#define	MCG_S_LOCK0_MASK 0x40u

#define	MCG_S_LOCK0_SHIFT 6

#define	MCG_S_LOLS0_MASK 0x80u

#define	MCG_S_LOLS0_SHIFT 7

#define	MCG_SC_LOCS0_MASK 0x1u

#define	MCG_SC_LOCS0_SHIFT 0

#define	MCG_SC_FCRDIV_MASK 0xEu

#define	MCG_SC_FCRDIV_SHIFT 1

#define	MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)

#define	MCG_SC_FLTPRSRV_MASK 0x10u

#define	MCG_SC_FLTPRSRV_SHIFT 4

#define	MCG_SC_ATMF_MASK 0x20u

#define	MCG_SC_ATMF_SHIFT 5

#define	MCG_SC_ATMS_MASK 0x40u

#define	MCG_SC_ATMS_SHIFT 6

#define	MCG_SC_ATME_MASK 0x80u

#define	MCG_SC_ATME_SHIFT 7

#define	MCG_ATCVH_ATCVH_MASK 0xFFu

#define	MCG_ATCVH_ATCVH_SHIFT 0

#define	MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)

#define	MCG_ATCVL_ATCVL_MASK 0xFFu

#define	MCG_ATCVL_ATCVL_SHIFT 0

#define	MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)

#define	MCG_C7_OSCSEL_MASK 0x1u

#define	MCG_C7_OSCSEL_SHIFT 0

#define	MCG_C8_LOCS1_MASK 0x1u

#define	MCG_C8_LOCS1_SHIFT 0

#define	MCG_C8_CME1_MASK 0x20u

#define	MCG_C8_CME1_SHIFT 5

#define	MCG_C8_LOCRE1_MASK 0x80u

#define	MCG_C8_LOCRE1_SHIFT 7

#define	MCG_C10_EREFS1_MASK 0x4u

#define	MCG_C10_EREFS1_SHIFT 2

#define	MCG_C10_HGO1_MASK 0x8u

#define	MCG_C10_HGO1_SHIFT 3

#define	MCG_C10_RANGE1_MASK 0x30u

#define	MCG_C10_RANGE1_SHIFT 4

#define	MCG_C10_RANGE1(x) (((uint8_t)(((uint8_t)(x))<<MCG_C10_RANGE1_SHIFT))&MCG_C10_RANGE1_MASK)

#define	MCG_C10_LOCRE2_MASK 0x80u

#define	MCG_C10_LOCRE2_SHIFT 7

#define	MCG_C11_PRDIV1_MASK 0x7u

#define	MCG_C11_PRDIV1_SHIFT 0

#define	MCG_C11_PRDIV1(x) (((uint8_t)(((uint8_t)(x))<<MCG_C11_PRDIV1_SHIFT))&MCG_C11_PRDIV1_MASK)

#define	MCG_C11_PLLCS_MASK 0x10u

#define	MCG_C11_PLLCS_SHIFT 4

#define	MCG_C11_PLLSTEN1_MASK 0x20u

#define	MCG_C11_PLLSTEN1_SHIFT 5

#define	MCG_C11_PLLCLKEN1_MASK 0x40u

#define	MCG_C11_PLLCLKEN1_SHIFT 6

#define	MCG_C11_PLLREFSEL1_MASK 0x80u

#define	MCG_C11_PLLREFSEL1_SHIFT 7

#define	MCG_C12_VDIV1_MASK 0x1Fu

#define	MCG_C12_VDIV1_SHIFT 0

#define	MCG_C12_VDIV1(x) (((uint8_t)(((uint8_t)(x))<<MCG_C12_VDIV1_SHIFT))&MCG_C12_VDIV1_MASK)

#define	MCG_C12_CME2_MASK 0x20u

#define	MCG_C12_CME2_SHIFT 5

#define	MCG_C12_LOLIE1_MASK 0x80u

#define	MCG_C12_LOLIE1_SHIFT 7

#define	MCG_S2_LOCS2_MASK 0x1u

#define	MCG_S2_LOCS2_SHIFT 0

#define	MCG_S2_OSCINIT1_MASK 0x2u

#define	MCG_S2_OSCINIT1_SHIFT 1

#define	MCG_S2_PLLCST_MASK 0x10u

#define	MCG_S2_PLLCST_SHIFT 4

#define	MCG_S2_LOCK1_MASK 0x40u

#define	MCG_S2_LOCK1_SHIFT 6

#define	MCG_S2_LOLS1_MASK 0x80u

#define	MCG_S2_LOLS1_SHIFT 7

#define	MCG_BASE_PTR ((MCG_MemMapPtr)0x40064000u)

#define	MCG_BASE_PTRS { MCG_BASE_PTR }

#define	MCG_C1 MCG_C1_REG(MCG_BASE_PTR)

#define	MCG_C2 MCG_C2_REG(MCG_BASE_PTR)

#define	MCG_C3 MCG_C3_REG(MCG_BASE_PTR)

#define	MCG_C4 MCG_C4_REG(MCG_BASE_PTR)

#define	MCG_C5 MCG_C5_REG(MCG_BASE_PTR)

#define	MCG_C6 MCG_C6_REG(MCG_BASE_PTR)

#define	MCG_S MCG_S_REG(MCG_BASE_PTR)

#define	MCG_SC MCG_SC_REG(MCG_BASE_PTR)

#define	MCG_ATCVH MCG_ATCVH_REG(MCG_BASE_PTR)

#define	MCG_ATCVL MCG_ATCVL_REG(MCG_BASE_PTR)

#define	MCG_C7 MCG_C7_REG(MCG_BASE_PTR)

#define	MCG_C8 MCG_C8_REG(MCG_BASE_PTR)

#define	MCG_C10 MCG_C10_REG(MCG_BASE_PTR)

#define	MCG_C11 MCG_C11_REG(MCG_BASE_PTR)

#define	MCG_C12 MCG_C12_REG(MCG_BASE_PTR)

#define	MCG_S2 MCG_S2_REG(MCG_BASE_PTR)

#define	MCM_PLASC_REG(base) ((base)->PLASC)

#define	MCM_PLAMC_REG(base) ((base)->PLAMC)

#define	MCM_CR_REG(base) ((base)->CR)

#define	MCM_ISCR_REG(base) ((base)->ISCR)

#define	MCM_ETBCC_REG(base) ((base)->ETBCC)

#define	MCM_ETBRL_REG(base) ((base)->ETBRL)

#define	MCM_ETBCNT_REG(base) ((base)->ETBCNT)

#define	MCM_FADR_REG(base) ((base)->FADR)

#define	MCM_FATR_REG(base) ((base)->FATR)

#define	MCM_FDR_REG(base) ((base)->FDR)

#define	MCM_PID_REG(base) ((base)->PID)

#define	MCM_PLASC_ASC_MASK 0xFFu

#define	MCM_PLASC_ASC_SHIFT 0

#define	MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)

#define	MCM_PLAMC_AMC_MASK 0xFFu

#define	MCM_PLAMC_AMC_SHIFT 0

#define	MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)

#define	MCM_CR_DDRSIZE_MASK 0x300000u

#define	MCM_CR_DDRSIZE_SHIFT 20

#define	MCM_CR_DDRSIZE(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_DDRSIZE_SHIFT))&MCM_CR_DDRSIZE_MASK)

#define	MCM_CR_SRAMUAP_MASK 0x3000000u

#define	MCM_CR_SRAMUAP_SHIFT 24

#define	MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)

#define	MCM_CR_SRAMUWP_MASK 0x4000000u

#define	MCM_CR_SRAMUWP_SHIFT 26

#define	MCM_CR_SRAMLAP_MASK 0x30000000u

#define	MCM_CR_SRAMLAP_SHIFT 28

#define	MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)

#define	MCM_CR_SRAMLWP_MASK 0x40000000u

#define	MCM_CR_SRAMLWP_SHIFT 30

#define	MCM_ISCR_IRQ_MASK 0x2u

#define	MCM_ISCR_IRQ_SHIFT 1

#define	MCM_ISCR_NMI_MASK 0x4u

#define	MCM_ISCR_NMI_SHIFT 2

#define	MCM_ISCR_DHREQ_MASK 0x8u

#define	MCM_ISCR_DHREQ_SHIFT 3

#define	MCM_ISCR_CWBER_MASK 0x10u

#define	MCM_ISCR_CWBER_SHIFT 4

#define	MCM_ISCR_FIOC_MASK 0x100u

#define	MCM_ISCR_FIOC_SHIFT 8

#define	MCM_ISCR_FDZC_MASK 0x200u

#define	MCM_ISCR_FDZC_SHIFT 9

#define	MCM_ISCR_FOFC_MASK 0x400u

#define	MCM_ISCR_FOFC_SHIFT 10

#define	MCM_ISCR_FUFC_MASK 0x800u

#define	MCM_ISCR_FUFC_SHIFT 11

#define	MCM_ISCR_FIXC_MASK 0x1000u

#define	MCM_ISCR_FIXC_SHIFT 12

#define	MCM_ISCR_FIDC_MASK 0x8000u

#define	MCM_ISCR_FIDC_SHIFT 15

#define	MCM_ISCR_CWBEE_MASK 0x100000u

#define	MCM_ISCR_CWBEE_SHIFT 20

#define	MCM_ISCR_FIOCE_MASK 0x1000000u

#define	MCM_ISCR_FIOCE_SHIFT 24

#define	MCM_ISCR_FDZCE_MASK 0x2000000u

#define	MCM_ISCR_FDZCE_SHIFT 25

#define	MCM_ISCR_FOFCE_MASK 0x4000000u

#define	MCM_ISCR_FOFCE_SHIFT 26

#define	MCM_ISCR_FUFCE_MASK 0x8000000u

#define	MCM_ISCR_FUFCE_SHIFT 27

#define	MCM_ISCR_FIXCE_MASK 0x10000000u

#define	MCM_ISCR_FIXCE_SHIFT 28

#define	MCM_ISCR_FIDCE_MASK 0x80000000u

#define	MCM_ISCR_FIDCE_SHIFT 31

#define	MCM_ETBCC_CNTEN_MASK 0x1u

#define	MCM_ETBCC_CNTEN_SHIFT 0

#define	MCM_ETBCC_RSPT_MASK 0x6u

#define	MCM_ETBCC_RSPT_SHIFT 1

#define	MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)

#define	MCM_ETBCC_RLRQ_MASK 0x8u

#define	MCM_ETBCC_RLRQ_SHIFT 3

#define	MCM_ETBCC_ETDIS_MASK 0x10u

#define	MCM_ETBCC_ETDIS_SHIFT 4

#define	MCM_ETBCC_ITDIS_MASK 0x20u

#define	MCM_ETBCC_ITDIS_SHIFT 5

#define	MCM_ETBRL_RELOAD_MASK 0x7FFu

#define	MCM_ETBRL_RELOAD_SHIFT 0

#define	MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)

#define	MCM_ETBCNT_COUNTER_MASK 0x7FFu

#define	MCM_ETBCNT_COUNTER_SHIFT 0

#define	MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)

#define	MCM_FADR_ADDRESS_MASK 0xFFFFFFFFu

#define	MCM_FADR_ADDRESS_SHIFT 0

#define	MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<MCM_FADR_ADDRESS_SHIFT))&MCM_FADR_ADDRESS_MASK)

#define	MCM_FATR_BEDA_MASK 0x1u

#define	MCM_FATR_BEDA_SHIFT 0

#define	MCM_FATR_BEMD_MASK 0x2u

#define	MCM_FATR_BEMD_SHIFT 1

#define	MCM_FATR_BESZ_MASK 0x30u

#define	MCM_FATR_BESZ_SHIFT 4

#define	MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x))<<MCM_FATR_BESZ_SHIFT))&MCM_FATR_BESZ_MASK)

#define	MCM_FATR_BEWT_MASK 0x80u

#define	MCM_FATR_BEWT_SHIFT 7

#define	MCM_FATR_BEMN_MASK 0xF00u

#define	MCM_FATR_BEMN_SHIFT 8

#define	MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x))<<MCM_FATR_BEMN_SHIFT))&MCM_FATR_BEMN_MASK)

#define	MCM_FATR_BEOVR_MASK 0x80000000u

#define	MCM_FATR_BEOVR_SHIFT 31

#define	MCM_FDR_DATA_MASK 0xFFFFFFFFu

#define	MCM_FDR_DATA_SHIFT 0

#define	MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<MCM_FDR_DATA_SHIFT))&MCM_FDR_DATA_MASK)

#define	MCM_PID_PID_MASK 0xFFu

#define	MCM_PID_PID_SHIFT 0

#define	MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)

#define	MCM_BASE_PTR ((MCM_MemMapPtr)0xE0080000u)

#define	MCM_BASE_PTRS { MCM_BASE_PTR }

#define	MCM_PLASC MCM_PLASC_REG(MCM_BASE_PTR)

#define	MCM_PLAMC MCM_PLAMC_REG(MCM_BASE_PTR)

#define	MCM_CR MCM_CR_REG(MCM_BASE_PTR)

#define	MCM_ISCR MCM_ISCR_REG(MCM_BASE_PTR)

#define	MCM_ETBCC MCM_ETBCC_REG(MCM_BASE_PTR)

#define	MCM_ETBRL MCM_ETBRL_REG(MCM_BASE_PTR)

#define	MCM_ETBCNT MCM_ETBCNT_REG(MCM_BASE_PTR)

#define	MCM_FADR MCM_FADR_REG(MCM_BASE_PTR)

#define	MCM_FATR MCM_FATR_REG(MCM_BASE_PTR)

#define	MCM_FDR MCM_FDR_REG(MCM_BASE_PTR)

#define	MCM_PID MCM_PID_REG(MCM_BASE_PTR)

#define	MPU_CESR_REG(base) ((base)->CESR)

#define	MPU_EAR_REG(base, index) ((base)->SP[index].EAR)

#define	MPU_EDR_REG(base, index) ((base)->SP[index].EDR)

#define	MPU_WORD_REG(base, index, index2) ((base)->WORD[index][index2])

#define	MPU_RGDAAC_REG(base, index) ((base)->RGDAAC[index])

#define	MPU_CESR_VLD_MASK 0x1u

#define	MPU_CESR_VLD_SHIFT 0

#define	MPU_CESR_NRGD_MASK 0xF00u

#define	MPU_CESR_NRGD_SHIFT 8

#define	MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)

#define	MPU_CESR_NSP_MASK 0xF000u

#define	MPU_CESR_NSP_SHIFT 12

#define	MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)

#define	MPU_CESR_HRL_MASK 0xF0000u

#define	MPU_CESR_HRL_SHIFT 16

#define	MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)

#define	MPU_CESR_SPERR_MASK 0xFF000000u

#define	MPU_CESR_SPERR_SHIFT 24

#define	MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)

#define	MPU_EAR_EADDR_MASK 0xFFFFFFFFu

#define	MPU_EAR_EADDR_SHIFT 0

#define	MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)

#define	MPU_EDR_ERW_MASK 0x1u

#define	MPU_EDR_ERW_SHIFT 0

#define	MPU_EDR_EATTR_MASK 0xEu

#define	MPU_EDR_EATTR_SHIFT 1

#define	MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)

#define	MPU_EDR_EMN_MASK 0xF0u

#define	MPU_EDR_EMN_SHIFT 4

#define	MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)

#define	MPU_EDR_EPID_MASK 0xFF00u

#define	MPU_EDR_EPID_SHIFT 8

#define	MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)

#define	MPU_EDR_EACD_MASK 0xFFFF0000u

#define	MPU_EDR_EACD_SHIFT 16

#define	MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)

#define	MPU_WORD_VLD_MASK 0x1u

#define	MPU_WORD_VLD_SHIFT 0

#define	MPU_WORD_M0UM_MASK 0x7u

#define	MPU_WORD_M0UM_SHIFT 0

#define	MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)

#define	MPU_WORD_M0SM_MASK 0x18u

#define	MPU_WORD_M0SM_SHIFT 3

#define	MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)

#define	MPU_WORD_M0PE_MASK 0x20u

#define	MPU_WORD_M0PE_SHIFT 5

#define	MPU_WORD_ENDADDR_MASK 0xFFFFFFE0u

#define	MPU_WORD_ENDADDR_SHIFT 5

#define	MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)

#define	MPU_WORD_SRTADDR_MASK 0xFFFFFFE0u

#define	MPU_WORD_SRTADDR_SHIFT 5

#define	MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)

#define	MPU_WORD_M1UM_MASK 0x1C0u

#define	MPU_WORD_M1UM_SHIFT 6

#define	MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)

#define	MPU_WORD_M1SM_MASK 0x600u

#define	MPU_WORD_M1SM_SHIFT 9

#define	MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)

#define	MPU_WORD_M1PE_MASK 0x800u

#define	MPU_WORD_M1PE_SHIFT 11

#define	MPU_WORD_M2UM_MASK 0x7000u

#define	MPU_WORD_M2UM_SHIFT 12

#define	MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)

#define	MPU_WORD_M2SM_MASK 0x18000u

#define	MPU_WORD_M2SM_SHIFT 15

#define	MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)

#define	MPU_WORD_PIDMASK_MASK 0xFF0000u

#define	MPU_WORD_PIDMASK_SHIFT 16

#define	MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)

#define	MPU_WORD_M2PE_MASK 0x20000u

#define	MPU_WORD_M2PE_SHIFT 17

#define	MPU_WORD_M3UM_MASK 0x1C0000u

#define	MPU_WORD_M3UM_SHIFT 18

#define	MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)

#define	MPU_WORD_M3SM_MASK 0x600000u

#define	MPU_WORD_M3SM_SHIFT 21

#define	MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)

#define	MPU_WORD_M3PE_MASK 0x800000u

#define	MPU_WORD_M3PE_SHIFT 23

#define	MPU_WORD_PID_MASK 0xFF000000u

#define	MPU_WORD_PID_SHIFT 24

#define	MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)

#define	MPU_WORD_M4WE_MASK 0x1000000u

#define	MPU_WORD_M4WE_SHIFT 24

#define	MPU_WORD_M4RE_MASK 0x2000000u

#define	MPU_WORD_M4RE_SHIFT 25

#define	MPU_WORD_M5WE_MASK 0x4000000u

#define	MPU_WORD_M5WE_SHIFT 26

#define	MPU_WORD_M5RE_MASK 0x8000000u

#define	MPU_WORD_M5RE_SHIFT 27

#define	MPU_WORD_M6WE_MASK 0x10000000u

#define	MPU_WORD_M6WE_SHIFT 28

#define	MPU_WORD_M6RE_MASK 0x20000000u

#define	MPU_WORD_M6RE_SHIFT 29

#define	MPU_WORD_M7WE_MASK 0x40000000u

#define	MPU_WORD_M7WE_SHIFT 30

#define	MPU_WORD_M7RE_MASK 0x80000000u

#define	MPU_WORD_M7RE_SHIFT 31

#define	MPU_RGDAAC_M0UM_MASK 0x7u

#define	MPU_RGDAAC_M0UM_SHIFT 0

#define	MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)

#define	MPU_RGDAAC_M0SM_MASK 0x18u

#define	MPU_RGDAAC_M0SM_SHIFT 3

#define	MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)

#define	MPU_RGDAAC_M0PE_MASK 0x20u

#define	MPU_RGDAAC_M0PE_SHIFT 5

#define	MPU_RGDAAC_M1UM_MASK 0x1C0u

#define	MPU_RGDAAC_M1UM_SHIFT 6

#define	MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)

#define	MPU_RGDAAC_M1SM_MASK 0x600u

#define	MPU_RGDAAC_M1SM_SHIFT 9

#define	MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)

#define	MPU_RGDAAC_M1PE_MASK 0x800u

#define	MPU_RGDAAC_M1PE_SHIFT 11

#define	MPU_RGDAAC_M2UM_MASK 0x7000u

#define	MPU_RGDAAC_M2UM_SHIFT 12

#define	MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)

#define	MPU_RGDAAC_M2SM_MASK 0x18000u

#define	MPU_RGDAAC_M2SM_SHIFT 15

#define	MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)

#define	MPU_RGDAAC_M2PE_MASK 0x20000u

#define	MPU_RGDAAC_M2PE_SHIFT 17

#define	MPU_RGDAAC_M3UM_MASK 0x1C0000u

#define	MPU_RGDAAC_M3UM_SHIFT 18

#define	MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)

#define	MPU_RGDAAC_M3SM_MASK 0x600000u

#define	MPU_RGDAAC_M3SM_SHIFT 21

#define	MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)

#define	MPU_RGDAAC_M3PE_MASK 0x800000u

#define	MPU_RGDAAC_M3PE_SHIFT 23

#define	MPU_RGDAAC_M4WE_MASK 0x1000000u

#define	MPU_RGDAAC_M4WE_SHIFT 24

#define	MPU_RGDAAC_M4RE_MASK 0x2000000u

#define	MPU_RGDAAC_M4RE_SHIFT 25

#define	MPU_RGDAAC_M5WE_MASK 0x4000000u

#define	MPU_RGDAAC_M5WE_SHIFT 26

#define	MPU_RGDAAC_M5RE_MASK 0x8000000u

#define	MPU_RGDAAC_M5RE_SHIFT 27

#define	MPU_RGDAAC_M6WE_MASK 0x10000000u

#define	MPU_RGDAAC_M6WE_SHIFT 28

#define	MPU_RGDAAC_M6RE_MASK 0x20000000u

#define	MPU_RGDAAC_M6RE_SHIFT 29

#define	MPU_RGDAAC_M7WE_MASK 0x40000000u

#define	MPU_RGDAAC_M7WE_SHIFT 30

#define	MPU_RGDAAC_M7RE_MASK 0x80000000u

#define	MPU_RGDAAC_M7RE_SHIFT 31

#define	MPU_BASE_PTR ((MPU_MemMapPtr)0x4000D000u)

#define	MPU_BASE_PTRS { MPU_BASE_PTR }

#define	MPU_CESR MPU_CESR_REG(MPU_BASE_PTR)

#define	MPU_EAR0 MPU_EAR_REG(MPU_BASE_PTR,0)

#define	MPU_EDR0 MPU_EDR_REG(MPU_BASE_PTR,0)

#define	MPU_EAR1 MPU_EAR_REG(MPU_BASE_PTR,1)

#define	MPU_EDR1 MPU_EDR_REG(MPU_BASE_PTR,1)

#define	MPU_EAR2 MPU_EAR_REG(MPU_BASE_PTR,2)

#define	MPU_EDR2 MPU_EDR_REG(MPU_BASE_PTR,2)

#define	MPU_EAR3 MPU_EAR_REG(MPU_BASE_PTR,3)

#define	MPU_EDR3 MPU_EDR_REG(MPU_BASE_PTR,3)

#define	MPU_EAR4 MPU_EAR_REG(MPU_BASE_PTR,4)

#define	MPU_EDR4 MPU_EDR_REG(MPU_BASE_PTR,4)

#define	MPU_RGD0_WORD0 MPU_WORD_REG(MPU_BASE_PTR,0,0)

#define	MPU_RGD0_WORD1 MPU_WORD_REG(MPU_BASE_PTR,0,1)

#define	MPU_RGD0_WORD2 MPU_WORD_REG(MPU_BASE_PTR,0,2)

#define	MPU_RGD0_WORD3 MPU_WORD_REG(MPU_BASE_PTR,0,3)

#define	MPU_RGD1_WORD0 MPU_WORD_REG(MPU_BASE_PTR,1,0)

#define	MPU_RGD1_WORD1 MPU_WORD_REG(MPU_BASE_PTR,1,1)

#define	MPU_RGD1_WORD2 MPU_WORD_REG(MPU_BASE_PTR,1,2)

#define	MPU_RGD1_WORD3 MPU_WORD_REG(MPU_BASE_PTR,1,3)

#define	MPU_RGD2_WORD0 MPU_WORD_REG(MPU_BASE_PTR,2,0)

#define	MPU_RGD2_WORD1 MPU_WORD_REG(MPU_BASE_PTR,2,1)

#define	MPU_RGD2_WORD2 MPU_WORD_REG(MPU_BASE_PTR,2,2)

#define	MPU_RGD2_WORD3 MPU_WORD_REG(MPU_BASE_PTR,2,3)

#define	MPU_RGD3_WORD0 MPU_WORD_REG(MPU_BASE_PTR,3,0)

#define	MPU_RGD3_WORD1 MPU_WORD_REG(MPU_BASE_PTR,3,1)

#define	MPU_RGD3_WORD2 MPU_WORD_REG(MPU_BASE_PTR,3,2)

#define	MPU_RGD3_WORD3 MPU_WORD_REG(MPU_BASE_PTR,3,3)

#define	MPU_RGD4_WORD0 MPU_WORD_REG(MPU_BASE_PTR,4,0)

#define	MPU_RGD4_WORD1 MPU_WORD_REG(MPU_BASE_PTR,4,1)

#define	MPU_RGD4_WORD2 MPU_WORD_REG(MPU_BASE_PTR,4,2)

#define	MPU_RGD4_WORD3 MPU_WORD_REG(MPU_BASE_PTR,4,3)

#define	MPU_RGD5_WORD0 MPU_WORD_REG(MPU_BASE_PTR,5,0)

#define	MPU_RGD5_WORD1 MPU_WORD_REG(MPU_BASE_PTR,5,1)

#define	MPU_RGD5_WORD2 MPU_WORD_REG(MPU_BASE_PTR,5,2)

#define	MPU_RGD5_WORD3 MPU_WORD_REG(MPU_BASE_PTR,5,3)

#define	MPU_RGD6_WORD0 MPU_WORD_REG(MPU_BASE_PTR,6,0)

#define	MPU_RGD6_WORD1 MPU_WORD_REG(MPU_BASE_PTR,6,1)

#define	MPU_RGD6_WORD2 MPU_WORD_REG(MPU_BASE_PTR,6,2)

#define	MPU_RGD6_WORD3 MPU_WORD_REG(MPU_BASE_PTR,6,3)

#define	MPU_RGD7_WORD0 MPU_WORD_REG(MPU_BASE_PTR,7,0)

#define	MPU_RGD7_WORD1 MPU_WORD_REG(MPU_BASE_PTR,7,1)

#define	MPU_RGD7_WORD2 MPU_WORD_REG(MPU_BASE_PTR,7,2)

#define	MPU_RGD7_WORD3 MPU_WORD_REG(MPU_BASE_PTR,7,3)

#define	MPU_RGD8_WORD0 MPU_WORD_REG(MPU_BASE_PTR,8,0)

#define	MPU_RGD8_WORD1 MPU_WORD_REG(MPU_BASE_PTR,8,1)

#define	MPU_RGD8_WORD2 MPU_WORD_REG(MPU_BASE_PTR,8,2)

#define	MPU_RGD8_WORD3 MPU_WORD_REG(MPU_BASE_PTR,8,3)

#define	MPU_RGD9_WORD0 MPU_WORD_REG(MPU_BASE_PTR,9,0)

#define	MPU_RGD9_WORD1 MPU_WORD_REG(MPU_BASE_PTR,9,1)

#define	MPU_RGD9_WORD2 MPU_WORD_REG(MPU_BASE_PTR,9,2)

#define	MPU_RGD9_WORD3 MPU_WORD_REG(MPU_BASE_PTR,9,3)

#define	MPU_RGD10_WORD0 MPU_WORD_REG(MPU_BASE_PTR,10,0)

#define	MPU_RGD10_WORD1 MPU_WORD_REG(MPU_BASE_PTR,10,1)

#define	MPU_RGD10_WORD2 MPU_WORD_REG(MPU_BASE_PTR,10,2)

#define	MPU_RGD10_WORD3 MPU_WORD_REG(MPU_BASE_PTR,10,3)

#define	MPU_RGD11_WORD0 MPU_WORD_REG(MPU_BASE_PTR,11,0)

#define	MPU_RGD11_WORD1 MPU_WORD_REG(MPU_BASE_PTR,11,1)

#define	MPU_RGD11_WORD2 MPU_WORD_REG(MPU_BASE_PTR,11,2)

#define	MPU_RGD11_WORD3 MPU_WORD_REG(MPU_BASE_PTR,11,3)

#define	MPU_RGD12_WORD0 MPU_WORD_REG(MPU_BASE_PTR,12,0)

#define	MPU_RGD12_WORD1 MPU_WORD_REG(MPU_BASE_PTR,12,1)

#define	MPU_RGD12_WORD2 MPU_WORD_REG(MPU_BASE_PTR,12,2)

#define	MPU_RGD12_WORD3 MPU_WORD_REG(MPU_BASE_PTR,12,3)

#define	MPU_RGD13_WORD0 MPU_WORD_REG(MPU_BASE_PTR,13,0)

#define	MPU_RGD13_WORD1 MPU_WORD_REG(MPU_BASE_PTR,13,1)

#define	MPU_RGD13_WORD2 MPU_WORD_REG(MPU_BASE_PTR,13,2)

#define	MPU_RGD13_WORD3 MPU_WORD_REG(MPU_BASE_PTR,13,3)

#define	MPU_RGD14_WORD0 MPU_WORD_REG(MPU_BASE_PTR,14,0)

#define	MPU_RGD14_WORD1 MPU_WORD_REG(MPU_BASE_PTR,14,1)

#define	MPU_RGD14_WORD2 MPU_WORD_REG(MPU_BASE_PTR,14,2)

#define	MPU_RGD14_WORD3 MPU_WORD_REG(MPU_BASE_PTR,14,3)

#define	MPU_RGD15_WORD0 MPU_WORD_REG(MPU_BASE_PTR,15,0)

#define	MPU_RGD15_WORD1 MPU_WORD_REG(MPU_BASE_PTR,15,1)

#define	MPU_RGD15_WORD2 MPU_WORD_REG(MPU_BASE_PTR,15,2)

#define	MPU_RGD15_WORD3 MPU_WORD_REG(MPU_BASE_PTR,15,3)

#define	MPU_RGDAAC0 MPU_RGDAAC_REG(MPU_BASE_PTR,0)

#define	MPU_RGDAAC1 MPU_RGDAAC_REG(MPU_BASE_PTR,1)

#define	MPU_RGDAAC2 MPU_RGDAAC_REG(MPU_BASE_PTR,2)

#define	MPU_RGDAAC3 MPU_RGDAAC_REG(MPU_BASE_PTR,3)

#define	MPU_RGDAAC4 MPU_RGDAAC_REG(MPU_BASE_PTR,4)

#define	MPU_RGDAAC5 MPU_RGDAAC_REG(MPU_BASE_PTR,5)

#define	MPU_RGDAAC6 MPU_RGDAAC_REG(MPU_BASE_PTR,6)

#define	MPU_RGDAAC7 MPU_RGDAAC_REG(MPU_BASE_PTR,7)

#define	MPU_RGDAAC8 MPU_RGDAAC_REG(MPU_BASE_PTR,8)

#define	MPU_RGDAAC9 MPU_RGDAAC_REG(MPU_BASE_PTR,9)

#define	MPU_RGDAAC10 MPU_RGDAAC_REG(MPU_BASE_PTR,10)

#define	MPU_RGDAAC11 MPU_RGDAAC_REG(MPU_BASE_PTR,11)

#define	MPU_RGDAAC12 MPU_RGDAAC_REG(MPU_BASE_PTR,12)

#define	MPU_RGDAAC13 MPU_RGDAAC_REG(MPU_BASE_PTR,13)

#define	MPU_RGDAAC14 MPU_RGDAAC_REG(MPU_BASE_PTR,14)

#define	MPU_RGDAAC15 MPU_RGDAAC_REG(MPU_BASE_PTR,15)

#define	MPU_EAR(index) MPU_EAR_REG(MPU_BASE_PTR,index)

#define	MPU_EDR(index) MPU_EDR_REG(MPU_BASE_PTR,index)

#define	MPU_WORD(index, index2) MPU_WORD_REG(MPU_BASE_PTR,index,index2)

#define	MPU_RGDAAC(index) MPU_RGDAAC_REG(MPU_BASE_PTR,index)

#define	NFC_SRAM_B0_REG(base, index) ((base)->RESERVED_0[index])
	NFC SRAM buffers definitions. More...

#define	NFC_SRAM_B1_REG(base, index) ((base)->RESERVED_0[index+0x1000u])

#define	NFC_SRAM_B2_REG(base, index) ((base)->RESERVED_0[index+0x2000u])

#define	NFC_SRAM_B3_REG(base, index) ((base)->RESERVED_0[index+0x3000u])

#define	NFC_SRAM_B0(index) NFC_SRAM_B0_REG(NFC_BASE_PTR,index)

#define	NFC_SRAM_B1(index) NFC_SRAM_B1_REG(NFC_BASE_PTR,index)

#define	NFC_SRAM_B2(index) NFC_SRAM_B2_REG(NFC_BASE_PTR,index)

#define	NFC_SRAM_B3(index) NFC_SRAM_B3_REG(NFC_BASE_PTR,index)

#define	NFC_CMD1_REG(base) ((base)->CMD1)

#define	NFC_CMD2_REG(base) ((base)->CMD2)

#define	NFC_CAR_REG(base) ((base)->CAR)

#define	NFC_RAR_REG(base) ((base)->RAR)

#define	NFC_RPT_REG(base) ((base)->RPT)

#define	NFC_RAI_REG(base) ((base)->RAI)

#define	NFC_SR1_REG(base) ((base)->SR1)

#define	NFC_SR2_REG(base) ((base)->SR2)

#define	NFC_DMA1_REG(base) ((base)->DMA1)

#define	NFC_DMACFG_REG(base) ((base)->DMACFG)

#define	NFC_SWAP_REG(base) ((base)->SWAP)

#define	NFC_SECSZ_REG(base) ((base)->SECSZ)

#define	NFC_CFG_REG(base) ((base)->CFG)

#define	NFC_DMA2_REG(base) ((base)->DMA2)

#define	NFC_ISR_REG(base) ((base)->ISR)

#define	NFC_CMD1_BYTE3_MASK 0xFF0000u

#define	NFC_CMD1_BYTE3_SHIFT 16

#define	NFC_CMD1_BYTE3(x) (((uint32_t)(((uint32_t)(x))<<NFC_CMD1_BYTE3_SHIFT))&NFC_CMD1_BYTE3_MASK)

#define	NFC_CMD1_BYTE2_MASK 0xFF000000u

#define	NFC_CMD1_BYTE2_SHIFT 24

#define	NFC_CMD1_BYTE2(x) (((uint32_t)(((uint32_t)(x))<<NFC_CMD1_BYTE2_SHIFT))&NFC_CMD1_BYTE2_MASK)

#define	NFC_CMD2_BUSY_START_MASK 0x1u

#define	NFC_CMD2_BUSY_START_SHIFT 0

#define	NFC_CMD2_BUFNO_MASK 0x6u

#define	NFC_CMD2_BUFNO_SHIFT 1

#define	NFC_CMD2_BUFNO(x) (((uint32_t)(((uint32_t)(x))<<NFC_CMD2_BUFNO_SHIFT))&NFC_CMD2_BUFNO_MASK)

#define	NFC_CMD2_CODE_MASK 0xFFFF00u

#define	NFC_CMD2_CODE_SHIFT 8

#define	NFC_CMD2_CODE(x) (((uint32_t)(((uint32_t)(x))<<NFC_CMD2_CODE_SHIFT))&NFC_CMD2_CODE_MASK)

#define	NFC_CMD2_BYTE1_MASK 0xFF000000u

#define	NFC_CMD2_BYTE1_SHIFT 24

#define	NFC_CMD2_BYTE1(x) (((uint32_t)(((uint32_t)(x))<<NFC_CMD2_BYTE1_SHIFT))&NFC_CMD2_BYTE1_MASK)

#define	NFC_CAR_BYTE1_MASK 0xFFu

#define	NFC_CAR_BYTE1_SHIFT 0

#define	NFC_CAR_BYTE1(x) (((uint32_t)(((uint32_t)(x))<<NFC_CAR_BYTE1_SHIFT))&NFC_CAR_BYTE1_MASK)

#define	NFC_CAR_BYTE2_MASK 0xFF00u

#define	NFC_CAR_BYTE2_SHIFT 8

#define	NFC_CAR_BYTE2(x) (((uint32_t)(((uint32_t)(x))<<NFC_CAR_BYTE2_SHIFT))&NFC_CAR_BYTE2_MASK)

#define	NFC_RAR_BYTE1_MASK 0xFFu

#define	NFC_RAR_BYTE1_SHIFT 0

#define	NFC_RAR_BYTE1(x) (((uint32_t)(((uint32_t)(x))<<NFC_RAR_BYTE1_SHIFT))&NFC_RAR_BYTE1_MASK)

#define	NFC_RAR_BYTE2_MASK 0xFF00u

#define	NFC_RAR_BYTE2_SHIFT 8

#define	NFC_RAR_BYTE2(x) (((uint32_t)(((uint32_t)(x))<<NFC_RAR_BYTE2_SHIFT))&NFC_RAR_BYTE2_MASK)

#define	NFC_RAR_BYTE3_MASK 0xFF0000u

#define	NFC_RAR_BYTE3_SHIFT 16

#define	NFC_RAR_BYTE3(x) (((uint32_t)(((uint32_t)(x))<<NFC_RAR_BYTE3_SHIFT))&NFC_RAR_BYTE3_MASK)

#define	NFC_RAR_RB0_MASK 0x1000000u

#define	NFC_RAR_RB0_SHIFT 24

#define	NFC_RAR_RB1_MASK 0x2000000u

#define	NFC_RAR_RB1_SHIFT 25

#define	NFC_RAR_CS0_MASK 0x10000000u

#define	NFC_RAR_CS0_SHIFT 28

#define	NFC_RAR_CS1_MASK 0x20000000u

#define	NFC_RAR_CS1_SHIFT 29

#define	NFC_RPT_COUNT_MASK 0xFFFFu

#define	NFC_RPT_COUNT_SHIFT 0

#define	NFC_RPT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<NFC_RPT_COUNT_SHIFT))&NFC_RPT_COUNT_MASK)

#define	NFC_RAI_INC1_MASK 0xFFu

#define	NFC_RAI_INC1_SHIFT 0

#define	NFC_RAI_INC1(x) (((uint32_t)(((uint32_t)(x))<<NFC_RAI_INC1_SHIFT))&NFC_RAI_INC1_MASK)

#define	NFC_RAI_INC2_MASK 0xFF00u

#define	NFC_RAI_INC2_SHIFT 8

#define	NFC_RAI_INC2(x) (((uint32_t)(((uint32_t)(x))<<NFC_RAI_INC2_SHIFT))&NFC_RAI_INC2_MASK)

#define	NFC_RAI_INC3_MASK 0xFF0000u

#define	NFC_RAI_INC3_SHIFT 16

#define	NFC_RAI_INC3(x) (((uint32_t)(((uint32_t)(x))<<NFC_RAI_INC3_SHIFT))&NFC_RAI_INC3_MASK)

#define	NFC_SR1_ID4_MASK 0xFFu

#define	NFC_SR1_ID4_SHIFT 0

#define	NFC_SR1_ID4(x) (((uint32_t)(((uint32_t)(x))<<NFC_SR1_ID4_SHIFT))&NFC_SR1_ID4_MASK)

#define	NFC_SR1_ID3_MASK 0xFF00u

#define	NFC_SR1_ID3_SHIFT 8

#define	NFC_SR1_ID3(x) (((uint32_t)(((uint32_t)(x))<<NFC_SR1_ID3_SHIFT))&NFC_SR1_ID3_MASK)

#define	NFC_SR1_ID2_MASK 0xFF0000u

#define	NFC_SR1_ID2_SHIFT 16

#define	NFC_SR1_ID2(x) (((uint32_t)(((uint32_t)(x))<<NFC_SR1_ID2_SHIFT))&NFC_SR1_ID2_MASK)

#define	NFC_SR1_ID1_MASK 0xFF000000u

#define	NFC_SR1_ID1_SHIFT 24

#define	NFC_SR1_ID1(x) (((uint32_t)(((uint32_t)(x))<<NFC_SR1_ID1_SHIFT))&NFC_SR1_ID1_MASK)

#define	NFC_SR2_STATUS1_MASK 0xFFu

#define	NFC_SR2_STATUS1_SHIFT 0

#define	NFC_SR2_STATUS1(x) (((uint32_t)(((uint32_t)(x))<<NFC_SR2_STATUS1_SHIFT))&NFC_SR2_STATUS1_MASK)

#define	NFC_SR2_ID5_MASK 0xFF000000u

#define	NFC_SR2_ID5_SHIFT 24

#define	NFC_SR2_ID5(x) (((uint32_t)(((uint32_t)(x))<<NFC_SR2_ID5_SHIFT))&NFC_SR2_ID5_MASK)

#define	NFC_DMA1_ADDRESS_MASK 0xFFFFFFFFu

#define	NFC_DMA1_ADDRESS_SHIFT 0

#define	NFC_DMA1_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<NFC_DMA1_ADDRESS_SHIFT))&NFC_DMA1_ADDRESS_MASK)

#define	NFC_DMACFG_ACT2_MASK 0x1u

#define	NFC_DMACFG_ACT2_SHIFT 0

#define	NFC_DMACFG_ACT1_MASK 0x2u

#define	NFC_DMACFG_ACT1_SHIFT 1

#define	NFC_DMACFG_OFFSET2_MASK 0x1E00u

#define	NFC_DMACFG_OFFSET2_SHIFT 9

#define	NFC_DMACFG_OFFSET2(x) (((uint32_t)(((uint32_t)(x))<<NFC_DMACFG_OFFSET2_SHIFT))&NFC_DMACFG_OFFSET2_MASK)

#define	NFC_DMACFG_COUNT2_MASK 0xFE000u

#define	NFC_DMACFG_COUNT2_SHIFT 13

#define	NFC_DMACFG_COUNT2(x) (((uint32_t)(((uint32_t)(x))<<NFC_DMACFG_COUNT2_SHIFT))&NFC_DMACFG_COUNT2_MASK)

#define	NFC_DMACFG_COUNT1_MASK 0xFFF00000u

#define	NFC_DMACFG_COUNT1_SHIFT 20

#define	NFC_DMACFG_COUNT1(x) (((uint32_t)(((uint32_t)(x))<<NFC_DMACFG_COUNT1_SHIFT))&NFC_DMACFG_COUNT1_MASK)

#define	NFC_SWAP_ADDR2_MASK 0xFFEu

#define	NFC_SWAP_ADDR2_SHIFT 1

#define	NFC_SWAP_ADDR2(x) (((uint32_t)(((uint32_t)(x))<<NFC_SWAP_ADDR2_SHIFT))&NFC_SWAP_ADDR2_MASK)

#define	NFC_SWAP_ADDR1_MASK 0xFFE0000u

#define	NFC_SWAP_ADDR1_SHIFT 17

#define	NFC_SWAP_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<NFC_SWAP_ADDR1_SHIFT))&NFC_SWAP_ADDR1_MASK)

#define	NFC_SECSZ_SIZE_MASK 0x1FFFu

#define	NFC_SECSZ_SIZE_SHIFT 0

#define	NFC_SECSZ_SIZE(x) (((uint32_t)(((uint32_t)(x))<<NFC_SECSZ_SIZE_SHIFT))&NFC_SECSZ_SIZE_MASK)

#define	NFC_CFG_PAGECNT_MASK 0xFu

#define	NFC_CFG_PAGECNT_SHIFT 0

#define	NFC_CFG_PAGECNT(x) (((uint32_t)(((uint32_t)(x))<<NFC_CFG_PAGECNT_SHIFT))&NFC_CFG_PAGECNT_MASK)

#define	NFC_CFG_AIBN_MASK 0x10u

#define	NFC_CFG_AIBN_SHIFT 4

#define	NFC_CFG_AIAD_MASK 0x20u

#define	NFC_CFG_AIAD_SHIFT 5

#define	NFC_CFG_BITWIDTH_MASK 0x80u

#define	NFC_CFG_BITWIDTH_SHIFT 7

#define	NFC_CFG_TIMEOUT_MASK 0x1F00u

#define	NFC_CFG_TIMEOUT_SHIFT 8

#define	NFC_CFG_TIMEOUT(x) (((uint32_t)(((uint32_t)(x))<<NFC_CFG_TIMEOUT_SHIFT))&NFC_CFG_TIMEOUT_MASK)

#define	NFC_CFG_IDCNT_MASK 0xE000u

#define	NFC_CFG_IDCNT_SHIFT 13

#define	NFC_CFG_IDCNT(x) (((uint32_t)(((uint32_t)(x))<<NFC_CFG_IDCNT_SHIFT))&NFC_CFG_IDCNT_MASK)

#define	NFC_CFG_FAST_MASK 0x10000u

#define	NFC_CFG_FAST_SHIFT 16

#define	NFC_CFG_ECCMODE_MASK 0xE0000u

#define	NFC_CFG_ECCMODE_SHIFT 17

#define	NFC_CFG_ECCMODE(x) (((uint32_t)(((uint32_t)(x))<<NFC_CFG_ECCMODE_SHIFT))&NFC_CFG_ECCMODE_MASK)

#define	NFC_CFG_DMAREQ_MASK 0x100000u

#define	NFC_CFG_DMAREQ_SHIFT 20

#define	NFC_CFG_ECCSRAM_MASK 0x200000u

#define	NFC_CFG_ECCSRAM_SHIFT 21

#define	NFC_CFG_ECCAD_MASK 0x7FC00000u

#define	NFC_CFG_ECCAD_SHIFT 22

#define	NFC_CFG_ECCAD(x) (((uint32_t)(((uint32_t)(x))<<NFC_CFG_ECCAD_SHIFT))&NFC_CFG_ECCAD_MASK)

#define	NFC_CFG_STOPWERR_MASK 0x80000000u

#define	NFC_CFG_STOPWERR_SHIFT 31

#define	NFC_DMA2_ADDRESS_MASK 0xFFFFFFFFu

#define	NFC_DMA2_ADDRESS_SHIFT 0

#define	NFC_DMA2_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<NFC_DMA2_ADDRESS_SHIFT))&NFC_DMA2_ADDRESS_MASK)

#define	NFC_ISR_DMABN_MASK 0x3u

#define	NFC_ISR_DMABN_SHIFT 0

#define	NFC_ISR_DMABN(x) (((uint32_t)(((uint32_t)(x))<<NFC_ISR_DMABN_SHIFT))&NFC_ISR_DMABN_MASK)

#define	NFC_ISR_ECCBN_MASK 0xCu

#define	NFC_ISR_ECCBN_SHIFT 2

#define	NFC_ISR_ECCBN(x) (((uint32_t)(((uint32_t)(x))<<NFC_ISR_ECCBN_SHIFT))&NFC_ISR_ECCBN_MASK)

#define	NFC_ISR_RESBN_MASK 0x30u

#define	NFC_ISR_RESBN_SHIFT 4

#define	NFC_ISR_RESBN(x) (((uint32_t)(((uint32_t)(x))<<NFC_ISR_RESBN_SHIFT))&NFC_ISR_RESBN_MASK)

#define	NFC_ISR_IDLECLR_MASK 0x20000u

#define	NFC_ISR_IDLECLR_SHIFT 17

#define	NFC_ISR_DONECLR_MASK 0x40000u

#define	NFC_ISR_DONECLR_SHIFT 18

#define	NFC_ISR_WERRCLR_MASK 0x80000u

#define	NFC_ISR_WERRCLR_SHIFT 19

#define	NFC_ISR_IDLEEN_MASK 0x100000u

#define	NFC_ISR_IDLEEN_SHIFT 20

#define	NFC_ISR_DONEEN_MASK 0x200000u

#define	NFC_ISR_DONEEN_SHIFT 21

#define	NFC_ISR_WERREN_MASK 0x400000u

#define	NFC_ISR_WERREN_SHIFT 22

#define	NFC_ISR_DMABUSY_MASK 0x800000u

#define	NFC_ISR_DMABUSY_SHIFT 23

#define	NFC_ISR_ECCBUSY_MASK 0x1000000u

#define	NFC_ISR_ECCBUSY_SHIFT 24

#define	NFC_ISR_RESBUSY_MASK 0x2000000u

#define	NFC_ISR_RESBUSY_SHIFT 25

#define	NFC_ISR_CMDBUSY_MASK 0x4000000u

#define	NFC_ISR_CMDBUSY_SHIFT 26

#define	NFC_ISR_WERRNS_MASK 0x8000000u

#define	NFC_ISR_WERRNS_SHIFT 27

#define	NFC_ISR_IDLE_MASK 0x20000000u

#define	NFC_ISR_IDLE_SHIFT 29

#define	NFC_ISR_DONE_MASK 0x40000000u

#define	NFC_ISR_DONE_SHIFT 30

#define	NFC_ISR_WERR_MASK 0x80000000u

#define	NFC_ISR_WERR_SHIFT 31

#define	NFC_BASE_PTR ((NFC_MemMapPtr)0x400A8000u)

#define	NFC_BASE_PTRS { NFC_BASE_PTR }

#define	NFC_CMD1 NFC_CMD1_REG(NFC_BASE_PTR)

#define	NFC_CMD2 NFC_CMD2_REG(NFC_BASE_PTR)

#define	NFC_CAR NFC_CAR_REG(NFC_BASE_PTR)

#define	NFC_RAR NFC_RAR_REG(NFC_BASE_PTR)

#define	NFC_RPT NFC_RPT_REG(NFC_BASE_PTR)

#define	NFC_RAI NFC_RAI_REG(NFC_BASE_PTR)

#define	NFC_SR1 NFC_SR1_REG(NFC_BASE_PTR)

#define	NFC_SR2 NFC_SR2_REG(NFC_BASE_PTR)

#define	NFC_DMA1 NFC_DMA1_REG(NFC_BASE_PTR)

#define	NFC_DMACFG NFC_DMACFG_REG(NFC_BASE_PTR)

#define	NFC_SWAP NFC_SWAP_REG(NFC_BASE_PTR)

#define	NFC_SECSZ NFC_SECSZ_REG(NFC_BASE_PTR)

#define	NFC_CFG NFC_CFG_REG(NFC_BASE_PTR)

#define	NFC_DMA2 NFC_DMA2_REG(NFC_BASE_PTR)

#define	NFC_ISR NFC_ISR_REG(NFC_BASE_PTR)

#define	NV_BACKKEY3_REG(base) ((base)->BACKKEY3)

#define	NV_BACKKEY2_REG(base) ((base)->BACKKEY2)

#define	NV_BACKKEY1_REG(base) ((base)->BACKKEY1)

#define	NV_BACKKEY0_REG(base) ((base)->BACKKEY0)

#define	NV_BACKKEY7_REG(base) ((base)->BACKKEY7)

#define	NV_BACKKEY6_REG(base) ((base)->BACKKEY6)

#define	NV_BACKKEY5_REG(base) ((base)->BACKKEY5)

#define	NV_BACKKEY4_REG(base) ((base)->BACKKEY4)

#define	NV_FPROT3_REG(base) ((base)->FPROT3)

#define	NV_FPROT2_REG(base) ((base)->FPROT2)

#define	NV_FPROT1_REG(base) ((base)->FPROT1)

#define	NV_FPROT0_REG(base) ((base)->FPROT0)

#define	NV_FSEC_REG(base) ((base)->FSEC)

#define	NV_FOPT_REG(base) ((base)->FOPT)

#define	NV_FEPROT_REG(base) ((base)->FEPROT)

#define	NV_FDPROT_REG(base) ((base)->FDPROT)

#define	NV_BACKKEY3_KEY_MASK 0xFFu

#define	NV_BACKKEY3_KEY_SHIFT 0

#define	NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)

#define	NV_BACKKEY2_KEY_MASK 0xFFu

#define	NV_BACKKEY2_KEY_SHIFT 0

#define	NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)

#define	NV_BACKKEY1_KEY_MASK 0xFFu

#define	NV_BACKKEY1_KEY_SHIFT 0

#define	NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)

#define	NV_BACKKEY0_KEY_MASK 0xFFu

#define	NV_BACKKEY0_KEY_SHIFT 0

#define	NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)

#define	NV_BACKKEY7_KEY_MASK 0xFFu

#define	NV_BACKKEY7_KEY_SHIFT 0

#define	NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)

#define	NV_BACKKEY6_KEY_MASK 0xFFu

#define	NV_BACKKEY6_KEY_SHIFT 0

#define	NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)

#define	NV_BACKKEY5_KEY_MASK 0xFFu

#define	NV_BACKKEY5_KEY_SHIFT 0

#define	NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)

#define	NV_BACKKEY4_KEY_MASK 0xFFu

#define	NV_BACKKEY4_KEY_SHIFT 0

#define	NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)

#define	NV_FPROT3_PROT_MASK 0xFFu

#define	NV_FPROT3_PROT_SHIFT 0

#define	NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)

#define	NV_FPROT2_PROT_MASK 0xFFu

#define	NV_FPROT2_PROT_SHIFT 0

#define	NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)

#define	NV_FPROT1_PROT_MASK 0xFFu

#define	NV_FPROT1_PROT_SHIFT 0

#define	NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)

#define	NV_FPROT0_PROT_MASK 0xFFu

#define	NV_FPROT0_PROT_SHIFT 0

#define	NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)

#define	NV_FSEC_SEC_MASK 0x3u

#define	NV_FSEC_SEC_SHIFT 0

#define	NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)

#define	NV_FSEC_FSLACC_MASK 0xCu

#define	NV_FSEC_FSLACC_SHIFT 2

#define	NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)

#define	NV_FSEC_MEEN_MASK 0x30u

#define	NV_FSEC_MEEN_SHIFT 4

#define	NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)

#define	NV_FSEC_KEYEN_MASK 0xC0u

#define	NV_FSEC_KEYEN_SHIFT 6

#define	NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)

#define	NV_FOPT_LPBOOT_MASK 0x1u

#define	NV_FOPT_LPBOOT_SHIFT 0

#define	NV_FOPT_EZPORT_DIS_MASK 0x2u

#define	NV_FOPT_EZPORT_DIS_SHIFT 1

#define	NV_FEPROT_EPROT_MASK 0xFFu

#define	NV_FEPROT_EPROT_SHIFT 0

#define	NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)

#define	NV_FDPROT_DPROT_MASK 0xFFu

#define	NV_FDPROT_DPROT_SHIFT 0

#define	NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)

#define	FTFE_FlashConfig_BASE_PTR ((NV_MemMapPtr)0x400u)

#define	NV_BASE_PTRS { FTFE_FlashConfig_BASE_PTR }

#define	NV_BACKKEY3 NV_BACKKEY3_REG(FTFE_FlashConfig_BASE_PTR)

#define	NV_BACKKEY2 NV_BACKKEY2_REG(FTFE_FlashConfig_BASE_PTR)

#define	NV_BACKKEY1 NV_BACKKEY1_REG(FTFE_FlashConfig_BASE_PTR)

#define	NV_BACKKEY0 NV_BACKKEY0_REG(FTFE_FlashConfig_BASE_PTR)

#define	NV_BACKKEY7 NV_BACKKEY7_REG(FTFE_FlashConfig_BASE_PTR)

#define	NV_BACKKEY6 NV_BACKKEY6_REG(FTFE_FlashConfig_BASE_PTR)

#define	NV_BACKKEY5 NV_BACKKEY5_REG(FTFE_FlashConfig_BASE_PTR)

#define	NV_BACKKEY4 NV_BACKKEY4_REG(FTFE_FlashConfig_BASE_PTR)

#define	NV_FPROT3 NV_FPROT3_REG(FTFE_FlashConfig_BASE_PTR)

#define	NV_FPROT2 NV_FPROT2_REG(FTFE_FlashConfig_BASE_PTR)

#define	NV_FPROT1 NV_FPROT1_REG(FTFE_FlashConfig_BASE_PTR)

#define	NV_FPROT0 NV_FPROT0_REG(FTFE_FlashConfig_BASE_PTR)

#define	NV_FSEC NV_FSEC_REG(FTFE_FlashConfig_BASE_PTR)

#define	NV_FOPT NV_FOPT_REG(FTFE_FlashConfig_BASE_PTR)

#define	NV_FEPROT NV_FEPROT_REG(FTFE_FlashConfig_BASE_PTR)

#define	NV_FDPROT NV_FDPROT_REG(FTFE_FlashConfig_BASE_PTR)

#define	NVIC_ISER_REG(base, index) ((base)->ISER[index])

#define	NVIC_ICER_REG(base, index) ((base)->ICER[index])

#define	NVIC_ISPR_REG(base, index) ((base)->ISPR[index])

#define	NVIC_ICPR_REG(base, index) ((base)->ICPR[index])

#define	NVIC_IABR_REG(base, index) ((base)->IABR[index])

#define	NVIC_IP_REG(base, index) ((base)->IP[index])

#define	NVIC_STIR_REG(base, index) ((base)->STIR[index])

#define	NVIC_ISER_SETENA_MASK 0xFFFFFFFFu

#define	NVIC_ISER_SETENA_SHIFT 0

#define	NVIC_ISER_SETENA(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ISER_SETENA_SHIFT))&NVIC_ISER_SETENA_MASK)

#define	NVIC_ICER_CLRENA_MASK 0xFFFFFFFFu

#define	NVIC_ICER_CLRENA_SHIFT 0

#define	NVIC_ICER_CLRENA(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ICER_CLRENA_SHIFT))&NVIC_ICER_CLRENA_MASK)

#define	NVIC_ISPR_SETPEND_MASK 0xFFFFFFFFu

#define	NVIC_ISPR_SETPEND_SHIFT 0

#define	NVIC_ISPR_SETPEND(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ISPR_SETPEND_SHIFT))&NVIC_ISPR_SETPEND_MASK)

#define	NVIC_ICPR_CLRPEND_MASK 0xFFFFFFFFu

#define	NVIC_ICPR_CLRPEND_SHIFT 0

#define	NVIC_ICPR_CLRPEND(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ICPR_CLRPEND_SHIFT))&NVIC_ICPR_CLRPEND_MASK)

#define	NVIC_IABR_ACTIVE_MASK 0xFFFFFFFFu

#define	NVIC_IABR_ACTIVE_SHIFT 0

#define	NVIC_IABR_ACTIVE(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IABR_ACTIVE_SHIFT))&NVIC_IABR_ACTIVE_MASK)

#define	NVIC_IP_PRI0_MASK 0xFFu

#define	NVIC_IP_PRI0_SHIFT 0

#define	NVIC_IP_PRI0(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI0_SHIFT))&NVIC_IP_PRI0_MASK)

#define	NVIC_IP_PRI1_MASK 0xFFu

#define	NVIC_IP_PRI1_SHIFT 0

#define	NVIC_IP_PRI1(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI1_SHIFT))&NVIC_IP_PRI1_MASK)

#define	NVIC_IP_PRI2_MASK 0xFFu

#define	NVIC_IP_PRI2_SHIFT 0

#define	NVIC_IP_PRI2(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI2_SHIFT))&NVIC_IP_PRI2_MASK)

#define	NVIC_IP_PRI3_MASK 0xFFu

#define	NVIC_IP_PRI3_SHIFT 0

#define	NVIC_IP_PRI3(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI3_SHIFT))&NVIC_IP_PRI3_MASK)

#define	NVIC_IP_PRI4_MASK 0xFFu

#define	NVIC_IP_PRI4_SHIFT 0

#define	NVIC_IP_PRI4(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI4_SHIFT))&NVIC_IP_PRI4_MASK)

#define	NVIC_IP_PRI5_MASK 0xFFu

#define	NVIC_IP_PRI5_SHIFT 0

#define	NVIC_IP_PRI5(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI5_SHIFT))&NVIC_IP_PRI5_MASK)

#define	NVIC_IP_PRI6_MASK 0xFFu

#define	NVIC_IP_PRI6_SHIFT 0

#define	NVIC_IP_PRI6(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI6_SHIFT))&NVIC_IP_PRI6_MASK)

#define	NVIC_IP_PRI7_MASK 0xFFu

#define	NVIC_IP_PRI7_SHIFT 0

#define	NVIC_IP_PRI7(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI7_SHIFT))&NVIC_IP_PRI7_MASK)

#define	NVIC_IP_PRI8_MASK 0xFFu

#define	NVIC_IP_PRI8_SHIFT 0

#define	NVIC_IP_PRI8(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI8_SHIFT))&NVIC_IP_PRI8_MASK)

#define	NVIC_IP_PRI9_MASK 0xFFu

#define	NVIC_IP_PRI9_SHIFT 0

#define	NVIC_IP_PRI9(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI9_SHIFT))&NVIC_IP_PRI9_MASK)

#define	NVIC_IP_PRI10_MASK 0xFFu

#define	NVIC_IP_PRI10_SHIFT 0

#define	NVIC_IP_PRI10(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI10_SHIFT))&NVIC_IP_PRI10_MASK)

#define	NVIC_IP_PRI11_MASK 0xFFu

#define	NVIC_IP_PRI11_SHIFT 0

#define	NVIC_IP_PRI11(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI11_SHIFT))&NVIC_IP_PRI11_MASK)

#define	NVIC_IP_PRI12_MASK 0xFFu

#define	NVIC_IP_PRI12_SHIFT 0

#define	NVIC_IP_PRI12(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI12_SHIFT))&NVIC_IP_PRI12_MASK)

#define	NVIC_IP_PRI13_MASK 0xFFu

#define	NVIC_IP_PRI13_SHIFT 0

#define	NVIC_IP_PRI13(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI13_SHIFT))&NVIC_IP_PRI13_MASK)

#define	NVIC_IP_PRI14_MASK 0xFFu

#define	NVIC_IP_PRI14_SHIFT 0

#define	NVIC_IP_PRI14(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI14_SHIFT))&NVIC_IP_PRI14_MASK)

#define	NVIC_IP_PRI15_MASK 0xFFu

#define	NVIC_IP_PRI15_SHIFT 0

#define	NVIC_IP_PRI15(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI15_SHIFT))&NVIC_IP_PRI15_MASK)

#define	NVIC_IP_PRI16_MASK 0xFFu

#define	NVIC_IP_PRI16_SHIFT 0

#define	NVIC_IP_PRI16(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI16_SHIFT))&NVIC_IP_PRI16_MASK)

#define	NVIC_IP_PRI17_MASK 0xFFu

#define	NVIC_IP_PRI17_SHIFT 0

#define	NVIC_IP_PRI17(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI17_SHIFT))&NVIC_IP_PRI17_MASK)

#define	NVIC_IP_PRI18_MASK 0xFFu

#define	NVIC_IP_PRI18_SHIFT 0

#define	NVIC_IP_PRI18(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI18_SHIFT))&NVIC_IP_PRI18_MASK)

#define	NVIC_IP_PRI19_MASK 0xFFu

#define	NVIC_IP_PRI19_SHIFT 0

#define	NVIC_IP_PRI19(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI19_SHIFT))&NVIC_IP_PRI19_MASK)

#define	NVIC_IP_PRI20_MASK 0xFFu

#define	NVIC_IP_PRI20_SHIFT 0

#define	NVIC_IP_PRI20(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI20_SHIFT))&NVIC_IP_PRI20_MASK)

#define	NVIC_IP_PRI21_MASK 0xFFu

#define	NVIC_IP_PRI21_SHIFT 0

#define	NVIC_IP_PRI21(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI21_SHIFT))&NVIC_IP_PRI21_MASK)

#define	NVIC_IP_PRI22_MASK 0xFFu

#define	NVIC_IP_PRI22_SHIFT 0

#define	NVIC_IP_PRI22(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI22_SHIFT))&NVIC_IP_PRI22_MASK)

#define	NVIC_IP_PRI23_MASK 0xFFu

#define	NVIC_IP_PRI23_SHIFT 0

#define	NVIC_IP_PRI23(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI23_SHIFT))&NVIC_IP_PRI23_MASK)

#define	NVIC_IP_PRI24_MASK 0xFFu

#define	NVIC_IP_PRI24_SHIFT 0

#define	NVIC_IP_PRI24(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI24_SHIFT))&NVIC_IP_PRI24_MASK)

#define	NVIC_IP_PRI25_MASK 0xFFu

#define	NVIC_IP_PRI25_SHIFT 0

#define	NVIC_IP_PRI25(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI25_SHIFT))&NVIC_IP_PRI25_MASK)

#define	NVIC_IP_PRI26_MASK 0xFFu

#define	NVIC_IP_PRI26_SHIFT 0

#define	NVIC_IP_PRI26(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI26_SHIFT))&NVIC_IP_PRI26_MASK)

#define	NVIC_IP_PRI27_MASK 0xFFu

#define	NVIC_IP_PRI27_SHIFT 0

#define	NVIC_IP_PRI27(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI27_SHIFT))&NVIC_IP_PRI27_MASK)

#define	NVIC_IP_PRI28_MASK 0xFFu

#define	NVIC_IP_PRI28_SHIFT 0

#define	NVIC_IP_PRI28(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI28_SHIFT))&NVIC_IP_PRI28_MASK)

#define	NVIC_IP_PRI29_MASK 0xFFu

#define	NVIC_IP_PRI29_SHIFT 0

#define	NVIC_IP_PRI29(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI29_SHIFT))&NVIC_IP_PRI29_MASK)

#define	NVIC_IP_PRI30_MASK 0xFFu

#define	NVIC_IP_PRI30_SHIFT 0

#define	NVIC_IP_PRI30(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI30_SHIFT))&NVIC_IP_PRI30_MASK)

#define	NVIC_IP_PRI31_MASK 0xFFu

#define	NVIC_IP_PRI31_SHIFT 0

#define	NVIC_IP_PRI31(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI31_SHIFT))&NVIC_IP_PRI31_MASK)

#define	NVIC_IP_PRI32_MASK 0xFFu

#define	NVIC_IP_PRI32_SHIFT 0

#define	NVIC_IP_PRI32(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI32_SHIFT))&NVIC_IP_PRI32_MASK)

#define	NVIC_IP_PRI33_MASK 0xFFu

#define	NVIC_IP_PRI33_SHIFT 0

#define	NVIC_IP_PRI33(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI33_SHIFT))&NVIC_IP_PRI33_MASK)

#define	NVIC_IP_PRI34_MASK 0xFFu

#define	NVIC_IP_PRI34_SHIFT 0

#define	NVIC_IP_PRI34(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI34_SHIFT))&NVIC_IP_PRI34_MASK)

#define	NVIC_IP_PRI35_MASK 0xFFu

#define	NVIC_IP_PRI35_SHIFT 0

#define	NVIC_IP_PRI35(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI35_SHIFT))&NVIC_IP_PRI35_MASK)

#define	NVIC_IP_PRI36_MASK 0xFFu

#define	NVIC_IP_PRI36_SHIFT 0

#define	NVIC_IP_PRI36(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI36_SHIFT))&NVIC_IP_PRI36_MASK)

#define	NVIC_IP_PRI37_MASK 0xFFu

#define	NVIC_IP_PRI37_SHIFT 0

#define	NVIC_IP_PRI37(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI37_SHIFT))&NVIC_IP_PRI37_MASK)

#define	NVIC_IP_PRI38_MASK 0xFFu

#define	NVIC_IP_PRI38_SHIFT 0

#define	NVIC_IP_PRI38(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI38_SHIFT))&NVIC_IP_PRI38_MASK)

#define	NVIC_IP_PRI39_MASK 0xFFu

#define	NVIC_IP_PRI39_SHIFT 0

#define	NVIC_IP_PRI39(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI39_SHIFT))&NVIC_IP_PRI39_MASK)

#define	NVIC_IP_PRI40_MASK 0xFFu

#define	NVIC_IP_PRI40_SHIFT 0

#define	NVIC_IP_PRI40(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI40_SHIFT))&NVIC_IP_PRI40_MASK)

#define	NVIC_IP_PRI41_MASK 0xFFu

#define	NVIC_IP_PRI41_SHIFT 0

#define	NVIC_IP_PRI41(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI41_SHIFT))&NVIC_IP_PRI41_MASK)

#define	NVIC_IP_PRI42_MASK 0xFFu

#define	NVIC_IP_PRI42_SHIFT 0

#define	NVIC_IP_PRI42(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI42_SHIFT))&NVIC_IP_PRI42_MASK)

#define	NVIC_IP_PRI43_MASK 0xFFu

#define	NVIC_IP_PRI43_SHIFT 0

#define	NVIC_IP_PRI43(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI43_SHIFT))&NVIC_IP_PRI43_MASK)

#define	NVIC_IP_PRI44_MASK 0xFFu

#define	NVIC_IP_PRI44_SHIFT 0

#define	NVIC_IP_PRI44(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI44_SHIFT))&NVIC_IP_PRI44_MASK)

#define	NVIC_IP_PRI45_MASK 0xFFu

#define	NVIC_IP_PRI45_SHIFT 0

#define	NVIC_IP_PRI45(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI45_SHIFT))&NVIC_IP_PRI45_MASK)

#define	NVIC_IP_PRI46_MASK 0xFFu

#define	NVIC_IP_PRI46_SHIFT 0

#define	NVIC_IP_PRI46(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI46_SHIFT))&NVIC_IP_PRI46_MASK)

#define	NVIC_IP_PRI47_MASK 0xFFu

#define	NVIC_IP_PRI47_SHIFT 0

#define	NVIC_IP_PRI47(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI47_SHIFT))&NVIC_IP_PRI47_MASK)

#define	NVIC_IP_PRI48_MASK 0xFFu

#define	NVIC_IP_PRI48_SHIFT 0

#define	NVIC_IP_PRI48(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI48_SHIFT))&NVIC_IP_PRI48_MASK)

#define	NVIC_IP_PRI49_MASK 0xFFu

#define	NVIC_IP_PRI49_SHIFT 0

#define	NVIC_IP_PRI49(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI49_SHIFT))&NVIC_IP_PRI49_MASK)

#define	NVIC_IP_PRI50_MASK 0xFFu

#define	NVIC_IP_PRI50_SHIFT 0

#define	NVIC_IP_PRI50(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI50_SHIFT))&NVIC_IP_PRI50_MASK)

#define	NVIC_IP_PRI51_MASK 0xFFu

#define	NVIC_IP_PRI51_SHIFT 0

#define	NVIC_IP_PRI51(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI51_SHIFT))&NVIC_IP_PRI51_MASK)

#define	NVIC_IP_PRI52_MASK 0xFFu

#define	NVIC_IP_PRI52_SHIFT 0

#define	NVIC_IP_PRI52(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI52_SHIFT))&NVIC_IP_PRI52_MASK)

#define	NVIC_IP_PRI53_MASK 0xFFu

#define	NVIC_IP_PRI53_SHIFT 0

#define	NVIC_IP_PRI53(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI53_SHIFT))&NVIC_IP_PRI53_MASK)

#define	NVIC_IP_PRI54_MASK 0xFFu

#define	NVIC_IP_PRI54_SHIFT 0

#define	NVIC_IP_PRI54(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI54_SHIFT))&NVIC_IP_PRI54_MASK)

#define	NVIC_IP_PRI55_MASK 0xFFu

#define	NVIC_IP_PRI55_SHIFT 0

#define	NVIC_IP_PRI55(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI55_SHIFT))&NVIC_IP_PRI55_MASK)

#define	NVIC_IP_PRI56_MASK 0xFFu

#define	NVIC_IP_PRI56_SHIFT 0

#define	NVIC_IP_PRI56(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI56_SHIFT))&NVIC_IP_PRI56_MASK)

#define	NVIC_IP_PRI57_MASK 0xFFu

#define	NVIC_IP_PRI57_SHIFT 0

#define	NVIC_IP_PRI57(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI57_SHIFT))&NVIC_IP_PRI57_MASK)

#define	NVIC_IP_PRI58_MASK 0xFFu

#define	NVIC_IP_PRI58_SHIFT 0

#define	NVIC_IP_PRI58(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI58_SHIFT))&NVIC_IP_PRI58_MASK)

#define	NVIC_IP_PRI59_MASK 0xFFu

#define	NVIC_IP_PRI59_SHIFT 0

#define	NVIC_IP_PRI59(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI59_SHIFT))&NVIC_IP_PRI59_MASK)

#define	NVIC_IP_PRI60_MASK 0xFFu

#define	NVIC_IP_PRI60_SHIFT 0

#define	NVIC_IP_PRI60(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI60_SHIFT))&NVIC_IP_PRI60_MASK)

#define	NVIC_IP_PRI61_MASK 0xFFu

#define	NVIC_IP_PRI61_SHIFT 0

#define	NVIC_IP_PRI61(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI61_SHIFT))&NVIC_IP_PRI61_MASK)

#define	NVIC_IP_PRI62_MASK 0xFFu

#define	NVIC_IP_PRI62_SHIFT 0

#define	NVIC_IP_PRI62(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI62_SHIFT))&NVIC_IP_PRI62_MASK)

#define	NVIC_IP_PRI63_MASK 0xFFu

#define	NVIC_IP_PRI63_SHIFT 0

#define	NVIC_IP_PRI63(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI63_SHIFT))&NVIC_IP_PRI63_MASK)

#define	NVIC_IP_PRI64_MASK 0xFFu

#define	NVIC_IP_PRI64_SHIFT 0

#define	NVIC_IP_PRI64(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI64_SHIFT))&NVIC_IP_PRI64_MASK)

#define	NVIC_IP_PRI65_MASK 0xFFu

#define	NVIC_IP_PRI65_SHIFT 0

#define	NVIC_IP_PRI65(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI65_SHIFT))&NVIC_IP_PRI65_MASK)

#define	NVIC_IP_PRI66_MASK 0xFFu

#define	NVIC_IP_PRI66_SHIFT 0

#define	NVIC_IP_PRI66(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI66_SHIFT))&NVIC_IP_PRI66_MASK)

#define	NVIC_IP_PRI67_MASK 0xFFu

#define	NVIC_IP_PRI67_SHIFT 0

#define	NVIC_IP_PRI67(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI67_SHIFT))&NVIC_IP_PRI67_MASK)

#define	NVIC_IP_PRI68_MASK 0xFFu

#define	NVIC_IP_PRI68_SHIFT 0

#define	NVIC_IP_PRI68(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI68_SHIFT))&NVIC_IP_PRI68_MASK)

#define	NVIC_IP_PRI69_MASK 0xFFu

#define	NVIC_IP_PRI69_SHIFT 0

#define	NVIC_IP_PRI69(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI69_SHIFT))&NVIC_IP_PRI69_MASK)

#define	NVIC_IP_PRI70_MASK 0xFFu

#define	NVIC_IP_PRI70_SHIFT 0

#define	NVIC_IP_PRI70(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI70_SHIFT))&NVIC_IP_PRI70_MASK)

#define	NVIC_IP_PRI71_MASK 0xFFu

#define	NVIC_IP_PRI71_SHIFT 0

#define	NVIC_IP_PRI71(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI71_SHIFT))&NVIC_IP_PRI71_MASK)

#define	NVIC_IP_PRI72_MASK 0xFFu

#define	NVIC_IP_PRI72_SHIFT 0

#define	NVIC_IP_PRI72(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI72_SHIFT))&NVIC_IP_PRI72_MASK)

#define	NVIC_IP_PRI73_MASK 0xFFu

#define	NVIC_IP_PRI73_SHIFT 0

#define	NVIC_IP_PRI73(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI73_SHIFT))&NVIC_IP_PRI73_MASK)

#define	NVIC_IP_PRI74_MASK 0xFFu

#define	NVIC_IP_PRI74_SHIFT 0

#define	NVIC_IP_PRI74(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI74_SHIFT))&NVIC_IP_PRI74_MASK)

#define	NVIC_IP_PRI75_MASK 0xFFu

#define	NVIC_IP_PRI75_SHIFT 0

#define	NVIC_IP_PRI75(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI75_SHIFT))&NVIC_IP_PRI75_MASK)

#define	NVIC_IP_PRI76_MASK 0xFFu

#define	NVIC_IP_PRI76_SHIFT 0

#define	NVIC_IP_PRI76(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI76_SHIFT))&NVIC_IP_PRI76_MASK)

#define	NVIC_IP_PRI77_MASK 0xFFu

#define	NVIC_IP_PRI77_SHIFT 0

#define	NVIC_IP_PRI77(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI77_SHIFT))&NVIC_IP_PRI77_MASK)

#define	NVIC_IP_PRI78_MASK 0xFFu

#define	NVIC_IP_PRI78_SHIFT 0

#define	NVIC_IP_PRI78(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI78_SHIFT))&NVIC_IP_PRI78_MASK)

#define	NVIC_IP_PRI79_MASK 0xFFu

#define	NVIC_IP_PRI79_SHIFT 0

#define	NVIC_IP_PRI79(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI79_SHIFT))&NVIC_IP_PRI79_MASK)

#define	NVIC_IP_PRI80_MASK 0xFFu

#define	NVIC_IP_PRI80_SHIFT 0

#define	NVIC_IP_PRI80(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI80_SHIFT))&NVIC_IP_PRI80_MASK)

#define	NVIC_IP_PRI81_MASK 0xFFu

#define	NVIC_IP_PRI81_SHIFT 0

#define	NVIC_IP_PRI81(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI81_SHIFT))&NVIC_IP_PRI81_MASK)

#define	NVIC_IP_PRI82_MASK 0xFFu

#define	NVIC_IP_PRI82_SHIFT 0

#define	NVIC_IP_PRI82(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI82_SHIFT))&NVIC_IP_PRI82_MASK)

#define	NVIC_IP_PRI83_MASK 0xFFu

#define	NVIC_IP_PRI83_SHIFT 0

#define	NVIC_IP_PRI83(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI83_SHIFT))&NVIC_IP_PRI83_MASK)

#define	NVIC_IP_PRI84_MASK 0xFFu

#define	NVIC_IP_PRI84_SHIFT 0

#define	NVIC_IP_PRI84(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI84_SHIFT))&NVIC_IP_PRI84_MASK)

#define	NVIC_IP_PRI85_MASK 0xFFu

#define	NVIC_IP_PRI85_SHIFT 0

#define	NVIC_IP_PRI85(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI85_SHIFT))&NVIC_IP_PRI85_MASK)

#define	NVIC_IP_PRI86_MASK 0xFFu

#define	NVIC_IP_PRI86_SHIFT 0

#define	NVIC_IP_PRI86(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI86_SHIFT))&NVIC_IP_PRI86_MASK)

#define	NVIC_IP_PRI87_MASK 0xFFu

#define	NVIC_IP_PRI87_SHIFT 0

#define	NVIC_IP_PRI87(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI87_SHIFT))&NVIC_IP_PRI87_MASK)

#define	NVIC_IP_PRI88_MASK 0xFFu

#define	NVIC_IP_PRI88_SHIFT 0

#define	NVIC_IP_PRI88(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI88_SHIFT))&NVIC_IP_PRI88_MASK)

#define	NVIC_IP_PRI89_MASK 0xFFu

#define	NVIC_IP_PRI89_SHIFT 0

#define	NVIC_IP_PRI89(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI89_SHIFT))&NVIC_IP_PRI89_MASK)

#define	NVIC_IP_PRI90_MASK 0xFFu

#define	NVIC_IP_PRI90_SHIFT 0

#define	NVIC_IP_PRI90(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI90_SHIFT))&NVIC_IP_PRI90_MASK)

#define	NVIC_IP_PRI91_MASK 0xFFu

#define	NVIC_IP_PRI91_SHIFT 0

#define	NVIC_IP_PRI91(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI91_SHIFT))&NVIC_IP_PRI91_MASK)

#define	NVIC_IP_PRI92_MASK 0xFFu

#define	NVIC_IP_PRI92_SHIFT 0

#define	NVIC_IP_PRI92(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI92_SHIFT))&NVIC_IP_PRI92_MASK)

#define	NVIC_IP_PRI93_MASK 0xFFu

#define	NVIC_IP_PRI93_SHIFT 0

#define	NVIC_IP_PRI93(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI93_SHIFT))&NVIC_IP_PRI93_MASK)

#define	NVIC_IP_PRI94_MASK 0xFFu

#define	NVIC_IP_PRI94_SHIFT 0

#define	NVIC_IP_PRI94(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI94_SHIFT))&NVIC_IP_PRI94_MASK)

#define	NVIC_IP_PRI95_MASK 0xFFu

#define	NVIC_IP_PRI95_SHIFT 0

#define	NVIC_IP_PRI95(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI95_SHIFT))&NVIC_IP_PRI95_MASK)

#define	NVIC_IP_PRI96_MASK 0xFFu

#define	NVIC_IP_PRI96_SHIFT 0

#define	NVIC_IP_PRI96(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI96_SHIFT))&NVIC_IP_PRI96_MASK)

#define	NVIC_IP_PRI97_MASK 0xFFu

#define	NVIC_IP_PRI97_SHIFT 0

#define	NVIC_IP_PRI97(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI97_SHIFT))&NVIC_IP_PRI97_MASK)

#define	NVIC_IP_PRI98_MASK 0xFFu

#define	NVIC_IP_PRI98_SHIFT 0

#define	NVIC_IP_PRI98(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI98_SHIFT))&NVIC_IP_PRI98_MASK)

#define	NVIC_IP_PRI99_MASK 0xFFu

#define	NVIC_IP_PRI99_SHIFT 0

#define	NVIC_IP_PRI99(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI99_SHIFT))&NVIC_IP_PRI99_MASK)

#define	NVIC_IP_PRI100_MASK 0xFFu

#define	NVIC_IP_PRI100_SHIFT 0

#define	NVIC_IP_PRI100(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI100_SHIFT))&NVIC_IP_PRI100_MASK)

#define	NVIC_IP_PRI101_MASK 0xFFu

#define	NVIC_IP_PRI101_SHIFT 0

#define	NVIC_IP_PRI101(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI101_SHIFT))&NVIC_IP_PRI101_MASK)

#define	NVIC_IP_PRI102_MASK 0xFFu

#define	NVIC_IP_PRI102_SHIFT 0

#define	NVIC_IP_PRI102(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI102_SHIFT))&NVIC_IP_PRI102_MASK)

#define	NVIC_IP_PRI103_MASK 0xFFu

#define	NVIC_IP_PRI103_SHIFT 0

#define	NVIC_IP_PRI103(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI103_SHIFT))&NVIC_IP_PRI103_MASK)

#define	NVIC_IP_PRI104_MASK 0xFFu

#define	NVIC_IP_PRI104_SHIFT 0

#define	NVIC_IP_PRI104(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI104_SHIFT))&NVIC_IP_PRI104_MASK)

#define	NVIC_IP_PRI105_MASK 0xFFu

#define	NVIC_IP_PRI105_SHIFT 0

#define	NVIC_IP_PRI105(x) (((uint8_t)(((uint8_t)(x))<<NVIC_IP_PRI105_SHIFT))&NVIC_IP_PRI105_MASK)

#define	NVIC_STIR_INTID_MASK 0x1FFu

#define	NVIC_STIR_INTID_SHIFT 0

#define	NVIC_STIR_INTID(x) (((uint32_t)(((uint32_t)(x))<<NVIC_STIR_INTID_SHIFT))&NVIC_STIR_INTID_MASK)

#define	NVIC_BASE_PTR ((NVIC_MemMapPtr)0xE000E100u)

#define	NVIC_BASE_PTRS { NVIC_BASE_PTR }

#define	NVICISER0 NVIC_ISER_REG(NVIC_BASE_PTR,0)

#define	NVICISER1 NVIC_ISER_REG(NVIC_BASE_PTR,1)

#define	NVICISER2 NVIC_ISER_REG(NVIC_BASE_PTR,2)

#define	NVICISER3 NVIC_ISER_REG(NVIC_BASE_PTR,3)

#define	NVICICER0 NVIC_ICER_REG(NVIC_BASE_PTR,0)

#define	NVICICER1 NVIC_ICER_REG(NVIC_BASE_PTR,1)

#define	NVICICER2 NVIC_ICER_REG(NVIC_BASE_PTR,2)

#define	NVICICER3 NVIC_ICER_REG(NVIC_BASE_PTR,3)

#define	NVICISPR0 NVIC_ISPR_REG(NVIC_BASE_PTR,0)

#define	NVICISPR1 NVIC_ISPR_REG(NVIC_BASE_PTR,1)

#define	NVICISPR2 NVIC_ISPR_REG(NVIC_BASE_PTR,2)

#define	NVICISPR3 NVIC_ISPR_REG(NVIC_BASE_PTR,3)

#define	NVICICPR0 NVIC_ICPR_REG(NVIC_BASE_PTR,0)

#define	NVICICPR1 NVIC_ICPR_REG(NVIC_BASE_PTR,1)

#define	NVICICPR2 NVIC_ICPR_REG(NVIC_BASE_PTR,2)

#define	NVICICPR3 NVIC_ICPR_REG(NVIC_BASE_PTR,3)

#define	NVICIABR0 NVIC_IABR_REG(NVIC_BASE_PTR,0)

#define	NVICIABR1 NVIC_IABR_REG(NVIC_BASE_PTR,1)

#define	NVICIABR2 NVIC_IABR_REG(NVIC_BASE_PTR,2)

#define	NVICIABR3 NVIC_IABR_REG(NVIC_BASE_PTR,3)

#define	NVICIP0 NVIC_IP_REG(NVIC_BASE_PTR,0)

#define	NVICIP1 NVIC_IP_REG(NVIC_BASE_PTR,1)

#define	NVICIP2 NVIC_IP_REG(NVIC_BASE_PTR,2)

#define	NVICIP3 NVIC_IP_REG(NVIC_BASE_PTR,3)

#define	NVICIP4 NVIC_IP_REG(NVIC_BASE_PTR,4)

#define	NVICIP5 NVIC_IP_REG(NVIC_BASE_PTR,5)

#define	NVICIP6 NVIC_IP_REG(NVIC_BASE_PTR,6)

#define	NVICIP7 NVIC_IP_REG(NVIC_BASE_PTR,7)

#define	NVICIP8 NVIC_IP_REG(NVIC_BASE_PTR,8)

#define	NVICIP9 NVIC_IP_REG(NVIC_BASE_PTR,9)

#define	NVICIP10 NVIC_IP_REG(NVIC_BASE_PTR,10)

#define	NVICIP11 NVIC_IP_REG(NVIC_BASE_PTR,11)

#define	NVICIP12 NVIC_IP_REG(NVIC_BASE_PTR,12)

#define	NVICIP13 NVIC_IP_REG(NVIC_BASE_PTR,13)

#define	NVICIP14 NVIC_IP_REG(NVIC_BASE_PTR,14)

#define	NVICIP15 NVIC_IP_REG(NVIC_BASE_PTR,15)

#define	NVICIP16 NVIC_IP_REG(NVIC_BASE_PTR,16)

#define	NVICIP17 NVIC_IP_REG(NVIC_BASE_PTR,17)

#define	NVICIP18 NVIC_IP_REG(NVIC_BASE_PTR,18)

#define	NVICIP19 NVIC_IP_REG(NVIC_BASE_PTR,19)

#define	NVICIP20 NVIC_IP_REG(NVIC_BASE_PTR,20)

#define	NVICIP21 NVIC_IP_REG(NVIC_BASE_PTR,21)

#define	NVICIP22 NVIC_IP_REG(NVIC_BASE_PTR,22)

#define	NVICIP23 NVIC_IP_REG(NVIC_BASE_PTR,23)

#define	NVICIP24 NVIC_IP_REG(NVIC_BASE_PTR,24)

#define	NVICIP25 NVIC_IP_REG(NVIC_BASE_PTR,25)

#define	NVICIP26 NVIC_IP_REG(NVIC_BASE_PTR,26)

#define	NVICIP27 NVIC_IP_REG(NVIC_BASE_PTR,27)

#define	NVICIP28 NVIC_IP_REG(NVIC_BASE_PTR,28)

#define	NVICIP29 NVIC_IP_REG(NVIC_BASE_PTR,29)

#define	NVICIP30 NVIC_IP_REG(NVIC_BASE_PTR,30)

#define	NVICIP31 NVIC_IP_REG(NVIC_BASE_PTR,31)

#define	NVICIP32 NVIC_IP_REG(NVIC_BASE_PTR,32)

#define	NVICIP33 NVIC_IP_REG(NVIC_BASE_PTR,33)

#define	NVICIP34 NVIC_IP_REG(NVIC_BASE_PTR,34)

#define	NVICIP35 NVIC_IP_REG(NVIC_BASE_PTR,35)

#define	NVICIP36 NVIC_IP_REG(NVIC_BASE_PTR,36)

#define	NVICIP37 NVIC_IP_REG(NVIC_BASE_PTR,37)

#define	NVICIP38 NVIC_IP_REG(NVIC_BASE_PTR,38)

#define	NVICIP39 NVIC_IP_REG(NVIC_BASE_PTR,39)

#define	NVICIP40 NVIC_IP_REG(NVIC_BASE_PTR,40)

#define	NVICIP41 NVIC_IP_REG(NVIC_BASE_PTR,41)

#define	NVICIP42 NVIC_IP_REG(NVIC_BASE_PTR,42)

#define	NVICIP43 NVIC_IP_REG(NVIC_BASE_PTR,43)

#define	NVICIP44 NVIC_IP_REG(NVIC_BASE_PTR,44)

#define	NVICIP45 NVIC_IP_REG(NVIC_BASE_PTR,45)

#define	NVICIP46 NVIC_IP_REG(NVIC_BASE_PTR,46)

#define	NVICIP47 NVIC_IP_REG(NVIC_BASE_PTR,47)

#define	NVICIP48 NVIC_IP_REG(NVIC_BASE_PTR,48)

#define	NVICIP49 NVIC_IP_REG(NVIC_BASE_PTR,49)

#define	NVICIP50 NVIC_IP_REG(NVIC_BASE_PTR,50)

#define	NVICIP51 NVIC_IP_REG(NVIC_BASE_PTR,51)

#define	NVICIP52 NVIC_IP_REG(NVIC_BASE_PTR,52)

#define	NVICIP53 NVIC_IP_REG(NVIC_BASE_PTR,53)

#define	NVICIP54 NVIC_IP_REG(NVIC_BASE_PTR,54)

#define	NVICIP55 NVIC_IP_REG(NVIC_BASE_PTR,55)

#define	NVICIP56 NVIC_IP_REG(NVIC_BASE_PTR,56)

#define	NVICIP57 NVIC_IP_REG(NVIC_BASE_PTR,57)

#define	NVICIP58 NVIC_IP_REG(NVIC_BASE_PTR,58)

#define	NVICIP59 NVIC_IP_REG(NVIC_BASE_PTR,59)

#define	NVICIP60 NVIC_IP_REG(NVIC_BASE_PTR,60)

#define	NVICIP61 NVIC_IP_REG(NVIC_BASE_PTR,61)

#define	NVICIP62 NVIC_IP_REG(NVIC_BASE_PTR,62)

#define	NVICIP63 NVIC_IP_REG(NVIC_BASE_PTR,63)

#define	NVICIP64 NVIC_IP_REG(NVIC_BASE_PTR,64)

#define	NVICIP65 NVIC_IP_REG(NVIC_BASE_PTR,65)

#define	NVICIP66 NVIC_IP_REG(NVIC_BASE_PTR,66)

#define	NVICIP67 NVIC_IP_REG(NVIC_BASE_PTR,67)

#define	NVICIP68 NVIC_IP_REG(NVIC_BASE_PTR,68)

#define	NVICIP69 NVIC_IP_REG(NVIC_BASE_PTR,69)

#define	NVICIP70 NVIC_IP_REG(NVIC_BASE_PTR,70)

#define	NVICIP71 NVIC_IP_REG(NVIC_BASE_PTR,71)

#define	NVICIP72 NVIC_IP_REG(NVIC_BASE_PTR,72)

#define	NVICIP73 NVIC_IP_REG(NVIC_BASE_PTR,73)

#define	NVICIP74 NVIC_IP_REG(NVIC_BASE_PTR,74)

#define	NVICIP75 NVIC_IP_REG(NVIC_BASE_PTR,75)

#define	NVICIP76 NVIC_IP_REG(NVIC_BASE_PTR,76)

#define	NVICIP77 NVIC_IP_REG(NVIC_BASE_PTR,77)

#define	NVICIP78 NVIC_IP_REG(NVIC_BASE_PTR,78)

#define	NVICIP79 NVIC_IP_REG(NVIC_BASE_PTR,79)

#define	NVICIP80 NVIC_IP_REG(NVIC_BASE_PTR,80)

#define	NVICIP81 NVIC_IP_REG(NVIC_BASE_PTR,81)

#define	NVICIP82 NVIC_IP_REG(NVIC_BASE_PTR,82)

#define	NVICIP83 NVIC_IP_REG(NVIC_BASE_PTR,83)

#define	NVICIP84 NVIC_IP_REG(NVIC_BASE_PTR,84)

#define	NVICIP85 NVIC_IP_REG(NVIC_BASE_PTR,85)

#define	NVICIP86 NVIC_IP_REG(NVIC_BASE_PTR,86)

#define	NVICIP87 NVIC_IP_REG(NVIC_BASE_PTR,87)

#define	NVICIP88 NVIC_IP_REG(NVIC_BASE_PTR,88)

#define	NVICIP89 NVIC_IP_REG(NVIC_BASE_PTR,89)

#define	NVICIP90 NVIC_IP_REG(NVIC_BASE_PTR,90)

#define	NVICIP91 NVIC_IP_REG(NVIC_BASE_PTR,91)

#define	NVICIP92 NVIC_IP_REG(NVIC_BASE_PTR,92)

#define	NVICIP93 NVIC_IP_REG(NVIC_BASE_PTR,93)

#define	NVICIP94 NVIC_IP_REG(NVIC_BASE_PTR,94)

#define	NVICIP95 NVIC_IP_REG(NVIC_BASE_PTR,95)

#define	NVICIP96 NVIC_IP_REG(NVIC_BASE_PTR,96)

#define	NVICIP97 NVIC_IP_REG(NVIC_BASE_PTR,97)

#define	NVICIP98 NVIC_IP_REG(NVIC_BASE_PTR,98)

#define	NVICIP99 NVIC_IP_REG(NVIC_BASE_PTR,99)

#define	NVICIP100 NVIC_IP_REG(NVIC_BASE_PTR,100)

#define	NVICIP101 NVIC_IP_REG(NVIC_BASE_PTR,101)

#define	NVICIP102 NVIC_IP_REG(NVIC_BASE_PTR,102)

#define	NVICIP103 NVIC_IP_REG(NVIC_BASE_PTR,103)

#define	NVICIP104 NVIC_IP_REG(NVIC_BASE_PTR,104)

#define	NVICIP105 NVIC_IP_REG(NVIC_BASE_PTR,105)

#define	NVICSTIR NVIC_STIR_REG(NVIC_BASE_PTR,0)

#define	NVIC_ISER(index) NVIC_ISER_REG(NVIC_BASE_PTR,index)

#define	NVIC_ICER(index) NVIC_ICER_REG(NVIC_BASE_PTR,index)

#define	NVIC_ISPR(index) NVIC_ISPR_REG(NVIC_BASE_PTR,index)

#define	NVIC_ICPR(index) NVIC_ICPR_REG(NVIC_BASE_PTR,index)

#define	NVIC_IABR(index) NVIC_IABR_REG(NVIC_BASE_PTR,index)

#define	NVIC_IP(index) NVIC_IP_REG(NVIC_BASE_PTR,index)

#define	NVIC_STIR(index) NVIC_STIR_REG(NVIC_BASE_PTR,index)

#define	OSC_CR_REG(base) ((base)->CR)

#define	OSC_CR_SC16P_MASK 0x1u

#define	OSC_CR_SC16P_SHIFT 0

#define	OSC_CR_SC8P_MASK 0x2u

#define	OSC_CR_SC8P_SHIFT 1

#define	OSC_CR_SC4P_MASK 0x4u

#define	OSC_CR_SC4P_SHIFT 2

#define	OSC_CR_SC2P_MASK 0x8u

#define	OSC_CR_SC2P_SHIFT 3

#define	OSC_CR_EREFSTEN_MASK 0x20u

#define	OSC_CR_EREFSTEN_SHIFT 5

#define	OSC_CR_ERCLKEN_MASK 0x80u

#define	OSC_CR_ERCLKEN_SHIFT 7

#define	OSC0_BASE_PTR ((OSC_MemMapPtr)0x40065000u)

#define	OSC1_BASE_PTR ((OSC_MemMapPtr)0x400E5000u)

#define	OSC_BASE_PTRS { OSC0_BASE_PTR, OSC1_BASE_PTR }

#define	OSC0_CR OSC_CR_REG(OSC0_BASE_PTR)

#define	OSC1_CR OSC_CR_REG(OSC1_BASE_PTR)

#define	PDB_SC_REG(base) ((base)->SC)

#define	PDB_MOD_REG(base) ((base)->MOD)

#define	PDB_CNT_REG(base) ((base)->CNT)

#define	PDB_IDLY_REG(base) ((base)->IDLY)

#define	PDB_C1_REG(base, index) ((base)->CH[index].C1)

#define	PDB_S_REG(base, index) ((base)->CH[index].S)

#define	PDB_DLY_REG(base, index, index2) ((base)->CH[index].DLY[index2])

#define	PDB_INTC_REG(base, index) ((base)->DAC[index].INTC)

#define	PDB_INT_REG(base, index) ((base)->DAC[index].INT)

#define	PDB_POEN_REG(base) ((base)->POEN)

#define	PDB_PODLY_REG(base, index) ((base)->PODLY[index])

#define	PDB_SC_LDOK_MASK 0x1u

#define	PDB_SC_LDOK_SHIFT 0

#define	PDB_SC_CONT_MASK 0x2u

#define	PDB_SC_CONT_SHIFT 1

#define	PDB_SC_MULT_MASK 0xCu

#define	PDB_SC_MULT_SHIFT 2

#define	PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)

#define	PDB_SC_PDBIE_MASK 0x20u

#define	PDB_SC_PDBIE_SHIFT 5

#define	PDB_SC_PDBIF_MASK 0x40u

#define	PDB_SC_PDBIF_SHIFT 6

#define	PDB_SC_PDBEN_MASK 0x80u

#define	PDB_SC_PDBEN_SHIFT 7

#define	PDB_SC_TRGSEL_MASK 0xF00u

#define	PDB_SC_TRGSEL_SHIFT 8

#define	PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)

#define	PDB_SC_PRESCALER_MASK 0x7000u

#define	PDB_SC_PRESCALER_SHIFT 12

#define	PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)

#define	PDB_SC_DMAEN_MASK 0x8000u

#define	PDB_SC_DMAEN_SHIFT 15

#define	PDB_SC_SWTRIG_MASK 0x10000u

#define	PDB_SC_SWTRIG_SHIFT 16

#define	PDB_SC_PDBEIE_MASK 0x20000u

#define	PDB_SC_PDBEIE_SHIFT 17

#define	PDB_SC_LDMOD_MASK 0xC0000u

#define	PDB_SC_LDMOD_SHIFT 18

#define	PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)

#define	PDB_MOD_MOD_MASK 0xFFFFu

#define	PDB_MOD_MOD_SHIFT 0

#define	PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)

#define	PDB_CNT_CNT_MASK 0xFFFFu

#define	PDB_CNT_CNT_SHIFT 0

#define	PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)

#define	PDB_IDLY_IDLY_MASK 0xFFFFu

#define	PDB_IDLY_IDLY_SHIFT 0

#define	PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)

#define	PDB_C1_EN_MASK 0xFFu

#define	PDB_C1_EN_SHIFT 0

#define	PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)

#define	PDB_C1_TOS_MASK 0xFF00u

#define	PDB_C1_TOS_SHIFT 8

#define	PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)

#define	PDB_C1_BB_MASK 0xFF0000u

#define	PDB_C1_BB_SHIFT 16

#define	PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)

#define	PDB_S_ERR_MASK 0xFFu

#define	PDB_S_ERR_SHIFT 0

#define	PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)

#define	PDB_S_CF_MASK 0xFF0000u

#define	PDB_S_CF_SHIFT 16

#define	PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)

#define	PDB_DLY_DLY_MASK 0xFFFFu

#define	PDB_DLY_DLY_SHIFT 0

#define	PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)

#define	PDB_INTC_TOE_MASK 0x1u

#define	PDB_INTC_TOE_SHIFT 0

#define	PDB_INTC_EXT_MASK 0x2u

#define	PDB_INTC_EXT_SHIFT 1

#define	PDB_INT_INT_MASK 0xFFFFu

#define	PDB_INT_INT_SHIFT 0

#define	PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)

#define	PDB_POEN_POEN_MASK 0xFFu

#define	PDB_POEN_POEN_SHIFT 0

#define	PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)

#define	PDB_PODLY_DLY2_MASK 0xFFFFu

#define	PDB_PODLY_DLY2_SHIFT 0

#define	PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)

#define	PDB_PODLY_DLY1_MASK 0xFFFF0000u

#define	PDB_PODLY_DLY1_SHIFT 16

#define	PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)

#define	PDB0_BASE_PTR ((PDB_MemMapPtr)0x40036000u)

#define	PDB_BASE_PTRS { PDB0_BASE_PTR }

#define	PDB0_SC PDB_SC_REG(PDB0_BASE_PTR)

#define	PDB0_MOD PDB_MOD_REG(PDB0_BASE_PTR)

#define	PDB0_CNT PDB_CNT_REG(PDB0_BASE_PTR)

#define	PDB0_IDLY PDB_IDLY_REG(PDB0_BASE_PTR)

#define	PDB0_CH0C1 PDB_C1_REG(PDB0_BASE_PTR,0)

#define	PDB0_CH0S PDB_S_REG(PDB0_BASE_PTR,0)

#define	PDB0_CH0DLY0 PDB_DLY_REG(PDB0_BASE_PTR,0,0)

#define	PDB0_CH0DLY1 PDB_DLY_REG(PDB0_BASE_PTR,0,1)

#define	PDB0_CH1C1 PDB_C1_REG(PDB0_BASE_PTR,1)

#define	PDB0_CH1S PDB_S_REG(PDB0_BASE_PTR,1)

#define	PDB0_CH1DLY0 PDB_DLY_REG(PDB0_BASE_PTR,1,0)

#define	PDB0_CH1DLY1 PDB_DLY_REG(PDB0_BASE_PTR,1,1)

#define	PDB0_CH2C1 PDB_C1_REG(PDB0_BASE_PTR,2)

#define	PDB0_CH2S PDB_S_REG(PDB0_BASE_PTR,2)

#define	PDB0_CH2DLY0 PDB_DLY_REG(PDB0_BASE_PTR,2,0)

#define	PDB0_CH2DLY1 PDB_DLY_REG(PDB0_BASE_PTR,2,1)

#define	PDB0_CH3C1 PDB_C1_REG(PDB0_BASE_PTR,3)

#define	PDB0_CH3S PDB_S_REG(PDB0_BASE_PTR,3)

#define	PDB0_CH3DLY0 PDB_DLY_REG(PDB0_BASE_PTR,3,0)

#define	PDB0_CH3DLY1 PDB_DLY_REG(PDB0_BASE_PTR,3,1)

#define	PDB0_DACINTC0 PDB_INTC_REG(PDB0_BASE_PTR,0)

#define	PDB0_DACINT0 PDB_INT_REG(PDB0_BASE_PTR,0)

#define	PDB0_DACINTC1 PDB_INTC_REG(PDB0_BASE_PTR,1)

#define	PDB0_DACINT1 PDB_INT_REG(PDB0_BASE_PTR,1)

#define	PDB0_POEN PDB_POEN_REG(PDB0_BASE_PTR)

#define	PDB0_PO0DLY PDB_PODLY_REG(PDB0_BASE_PTR,0)

#define	PDB0_PO1DLY PDB_PODLY_REG(PDB0_BASE_PTR,1)

#define	PDB0_PO2DLY PDB_PODLY_REG(PDB0_BASE_PTR,2)

#define	PDB0_PO3DLY PDB_PODLY_REG(PDB0_BASE_PTR,3)

#define	PDB0_C1(index) PDB_C1_REG(PDB0_BASE_PTR,index)

#define	PDB0_S(index) PDB_S_REG(PDB0_BASE_PTR,index)

#define	PDB0_DLY(index, index2) PDB_DLY_REG(PDB0_BASE_PTR,index,index2)

#define	PDB0_INTC(index) PDB_INTC_REG(PDB0_BASE_PTR,index)

#define	PDB0_INT(index) PDB_INT_REG(PDB0_BASE_PTR,index)

#define	PDB0_PODLY(index) PDB_PODLY_REG(PDB0_BASE_PTR,index)

#define	PIT_MCR_REG(base) ((base)->MCR)

#define	PIT_LDVAL_REG(base, index) ((base)->CHANNEL[index].LDVAL)

#define	PIT_CVAL_REG(base, index) ((base)->CHANNEL[index].CVAL)

#define	PIT_TCTRL_REG(base, index) ((base)->CHANNEL[index].TCTRL)

#define	PIT_TFLG_REG(base, index) ((base)->CHANNEL[index].TFLG)

#define	PIT_MCR_FRZ_MASK 0x1u

#define	PIT_MCR_FRZ_SHIFT 0

#define	PIT_MCR_MDIS_MASK 0x2u

#define	PIT_MCR_MDIS_SHIFT 1

#define	PIT_LDVAL_TSV_MASK 0xFFFFFFFFu

#define	PIT_LDVAL_TSV_SHIFT 0

#define	PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)

#define	PIT_CVAL_TVL_MASK 0xFFFFFFFFu

#define	PIT_CVAL_TVL_SHIFT 0

#define	PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)

#define	PIT_TCTRL_TEN_MASK 0x1u

#define	PIT_TCTRL_TEN_SHIFT 0

#define	PIT_TCTRL_TIE_MASK 0x2u

#define	PIT_TCTRL_TIE_SHIFT 1

#define	PIT_TFLG_TIF_MASK 0x1u

#define	PIT_TFLG_TIF_SHIFT 0

#define	PIT_BASE_PTR ((PIT_MemMapPtr)0x40037000u)

#define	PIT_BASE_PTRS { PIT_BASE_PTR }

#define	PIT_MCR PIT_MCR_REG(PIT_BASE_PTR)

#define	PIT_LDVAL0 PIT_LDVAL_REG(PIT_BASE_PTR,0)

#define	PIT_CVAL0 PIT_CVAL_REG(PIT_BASE_PTR,0)

#define	PIT_TCTRL0 PIT_TCTRL_REG(PIT_BASE_PTR,0)

#define	PIT_TFLG0 PIT_TFLG_REG(PIT_BASE_PTR,0)

#define	PIT_LDVAL1 PIT_LDVAL_REG(PIT_BASE_PTR,1)

#define	PIT_CVAL1 PIT_CVAL_REG(PIT_BASE_PTR,1)

#define	PIT_TCTRL1 PIT_TCTRL_REG(PIT_BASE_PTR,1)

#define	PIT_TFLG1 PIT_TFLG_REG(PIT_BASE_PTR,1)

#define	PIT_LDVAL2 PIT_LDVAL_REG(PIT_BASE_PTR,2)

#define	PIT_CVAL2 PIT_CVAL_REG(PIT_BASE_PTR,2)

#define	PIT_TCTRL2 PIT_TCTRL_REG(PIT_BASE_PTR,2)

#define	PIT_TFLG2 PIT_TFLG_REG(PIT_BASE_PTR,2)

#define	PIT_LDVAL3 PIT_LDVAL_REG(PIT_BASE_PTR,3)

#define	PIT_CVAL3 PIT_CVAL_REG(PIT_BASE_PTR,3)

#define	PIT_TCTRL3 PIT_TCTRL_REG(PIT_BASE_PTR,3)

#define	PIT_TFLG3 PIT_TFLG_REG(PIT_BASE_PTR,3)

#define	PIT_LDVAL(index) PIT_LDVAL_REG(PIT_BASE_PTR,index)

#define	PIT_CVAL(index) PIT_CVAL_REG(PIT_BASE_PTR,index)

#define	PIT_TCTRL(index) PIT_TCTRL_REG(PIT_BASE_PTR,index)

#define	PIT_TFLG(index) PIT_TFLG_REG(PIT_BASE_PTR,index)

#define	PMC_LVDSC1_REG(base) ((base)->LVDSC1)

#define	PMC_LVDSC2_REG(base) ((base)->LVDSC2)

#define	PMC_REGSC_REG(base) ((base)->REGSC)

#define	PMC_LVDSC1_LVDV_MASK 0x3u

#define	PMC_LVDSC1_LVDV_SHIFT 0

#define	PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)

#define	PMC_LVDSC1_LVDRE_MASK 0x10u

#define	PMC_LVDSC1_LVDRE_SHIFT 4

#define	PMC_LVDSC1_LVDIE_MASK 0x20u

#define	PMC_LVDSC1_LVDIE_SHIFT 5

#define	PMC_LVDSC1_LVDACK_MASK 0x40u

#define	PMC_LVDSC1_LVDACK_SHIFT 6

#define	PMC_LVDSC1_LVDF_MASK 0x80u

#define	PMC_LVDSC1_LVDF_SHIFT 7

#define	PMC_LVDSC2_LVWV_MASK 0x3u

#define	PMC_LVDSC2_LVWV_SHIFT 0

#define	PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)

#define	PMC_LVDSC2_LVWIE_MASK 0x20u

#define	PMC_LVDSC2_LVWIE_SHIFT 5

#define	PMC_LVDSC2_LVWACK_MASK 0x40u

#define	PMC_LVDSC2_LVWACK_SHIFT 6

#define	PMC_LVDSC2_LVWF_MASK 0x80u

#define	PMC_LVDSC2_LVWF_SHIFT 7

#define	PMC_REGSC_BGBE_MASK 0x1u

#define	PMC_REGSC_BGBE_SHIFT 0

#define	PMC_REGSC_REGONS_MASK 0x4u

#define	PMC_REGSC_REGONS_SHIFT 2

#define	PMC_REGSC_ACKISO_MASK 0x8u

#define	PMC_REGSC_ACKISO_SHIFT 3

#define	PMC_BASE_PTR ((PMC_MemMapPtr)0x4007D000u)

#define	PMC_BASE_PTRS { PMC_BASE_PTR }

#define	PMC_LVDSC1 PMC_LVDSC1_REG(PMC_BASE_PTR)

#define	PMC_LVDSC2 PMC_LVDSC2_REG(PMC_BASE_PTR)

#define	PMC_REGSC PMC_REGSC_REG(PMC_BASE_PTR)

#define	PORT_PCR_REG(base, index) ((base)->PCR[index])

#define	PORT_GPCLR_REG(base) ((base)->GPCLR)

#define	PORT_GPCHR_REG(base) ((base)->GPCHR)

#define	PORT_ISFR_REG(base) ((base)->ISFR)

#define	PORT_DFER_REG(base) ((base)->DFER)

#define	PORT_DFCR_REG(base) ((base)->DFCR)

#define	PORT_DFWR_REG(base) ((base)->DFWR)

#define	PORT_PCR_PS_MASK 0x1u

#define	PORT_PCR_PS_SHIFT 0

#define	PORT_PCR_PE_MASK 0x2u

#define	PORT_PCR_PE_SHIFT 1

#define	PORT_PCR_SRE_MASK 0x4u

#define	PORT_PCR_SRE_SHIFT 2

#define	PORT_PCR_PFE_MASK 0x10u

#define	PORT_PCR_PFE_SHIFT 4

#define	PORT_PCR_ODE_MASK 0x20u

#define	PORT_PCR_ODE_SHIFT 5

#define	PORT_PCR_DSE_MASK 0x40u

#define	PORT_PCR_DSE_SHIFT 6

#define	PORT_PCR_MUX_MASK 0x700u

#define	PORT_PCR_MUX_SHIFT 8

#define	PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)

#define	PORT_PCR_LK_MASK 0x8000u

#define	PORT_PCR_LK_SHIFT 15

#define	PORT_PCR_IRQC_MASK 0xF0000u

#define	PORT_PCR_IRQC_SHIFT 16

#define	PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)

#define	PORT_PCR_ISF_MASK 0x1000000u

#define	PORT_PCR_ISF_SHIFT 24

#define	PORT_GPCLR_GPWD_MASK 0xFFFFu

#define	PORT_GPCLR_GPWD_SHIFT 0

#define	PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)

#define	PORT_GPCLR_GPWE_MASK 0xFFFF0000u

#define	PORT_GPCLR_GPWE_SHIFT 16

#define	PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)

#define	PORT_GPCHR_GPWD_MASK 0xFFFFu

#define	PORT_GPCHR_GPWD_SHIFT 0

#define	PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)

#define	PORT_GPCHR_GPWE_MASK 0xFFFF0000u

#define	PORT_GPCHR_GPWE_SHIFT 16

#define	PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)

#define	PORT_ISFR_ISF_MASK 0xFFFFFFFFu

#define	PORT_ISFR_ISF_SHIFT 0

#define	PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)

#define	PORT_DFER_DFE_MASK 0xFFFFFFFFu

#define	PORT_DFER_DFE_SHIFT 0

#define	PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)

#define	PORT_DFCR_CS_MASK 0x1u

#define	PORT_DFCR_CS_SHIFT 0

#define	PORT_DFWR_FILT_MASK 0x1Fu

#define	PORT_DFWR_FILT_SHIFT 0

#define	PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)

#define	PORTA_BASE_PTR ((PORT_MemMapPtr)0x40049000u)

#define	PORTB_BASE_PTR ((PORT_MemMapPtr)0x4004A000u)

#define	PORTC_BASE_PTR ((PORT_MemMapPtr)0x4004B000u)

#define	PORTD_BASE_PTR ((PORT_MemMapPtr)0x4004C000u)

#define	PORTE_BASE_PTR ((PORT_MemMapPtr)0x4004D000u)

#define	PORTF_BASE_PTR ((PORT_MemMapPtr)0x4004E000u)

#define	PORT_BASE_PTRS { PORTA_BASE_PTR, PORTB_BASE_PTR, PORTC_BASE_PTR, PORTD_BASE_PTR, PORTE_BASE_PTR, PORTF_BASE_PTR }

#define	PORTA_PCR0 PORT_PCR_REG(PORTA_BASE_PTR,0)

#define	PORTA_PCR1 PORT_PCR_REG(PORTA_BASE_PTR,1)

#define	PORTA_PCR2 PORT_PCR_REG(PORTA_BASE_PTR,2)

#define	PORTA_PCR3 PORT_PCR_REG(PORTA_BASE_PTR,3)

#define	PORTA_PCR4 PORT_PCR_REG(PORTA_BASE_PTR,4)

#define	PORTA_PCR5 PORT_PCR_REG(PORTA_BASE_PTR,5)

#define	PORTA_PCR6 PORT_PCR_REG(PORTA_BASE_PTR,6)

#define	PORTA_PCR7 PORT_PCR_REG(PORTA_BASE_PTR,7)

#define	PORTA_PCR8 PORT_PCR_REG(PORTA_BASE_PTR,8)

#define	PORTA_PCR9 PORT_PCR_REG(PORTA_BASE_PTR,9)

#define	PORTA_PCR10 PORT_PCR_REG(PORTA_BASE_PTR,10)

#define	PORTA_PCR11 PORT_PCR_REG(PORTA_BASE_PTR,11)

#define	PORTA_PCR12 PORT_PCR_REG(PORTA_BASE_PTR,12)

#define	PORTA_PCR13 PORT_PCR_REG(PORTA_BASE_PTR,13)

#define	PORTA_PCR14 PORT_PCR_REG(PORTA_BASE_PTR,14)

#define	PORTA_PCR15 PORT_PCR_REG(PORTA_BASE_PTR,15)

#define	PORTA_PCR16 PORT_PCR_REG(PORTA_BASE_PTR,16)

#define	PORTA_PCR17 PORT_PCR_REG(PORTA_BASE_PTR,17)

#define	PORTA_PCR18 PORT_PCR_REG(PORTA_BASE_PTR,18)

#define	PORTA_PCR19 PORT_PCR_REG(PORTA_BASE_PTR,19)

#define	PORTA_PCR20 PORT_PCR_REG(PORTA_BASE_PTR,20)

#define	PORTA_PCR21 PORT_PCR_REG(PORTA_BASE_PTR,21)

#define	PORTA_PCR22 PORT_PCR_REG(PORTA_BASE_PTR,22)

#define	PORTA_PCR23 PORT_PCR_REG(PORTA_BASE_PTR,23)

#define	PORTA_PCR24 PORT_PCR_REG(PORTA_BASE_PTR,24)

#define	PORTA_PCR25 PORT_PCR_REG(PORTA_BASE_PTR,25)

#define	PORTA_PCR26 PORT_PCR_REG(PORTA_BASE_PTR,26)

#define	PORTA_PCR27 PORT_PCR_REG(PORTA_BASE_PTR,27)

#define	PORTA_PCR28 PORT_PCR_REG(PORTA_BASE_PTR,28)

#define	PORTA_PCR29 PORT_PCR_REG(PORTA_BASE_PTR,29)

#define	PORTA_PCR30 PORT_PCR_REG(PORTA_BASE_PTR,30)

#define	PORTA_PCR31 PORT_PCR_REG(PORTA_BASE_PTR,31)

#define	PORTA_GPCLR PORT_GPCLR_REG(PORTA_BASE_PTR)

#define	PORTA_GPCHR PORT_GPCHR_REG(PORTA_BASE_PTR)

#define	PORTA_ISFR PORT_ISFR_REG(PORTA_BASE_PTR)

#define	PORTA_DFER PORT_DFER_REG(PORTA_BASE_PTR)

#define	PORTA_DFCR PORT_DFCR_REG(PORTA_BASE_PTR)

#define	PORTA_DFWR PORT_DFWR_REG(PORTA_BASE_PTR)

#define	PORTB_PCR0 PORT_PCR_REG(PORTB_BASE_PTR,0)

#define	PORTB_PCR1 PORT_PCR_REG(PORTB_BASE_PTR,1)

#define	PORTB_PCR2 PORT_PCR_REG(PORTB_BASE_PTR,2)

#define	PORTB_PCR3 PORT_PCR_REG(PORTB_BASE_PTR,3)

#define	PORTB_PCR4 PORT_PCR_REG(PORTB_BASE_PTR,4)

#define	PORTB_PCR5 PORT_PCR_REG(PORTB_BASE_PTR,5)

#define	PORTB_PCR6 PORT_PCR_REG(PORTB_BASE_PTR,6)

#define	PORTB_PCR7 PORT_PCR_REG(PORTB_BASE_PTR,7)

#define	PORTB_PCR8 PORT_PCR_REG(PORTB_BASE_PTR,8)

#define	PORTB_PCR9 PORT_PCR_REG(PORTB_BASE_PTR,9)

#define	PORTB_PCR10 PORT_PCR_REG(PORTB_BASE_PTR,10)

#define	PORTB_PCR11 PORT_PCR_REG(PORTB_BASE_PTR,11)

#define	PORTB_PCR12 PORT_PCR_REG(PORTB_BASE_PTR,12)

#define	PORTB_PCR13 PORT_PCR_REG(PORTB_BASE_PTR,13)

#define	PORTB_PCR14 PORT_PCR_REG(PORTB_BASE_PTR,14)

#define	PORTB_PCR15 PORT_PCR_REG(PORTB_BASE_PTR,15)

#define	PORTB_PCR16 PORT_PCR_REG(PORTB_BASE_PTR,16)

#define	PORTB_PCR17 PORT_PCR_REG(PORTB_BASE_PTR,17)

#define	PORTB_PCR18 PORT_PCR_REG(PORTB_BASE_PTR,18)

#define	PORTB_PCR19 PORT_PCR_REG(PORTB_BASE_PTR,19)

#define	PORTB_PCR20 PORT_PCR_REG(PORTB_BASE_PTR,20)

#define	PORTB_PCR21 PORT_PCR_REG(PORTB_BASE_PTR,21)

#define	PORTB_PCR22 PORT_PCR_REG(PORTB_BASE_PTR,22)

#define	PORTB_PCR23 PORT_PCR_REG(PORTB_BASE_PTR,23)

#define	PORTB_PCR24 PORT_PCR_REG(PORTB_BASE_PTR,24)

#define	PORTB_PCR25 PORT_PCR_REG(PORTB_BASE_PTR,25)

#define	PORTB_PCR26 PORT_PCR_REG(PORTB_BASE_PTR,26)

#define	PORTB_PCR27 PORT_PCR_REG(PORTB_BASE_PTR,27)

#define	PORTB_PCR28 PORT_PCR_REG(PORTB_BASE_PTR,28)

#define	PORTB_PCR29 PORT_PCR_REG(PORTB_BASE_PTR,29)

#define	PORTB_PCR30 PORT_PCR_REG(PORTB_BASE_PTR,30)

#define	PORTB_PCR31 PORT_PCR_REG(PORTB_BASE_PTR,31)

#define	PORTB_GPCLR PORT_GPCLR_REG(PORTB_BASE_PTR)

#define	PORTB_GPCHR PORT_GPCHR_REG(PORTB_BASE_PTR)

#define	PORTB_ISFR PORT_ISFR_REG(PORTB_BASE_PTR)

#define	PORTB_DFER PORT_DFER_REG(PORTB_BASE_PTR)

#define	PORTB_DFCR PORT_DFCR_REG(PORTB_BASE_PTR)

#define	PORTB_DFWR PORT_DFWR_REG(PORTB_BASE_PTR)

#define	PORTC_PCR0 PORT_PCR_REG(PORTC_BASE_PTR,0)

#define	PORTC_PCR1 PORT_PCR_REG(PORTC_BASE_PTR,1)

#define	PORTC_PCR2 PORT_PCR_REG(PORTC_BASE_PTR,2)

#define	PORTC_PCR3 PORT_PCR_REG(PORTC_BASE_PTR,3)

#define	PORTC_PCR4 PORT_PCR_REG(PORTC_BASE_PTR,4)

#define	PORTC_PCR5 PORT_PCR_REG(PORTC_BASE_PTR,5)

#define	PORTC_PCR6 PORT_PCR_REG(PORTC_BASE_PTR,6)

#define	PORTC_PCR7 PORT_PCR_REG(PORTC_BASE_PTR,7)

#define	PORTC_PCR8 PORT_PCR_REG(PORTC_BASE_PTR,8)

#define	PORTC_PCR9 PORT_PCR_REG(PORTC_BASE_PTR,9)

#define	PORTC_PCR10 PORT_PCR_REG(PORTC_BASE_PTR,10)

#define	PORTC_PCR11 PORT_PCR_REG(PORTC_BASE_PTR,11)

#define	PORTC_PCR12 PORT_PCR_REG(PORTC_BASE_PTR,12)

#define	PORTC_PCR13 PORT_PCR_REG(PORTC_BASE_PTR,13)

#define	PORTC_PCR14 PORT_PCR_REG(PORTC_BASE_PTR,14)

#define	PORTC_PCR15 PORT_PCR_REG(PORTC_BASE_PTR,15)

#define	PORTC_PCR16 PORT_PCR_REG(PORTC_BASE_PTR,16)

#define	PORTC_PCR17 PORT_PCR_REG(PORTC_BASE_PTR,17)

#define	PORTC_PCR18 PORT_PCR_REG(PORTC_BASE_PTR,18)

#define	PORTC_PCR19 PORT_PCR_REG(PORTC_BASE_PTR,19)

#define	PORTC_PCR20 PORT_PCR_REG(PORTC_BASE_PTR,20)

#define	PORTC_PCR21 PORT_PCR_REG(PORTC_BASE_PTR,21)

#define	PORTC_PCR22 PORT_PCR_REG(PORTC_BASE_PTR,22)

#define	PORTC_PCR23 PORT_PCR_REG(PORTC_BASE_PTR,23)

#define	PORTC_PCR24 PORT_PCR_REG(PORTC_BASE_PTR,24)

#define	PORTC_PCR25 PORT_PCR_REG(PORTC_BASE_PTR,25)

#define	PORTC_PCR26 PORT_PCR_REG(PORTC_BASE_PTR,26)

#define	PORTC_PCR27 PORT_PCR_REG(PORTC_BASE_PTR,27)

#define	PORTC_PCR28 PORT_PCR_REG(PORTC_BASE_PTR,28)

#define	PORTC_PCR29 PORT_PCR_REG(PORTC_BASE_PTR,29)

#define	PORTC_PCR30 PORT_PCR_REG(PORTC_BASE_PTR,30)

#define	PORTC_PCR31 PORT_PCR_REG(PORTC_BASE_PTR,31)

#define	PORTC_GPCLR PORT_GPCLR_REG(PORTC_BASE_PTR)

#define	PORTC_GPCHR PORT_GPCHR_REG(PORTC_BASE_PTR)

#define	PORTC_ISFR PORT_ISFR_REG(PORTC_BASE_PTR)

#define	PORTC_DFER PORT_DFER_REG(PORTC_BASE_PTR)

#define	PORTC_DFCR PORT_DFCR_REG(PORTC_BASE_PTR)

#define	PORTC_DFWR PORT_DFWR_REG(PORTC_BASE_PTR)

#define	PORTD_PCR0 PORT_PCR_REG(PORTD_BASE_PTR,0)

#define	PORTD_PCR1 PORT_PCR_REG(PORTD_BASE_PTR,1)

#define	PORTD_PCR2 PORT_PCR_REG(PORTD_BASE_PTR,2)

#define	PORTD_PCR3 PORT_PCR_REG(PORTD_BASE_PTR,3)

#define	PORTD_PCR4 PORT_PCR_REG(PORTD_BASE_PTR,4)

#define	PORTD_PCR5 PORT_PCR_REG(PORTD_BASE_PTR,5)

#define	PORTD_PCR6 PORT_PCR_REG(PORTD_BASE_PTR,6)

#define	PORTD_PCR7 PORT_PCR_REG(PORTD_BASE_PTR,7)

#define	PORTD_PCR8 PORT_PCR_REG(PORTD_BASE_PTR,8)

#define	PORTD_PCR9 PORT_PCR_REG(PORTD_BASE_PTR,9)

#define	PORTD_PCR10 PORT_PCR_REG(PORTD_BASE_PTR,10)

#define	PORTD_PCR11 PORT_PCR_REG(PORTD_BASE_PTR,11)

#define	PORTD_PCR12 PORT_PCR_REG(PORTD_BASE_PTR,12)

#define	PORTD_PCR13 PORT_PCR_REG(PORTD_BASE_PTR,13)

#define	PORTD_PCR14 PORT_PCR_REG(PORTD_BASE_PTR,14)

#define	PORTD_PCR15 PORT_PCR_REG(PORTD_BASE_PTR,15)

#define	PORTD_PCR16 PORT_PCR_REG(PORTD_BASE_PTR,16)

#define	PORTD_PCR17 PORT_PCR_REG(PORTD_BASE_PTR,17)

#define	PORTD_PCR18 PORT_PCR_REG(PORTD_BASE_PTR,18)

#define	PORTD_PCR19 PORT_PCR_REG(PORTD_BASE_PTR,19)

#define	PORTD_PCR20 PORT_PCR_REG(PORTD_BASE_PTR,20)

#define	PORTD_PCR21 PORT_PCR_REG(PORTD_BASE_PTR,21)

#define	PORTD_PCR22 PORT_PCR_REG(PORTD_BASE_PTR,22)

#define	PORTD_PCR23 PORT_PCR_REG(PORTD_BASE_PTR,23)

#define	PORTD_PCR24 PORT_PCR_REG(PORTD_BASE_PTR,24)

#define	PORTD_PCR25 PORT_PCR_REG(PORTD_BASE_PTR,25)

#define	PORTD_PCR26 PORT_PCR_REG(PORTD_BASE_PTR,26)

#define	PORTD_PCR27 PORT_PCR_REG(PORTD_BASE_PTR,27)

#define	PORTD_PCR28 PORT_PCR_REG(PORTD_BASE_PTR,28)

#define	PORTD_PCR29 PORT_PCR_REG(PORTD_BASE_PTR,29)

#define	PORTD_PCR30 PORT_PCR_REG(PORTD_BASE_PTR,30)

#define	PORTD_PCR31 PORT_PCR_REG(PORTD_BASE_PTR,31)

#define	PORTD_GPCLR PORT_GPCLR_REG(PORTD_BASE_PTR)

#define	PORTD_GPCHR PORT_GPCHR_REG(PORTD_BASE_PTR)

#define	PORTD_ISFR PORT_ISFR_REG(PORTD_BASE_PTR)

#define	PORTD_DFER PORT_DFER_REG(PORTD_BASE_PTR)

#define	PORTD_DFCR PORT_DFCR_REG(PORTD_BASE_PTR)

#define	PORTD_DFWR PORT_DFWR_REG(PORTD_BASE_PTR)

#define	PORTE_PCR0 PORT_PCR_REG(PORTE_BASE_PTR,0)

#define	PORTE_PCR1 PORT_PCR_REG(PORTE_BASE_PTR,1)

#define	PORTE_PCR2 PORT_PCR_REG(PORTE_BASE_PTR,2)

#define	PORTE_PCR3 PORT_PCR_REG(PORTE_BASE_PTR,3)

#define	PORTE_PCR4 PORT_PCR_REG(PORTE_BASE_PTR,4)

#define	PORTE_PCR5 PORT_PCR_REG(PORTE_BASE_PTR,5)

#define	PORTE_PCR6 PORT_PCR_REG(PORTE_BASE_PTR,6)

#define	PORTE_PCR7 PORT_PCR_REG(PORTE_BASE_PTR,7)

#define	PORTE_PCR8 PORT_PCR_REG(PORTE_BASE_PTR,8)

#define	PORTE_PCR9 PORT_PCR_REG(PORTE_BASE_PTR,9)

#define	PORTE_PCR10 PORT_PCR_REG(PORTE_BASE_PTR,10)

#define	PORTE_PCR11 PORT_PCR_REG(PORTE_BASE_PTR,11)

#define	PORTE_PCR12 PORT_PCR_REG(PORTE_BASE_PTR,12)

#define	PORTE_PCR13 PORT_PCR_REG(PORTE_BASE_PTR,13)

#define	PORTE_PCR14 PORT_PCR_REG(PORTE_BASE_PTR,14)

#define	PORTE_PCR15 PORT_PCR_REG(PORTE_BASE_PTR,15)

#define	PORTE_PCR16 PORT_PCR_REG(PORTE_BASE_PTR,16)

#define	PORTE_PCR17 PORT_PCR_REG(PORTE_BASE_PTR,17)

#define	PORTE_PCR18 PORT_PCR_REG(PORTE_BASE_PTR,18)

#define	PORTE_PCR19 PORT_PCR_REG(PORTE_BASE_PTR,19)

#define	PORTE_PCR20 PORT_PCR_REG(PORTE_BASE_PTR,20)

#define	PORTE_PCR21 PORT_PCR_REG(PORTE_BASE_PTR,21)

#define	PORTE_PCR22 PORT_PCR_REG(PORTE_BASE_PTR,22)

#define	PORTE_PCR23 PORT_PCR_REG(PORTE_BASE_PTR,23)

#define	PORTE_PCR24 PORT_PCR_REG(PORTE_BASE_PTR,24)

#define	PORTE_PCR25 PORT_PCR_REG(PORTE_BASE_PTR,25)

#define	PORTE_PCR26 PORT_PCR_REG(PORTE_BASE_PTR,26)

#define	PORTE_PCR27 PORT_PCR_REG(PORTE_BASE_PTR,27)

#define	PORTE_PCR28 PORT_PCR_REG(PORTE_BASE_PTR,28)

#define	PORTE_PCR29 PORT_PCR_REG(PORTE_BASE_PTR,29)

#define	PORTE_PCR30 PORT_PCR_REG(PORTE_BASE_PTR,30)

#define	PORTE_PCR31 PORT_PCR_REG(PORTE_BASE_PTR,31)

#define	PORTE_GPCLR PORT_GPCLR_REG(PORTE_BASE_PTR)

#define	PORTE_GPCHR PORT_GPCHR_REG(PORTE_BASE_PTR)

#define	PORTE_ISFR PORT_ISFR_REG(PORTE_BASE_PTR)

#define	PORTE_DFER PORT_DFER_REG(PORTE_BASE_PTR)

#define	PORTE_DFCR PORT_DFCR_REG(PORTE_BASE_PTR)

#define	PORTE_DFWR PORT_DFWR_REG(PORTE_BASE_PTR)

#define	PORTF_PCR0 PORT_PCR_REG(PORTF_BASE_PTR,0)

#define	PORTF_PCR1 PORT_PCR_REG(PORTF_BASE_PTR,1)

#define	PORTF_PCR2 PORT_PCR_REG(PORTF_BASE_PTR,2)

#define	PORTF_PCR3 PORT_PCR_REG(PORTF_BASE_PTR,3)

#define	PORTF_PCR4 PORT_PCR_REG(PORTF_BASE_PTR,4)

#define	PORTF_PCR5 PORT_PCR_REG(PORTF_BASE_PTR,5)

#define	PORTF_PCR6 PORT_PCR_REG(PORTF_BASE_PTR,6)

#define	PORTF_PCR7 PORT_PCR_REG(PORTF_BASE_PTR,7)

#define	PORTF_PCR8 PORT_PCR_REG(PORTF_BASE_PTR,8)

#define	PORTF_PCR9 PORT_PCR_REG(PORTF_BASE_PTR,9)

#define	PORTF_PCR10 PORT_PCR_REG(PORTF_BASE_PTR,10)

#define	PORTF_PCR11 PORT_PCR_REG(PORTF_BASE_PTR,11)

#define	PORTF_PCR12 PORT_PCR_REG(PORTF_BASE_PTR,12)

#define	PORTF_PCR13 PORT_PCR_REG(PORTF_BASE_PTR,13)

#define	PORTF_PCR14 PORT_PCR_REG(PORTF_BASE_PTR,14)

#define	PORTF_PCR15 PORT_PCR_REG(PORTF_BASE_PTR,15)

#define	PORTF_PCR16 PORT_PCR_REG(PORTF_BASE_PTR,16)

#define	PORTF_PCR17 PORT_PCR_REG(PORTF_BASE_PTR,17)

#define	PORTF_PCR18 PORT_PCR_REG(PORTF_BASE_PTR,18)

#define	PORTF_PCR19 PORT_PCR_REG(PORTF_BASE_PTR,19)

#define	PORTF_PCR20 PORT_PCR_REG(PORTF_BASE_PTR,20)

#define	PORTF_PCR21 PORT_PCR_REG(PORTF_BASE_PTR,21)

#define	PORTF_PCR22 PORT_PCR_REG(PORTF_BASE_PTR,22)

#define	PORTF_PCR23 PORT_PCR_REG(PORTF_BASE_PTR,23)

#define	PORTF_PCR24 PORT_PCR_REG(PORTF_BASE_PTR,24)

#define	PORTF_PCR25 PORT_PCR_REG(PORTF_BASE_PTR,25)

#define	PORTF_PCR26 PORT_PCR_REG(PORTF_BASE_PTR,26)

#define	PORTF_PCR27 PORT_PCR_REG(PORTF_BASE_PTR,27)

#define	PORTF_PCR28 PORT_PCR_REG(PORTF_BASE_PTR,28)

#define	PORTF_PCR29 PORT_PCR_REG(PORTF_BASE_PTR,29)

#define	PORTF_PCR30 PORT_PCR_REG(PORTF_BASE_PTR,30)

#define	PORTF_PCR31 PORT_PCR_REG(PORTF_BASE_PTR,31)

#define	PORTF_GPCLR PORT_GPCLR_REG(PORTF_BASE_PTR)

#define	PORTF_GPCHR PORT_GPCHR_REG(PORTF_BASE_PTR)

#define	PORTF_ISFR PORT_ISFR_REG(PORTF_BASE_PTR)

#define	PORTF_DFER PORT_DFER_REG(PORTF_BASE_PTR)

#define	PORTF_DFCR PORT_DFCR_REG(PORTF_BASE_PTR)

#define	PORTF_DFWR PORT_DFWR_REG(PORTF_BASE_PTR)

#define	PORTA_PCR(index) PORT_PCR_REG(PORTA_BASE_PTR,index)

#define	PORTB_PCR(index) PORT_PCR_REG(PORTB_BASE_PTR,index)

#define	PORTC_PCR(index) PORT_PCR_REG(PORTC_BASE_PTR,index)

#define	PORTD_PCR(index) PORT_PCR_REG(PORTD_BASE_PTR,index)

#define	PORTE_PCR(index) PORT_PCR_REG(PORTE_BASE_PTR,index)

#define	PORTF_PCR(index) PORT_PCR_REG(PORTF_BASE_PTR,index)

#define	RCM_SRS0_REG(base) ((base)->SRS0)

#define	RCM_SRS1_REG(base) ((base)->SRS1)

#define	RCM_RPFC_REG(base) ((base)->RPFC)

#define	RCM_RPFW_REG(base) ((base)->RPFW)

#define	RCM_MR_REG(base) ((base)->MR)

#define	RCM_SRS0_WAKEUP_MASK 0x1u

#define	RCM_SRS0_WAKEUP_SHIFT 0

#define	RCM_SRS0_LVD_MASK 0x2u

#define	RCM_SRS0_LVD_SHIFT 1

#define	RCM_SRS0_LOC_MASK 0x4u

#define	RCM_SRS0_LOC_SHIFT 2

#define	RCM_SRS0_WDOG_MASK 0x20u

#define	RCM_SRS0_WDOG_SHIFT 5

#define	RCM_SRS0_PIN_MASK 0x40u

#define	RCM_SRS0_PIN_SHIFT 6

#define	RCM_SRS0_POR_MASK 0x80u

#define	RCM_SRS0_POR_SHIFT 7

#define	RCM_SRS1_JTAG_MASK 0x1u

#define	RCM_SRS1_JTAG_SHIFT 0

#define	RCM_SRS1_LOCKUP_MASK 0x2u

#define	RCM_SRS1_LOCKUP_SHIFT 1

#define	RCM_SRS1_SW_MASK 0x4u

#define	RCM_SRS1_SW_SHIFT 2

#define	RCM_SRS1_MDM_AP_MASK 0x8u

#define	RCM_SRS1_MDM_AP_SHIFT 3

#define	RCM_SRS1_EZPT_MASK 0x10u

#define	RCM_SRS1_EZPT_SHIFT 4

#define	RCM_SRS1_SACKERR_MASK 0x20u

#define	RCM_SRS1_SACKERR_SHIFT 5

#define	RCM_RPFC_RSTFLTSRW_MASK 0x3u

#define	RCM_RPFC_RSTFLTSRW_SHIFT 0

#define	RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)

#define	RCM_RPFC_RSTFLTSS_MASK 0x4u

#define	RCM_RPFC_RSTFLTSS_SHIFT 2

#define	RCM_RPFW_RSTFLTSEL_MASK 0x1Fu

#define	RCM_RPFW_RSTFLTSEL_SHIFT 0

#define	RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)

#define	RCM_MR_EZP_MS_MASK 0x2u

#define	RCM_MR_EZP_MS_SHIFT 1

#define	RCM_BASE_PTR ((RCM_MemMapPtr)0x4007F000u)

#define	RCM_BASE_PTRS { RCM_BASE_PTR }

#define	RCM_SRS0 RCM_SRS0_REG(RCM_BASE_PTR)

#define	RCM_SRS1 RCM_SRS1_REG(RCM_BASE_PTR)

#define	RCM_RPFC RCM_RPFC_REG(RCM_BASE_PTR)

#define	RCM_RPFW RCM_RPFW_REG(RCM_BASE_PTR)

#define	RCM_MR RCM_MR_REG(RCM_BASE_PTR)

#define	RFSYS_REG_REG(base, index) ((base)->REG[index])

#define	RFSYS_REG_LL_MASK 0xFFu

#define	RFSYS_REG_LL_SHIFT 0

#define	RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)

#define	RFSYS_REG_LH_MASK 0xFF00u

#define	RFSYS_REG_LH_SHIFT 8

#define	RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)

#define	RFSYS_REG_HL_MASK 0xFF0000u

#define	RFSYS_REG_HL_SHIFT 16

#define	RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)

#define	RFSYS_REG_HH_MASK 0xFF000000u

#define	RFSYS_REG_HH_SHIFT 24

#define	RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)

#define	RFSYS_BASE_PTR ((RFSYS_MemMapPtr)0x40041000u)

#define	RFSYS_BASE_PTRS { RFSYS_BASE_PTR }

#define	RFSYS_REG0 RFSYS_REG_REG(RFSYS_BASE_PTR,0)

#define	RFSYS_REG1 RFSYS_REG_REG(RFSYS_BASE_PTR,1)

#define	RFSYS_REG2 RFSYS_REG_REG(RFSYS_BASE_PTR,2)

#define	RFSYS_REG3 RFSYS_REG_REG(RFSYS_BASE_PTR,3)

#define	RFSYS_REG4 RFSYS_REG_REG(RFSYS_BASE_PTR,4)

#define	RFSYS_REG5 RFSYS_REG_REG(RFSYS_BASE_PTR,5)

#define	RFSYS_REG6 RFSYS_REG_REG(RFSYS_BASE_PTR,6)

#define	RFSYS_REG7 RFSYS_REG_REG(RFSYS_BASE_PTR,7)

#define	RFSYS_REG(index) RFSYS_REG_REG(RFSYS_BASE_PTR,index)

#define	RFVBAT_REG_REG(base, index) ((base)->REG[index])

#define	RFVBAT_REG_LL_MASK 0xFFu

#define	RFVBAT_REG_LL_SHIFT 0

#define	RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)

#define	RFVBAT_REG_LH_MASK 0xFF00u

#define	RFVBAT_REG_LH_SHIFT 8

#define	RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)

#define	RFVBAT_REG_HL_MASK 0xFF0000u

#define	RFVBAT_REG_HL_SHIFT 16

#define	RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)

#define	RFVBAT_REG_HH_MASK 0xFF000000u

#define	RFVBAT_REG_HH_SHIFT 24

#define	RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)

#define	RFVBAT_BASE_PTR ((RFVBAT_MemMapPtr)0x4003E000u)

#define	RFVBAT_BASE_PTRS { RFVBAT_BASE_PTR }

#define	RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT_BASE_PTR,0)

#define	RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT_BASE_PTR,1)

#define	RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT_BASE_PTR,2)

#define	RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT_BASE_PTR,3)

#define	RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT_BASE_PTR,4)

#define	RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT_BASE_PTR,5)

#define	RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT_BASE_PTR,6)

#define	RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT_BASE_PTR,7)

#define	RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT_BASE_PTR,index)

#define	RNG_CR_REG(base) ((base)->CR)

#define	RNG_SR_REG(base) ((base)->SR)

#define	RNG_ER_REG(base) ((base)->ER)

#define	RNG_OR_REG(base) ((base)->OR)

#define	RNG_CR_GO_MASK 0x1u

#define	RNG_CR_GO_SHIFT 0

#define	RNG_CR_HA_MASK 0x2u

#define	RNG_CR_HA_SHIFT 1

#define	RNG_CR_INTM_MASK 0x4u

#define	RNG_CR_INTM_SHIFT 2

#define	RNG_CR_CLRI_MASK 0x8u

#define	RNG_CR_CLRI_SHIFT 3

#define	RNG_CR_SLP_MASK 0x10u

#define	RNG_CR_SLP_SHIFT 4

#define	RNG_SR_SECV_MASK 0x1u

#define	RNG_SR_SECV_SHIFT 0

#define	RNG_SR_LRS_MASK 0x2u

#define	RNG_SR_LRS_SHIFT 1

#define	RNG_SR_ORU_MASK 0x4u

#define	RNG_SR_ORU_SHIFT 2

#define	RNG_SR_ERRI_MASK 0x8u

#define	RNG_SR_ERRI_SHIFT 3

#define	RNG_SR_SLP_MASK 0x10u

#define	RNG_SR_SLP_SHIFT 4

#define	RNG_SR_OREG_LVL_MASK 0xFF00u

#define	RNG_SR_OREG_LVL_SHIFT 8

#define	RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)

#define	RNG_SR_OREG_SIZE_MASK 0xFF0000u

#define	RNG_SR_OREG_SIZE_SHIFT 16

#define	RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)

#define	RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu

#define	RNG_ER_EXT_ENT_SHIFT 0

#define	RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)

#define	RNG_OR_RANDOUT_MASK 0xFFFFFFFFu

#define	RNG_OR_RANDOUT_SHIFT 0

#define	RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)

#define	RNG_BASE_PTR ((RNG_MemMapPtr)0x400A0000u)

#define	RNG_BASE_PTRS { RNG_BASE_PTR }

#define	RNG_CR RNG_CR_REG(RNG_BASE_PTR)

#define	RNG_SR RNG_SR_REG(RNG_BASE_PTR)

#define	RNG_ER RNG_ER_REG(RNG_BASE_PTR)

#define	RNG_OR RNG_OR_REG(RNG_BASE_PTR)

#define	RTC_TSR_REG(base) ((base)->TSR)

#define	RTC_TPR_REG(base) ((base)->TPR)

#define	RTC_TAR_REG(base) ((base)->TAR)

#define	RTC_TCR_REG(base) ((base)->TCR)

#define	RTC_CR_REG(base) ((base)->CR)

#define	RTC_SR_REG(base) ((base)->SR)

#define	RTC_LR_REG(base) ((base)->LR)

#define	RTC_IER_REG(base) ((base)->IER)

#define	RTC_TTSR_REG(base) ((base)->TTSR)

#define	RTC_MER_REG(base) ((base)->MER)

#define	RTC_MCLR_REG(base) ((base)->MCLR)

#define	RTC_MCHR_REG(base) ((base)->MCHR)

#define	RTC_WAR_REG(base) ((base)->WAR)

#define	RTC_RAR_REG(base) ((base)->RAR)

#define	RTC_TSR_TSR_MASK 0xFFFFFFFFu

#define	RTC_TSR_TSR_SHIFT 0

#define	RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)

#define	RTC_TPR_TPR_MASK 0xFFFFu

#define	RTC_TPR_TPR_SHIFT 0

#define	RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)

#define	RTC_TAR_TAR_MASK 0xFFFFFFFFu

#define	RTC_TAR_TAR_SHIFT 0

#define	RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)

#define	RTC_TCR_TCR_MASK 0xFFu

#define	RTC_TCR_TCR_SHIFT 0

#define	RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)

#define	RTC_TCR_CIR_MASK 0xFF00u

#define	RTC_TCR_CIR_SHIFT 8

#define	RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)

#define	RTC_TCR_TCV_MASK 0xFF0000u

#define	RTC_TCR_TCV_SHIFT 16

#define	RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)

#define	RTC_TCR_CIC_MASK 0xFF000000u

#define	RTC_TCR_CIC_SHIFT 24

#define	RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)

#define	RTC_CR_SWR_MASK 0x1u

#define	RTC_CR_SWR_SHIFT 0

#define	RTC_CR_WPE_MASK 0x2u

#define	RTC_CR_WPE_SHIFT 1

#define	RTC_CR_SUP_MASK 0x4u

#define	RTC_CR_SUP_SHIFT 2

#define	RTC_CR_UM_MASK 0x8u

#define	RTC_CR_UM_SHIFT 3

#define	RTC_CR_OSCE_MASK 0x100u

#define	RTC_CR_OSCE_SHIFT 8

#define	RTC_CR_CLKO_MASK 0x200u

#define	RTC_CR_CLKO_SHIFT 9

#define	RTC_CR_SC16P_MASK 0x400u

#define	RTC_CR_SC16P_SHIFT 10

#define	RTC_CR_SC8P_MASK 0x800u

#define	RTC_CR_SC8P_SHIFT 11

#define	RTC_CR_SC4P_MASK 0x1000u

#define	RTC_CR_SC4P_SHIFT 12

#define	RTC_CR_SC2P_MASK 0x2000u

#define	RTC_CR_SC2P_SHIFT 13

#define	RTC_SR_TIF_MASK 0x1u

#define	RTC_SR_TIF_SHIFT 0

#define	RTC_SR_TOF_MASK 0x2u

#define	RTC_SR_TOF_SHIFT 1

#define	RTC_SR_TAF_MASK 0x4u

#define	RTC_SR_TAF_SHIFT 2

#define	RTC_SR_MOF_MASK 0x8u

#define	RTC_SR_MOF_SHIFT 3

#define	RTC_SR_TCE_MASK 0x10u

#define	RTC_SR_TCE_SHIFT 4

#define	RTC_LR_TCL_MASK 0x8u

#define	RTC_LR_TCL_SHIFT 3

#define	RTC_LR_CRL_MASK 0x10u

#define	RTC_LR_CRL_SHIFT 4

#define	RTC_LR_SRL_MASK 0x20u

#define	RTC_LR_SRL_SHIFT 5

#define	RTC_LR_LRL_MASK 0x40u

#define	RTC_LR_LRL_SHIFT 6

#define	RTC_LR_TTSL_MASK 0x100u

#define	RTC_LR_TTSL_SHIFT 8

#define	RTC_LR_MEL_MASK 0x200u

#define	RTC_LR_MEL_SHIFT 9

#define	RTC_LR_MCLL_MASK 0x400u

#define	RTC_LR_MCLL_SHIFT 10

#define	RTC_LR_MCHL_MASK 0x800u

#define	RTC_LR_MCHL_SHIFT 11

#define	RTC_IER_TIIE_MASK 0x1u

#define	RTC_IER_TIIE_SHIFT 0

#define	RTC_IER_TOIE_MASK 0x2u

#define	RTC_IER_TOIE_SHIFT 1

#define	RTC_IER_TAIE_MASK 0x4u

#define	RTC_IER_TAIE_SHIFT 2

#define	RTC_IER_MOIE_MASK 0x8u

#define	RTC_IER_MOIE_SHIFT 3

#define	RTC_IER_TSIE_MASK 0x10u

#define	RTC_IER_TSIE_SHIFT 4

#define	RTC_TTSR_TTS_MASK 0xFFFFFFFFu

#define	RTC_TTSR_TTS_SHIFT 0

#define	RTC_TTSR_TTS(x) (((uint32_t)(((uint32_t)(x))<<RTC_TTSR_TTS_SHIFT))&RTC_TTSR_TTS_MASK)

#define	RTC_MER_MCE_MASK 0x10u

#define	RTC_MER_MCE_SHIFT 4

#define	RTC_MCLR_MCL_MASK 0xFFFFFFFFu

#define	RTC_MCLR_MCL_SHIFT 0

#define	RTC_MCLR_MCL(x) (((uint32_t)(((uint32_t)(x))<<RTC_MCLR_MCL_SHIFT))&RTC_MCLR_MCL_MASK)

#define	RTC_MCHR_MCH_MASK 0xFFFFFFFFu

#define	RTC_MCHR_MCH_SHIFT 0

#define	RTC_MCHR_MCH(x) (((uint32_t)(((uint32_t)(x))<<RTC_MCHR_MCH_SHIFT))&RTC_MCHR_MCH_MASK)

#define	RTC_WAR_TSRW_MASK 0x1u

#define	RTC_WAR_TSRW_SHIFT 0

#define	RTC_WAR_TPRW_MASK 0x2u

#define	RTC_WAR_TPRW_SHIFT 1

#define	RTC_WAR_TARW_MASK 0x4u

#define	RTC_WAR_TARW_SHIFT 2

#define	RTC_WAR_TCRW_MASK 0x8u

#define	RTC_WAR_TCRW_SHIFT 3

#define	RTC_WAR_CRW_MASK 0x10u

#define	RTC_WAR_CRW_SHIFT 4

#define	RTC_WAR_SRW_MASK 0x20u

#define	RTC_WAR_SRW_SHIFT 5

#define	RTC_WAR_LRW_MASK 0x40u

#define	RTC_WAR_LRW_SHIFT 6

#define	RTC_WAR_IERW_MASK 0x80u

#define	RTC_WAR_IERW_SHIFT 7

#define	RTC_WAR_TTSW_MASK 0x100u

#define	RTC_WAR_TTSW_SHIFT 8

#define	RTC_WAR_MERW_MASK 0x200u

#define	RTC_WAR_MERW_SHIFT 9

#define	RTC_WAR_MCLW_MASK 0x400u

#define	RTC_WAR_MCLW_SHIFT 10

#define	RTC_WAR_MCHW_MASK 0x800u

#define	RTC_WAR_MCHW_SHIFT 11

#define	RTC_RAR_TSRR_MASK 0x1u

#define	RTC_RAR_TSRR_SHIFT 0

#define	RTC_RAR_TPRR_MASK 0x2u

#define	RTC_RAR_TPRR_SHIFT 1

#define	RTC_RAR_TARR_MASK 0x4u

#define	RTC_RAR_TARR_SHIFT 2

#define	RTC_RAR_TCRR_MASK 0x8u

#define	RTC_RAR_TCRR_SHIFT 3

#define	RTC_RAR_CRR_MASK 0x10u

#define	RTC_RAR_CRR_SHIFT 4

#define	RTC_RAR_SRR_MASK 0x20u

#define	RTC_RAR_SRR_SHIFT 5

#define	RTC_RAR_LRR_MASK 0x40u

#define	RTC_RAR_LRR_SHIFT 6

#define	RTC_RAR_IERR_MASK 0x80u

#define	RTC_RAR_IERR_SHIFT 7

#define	RTC_RAR_TTSR_MASK 0x100u

#define	RTC_RAR_TTSR_SHIFT 8

#define	RTC_RAR_MERR_MASK 0x200u

#define	RTC_RAR_MERR_SHIFT 9

#define	RTC_RAR_MCLR_MASK 0x400u

#define	RTC_RAR_MCLR_SHIFT 10

#define	RTC_RAR_MCHR_MASK 0x800u

#define	RTC_RAR_MCHR_SHIFT 11

#define	RTC_BASE_PTR ((RTC_MemMapPtr)0x4003D000u)

#define	RTC_BASE_PTRS { RTC_BASE_PTR }

#define	RTC_TSR RTC_TSR_REG(RTC_BASE_PTR)

#define	RTC_TPR RTC_TPR_REG(RTC_BASE_PTR)

#define	RTC_TAR RTC_TAR_REG(RTC_BASE_PTR)

#define	RTC_TCR RTC_TCR_REG(RTC_BASE_PTR)

#define	RTC_CR RTC_CR_REG(RTC_BASE_PTR)

#define	RTC_SR RTC_SR_REG(RTC_BASE_PTR)

#define	RTC_LR RTC_LR_REG(RTC_BASE_PTR)

#define	RTC_IER RTC_IER_REG(RTC_BASE_PTR)

#define	RTC_TTSR RTC_TTSR_REG(RTC_BASE_PTR)

#define	RTC_MER RTC_MER_REG(RTC_BASE_PTR)

#define	RTC_MCLR RTC_MCLR_REG(RTC_BASE_PTR)

#define	RTC_MCHR RTC_MCHR_REG(RTC_BASE_PTR)

#define	RTC_WAR RTC_WAR_REG(RTC_BASE_PTR)

#define	RTC_RAR RTC_RAR_REG(RTC_BASE_PTR)

#define	SCB_ACTLR_REG(base) ((base)->ACTLR)

#define	SCB_CPUID_REG(base) ((base)->CPUID)

#define	SCB_ICSR_REG(base) ((base)->ICSR)

#define	SCB_VTOR_REG(base) ((base)->VTOR)

#define	SCB_AIRCR_REG(base) ((base)->AIRCR)

#define	SCB_SCR_REG(base) ((base)->SCR)

#define	SCB_CCR_REG(base) ((base)->CCR)

#define	SCB_SHPR1_REG(base) ((base)->SHPR1)

#define	SCB_SHPR2_REG(base) ((base)->SHPR2)

#define	SCB_SHPR3_REG(base) ((base)->SHPR3)

#define	SCB_SHCSR_REG(base) ((base)->SHCSR)

#define	SCB_CFSR_REG(base) ((base)->CFSR)

#define	SCB_HFSR_REG(base) ((base)->HFSR)

#define	SCB_DFSR_REG(base) ((base)->DFSR)

#define	SCB_MMFAR_REG(base) ((base)->MMFAR)

#define	SCB_BFAR_REG(base) ((base)->BFAR)

#define	SCB_AFSR_REG(base) ((base)->AFSR)

#define	SCB_CPACR_REG(base) ((base)->CPACR)

#define	SCB_ACTLR_DISMCYCINT_MASK 0x1u

#define	SCB_ACTLR_DISMCYCINT_SHIFT 0

#define	SCB_ACTLR_DISDEFWBUF_MASK 0x2u

#define	SCB_ACTLR_DISDEFWBUF_SHIFT 1

#define	SCB_ACTLR_DISFOLD_MASK 0x4u

#define	SCB_ACTLR_DISFOLD_SHIFT 2

#define	SCB_CPUID_REVISION_MASK 0xFu

#define	SCB_CPUID_REVISION_SHIFT 0

#define	SCB_CPUID_REVISION(x) (((uint32_t)(((uint32_t)(x))<<SCB_CPUID_REVISION_SHIFT))&SCB_CPUID_REVISION_MASK)

#define	SCB_CPUID_PARTNO_MASK 0xFFF0u

#define	SCB_CPUID_PARTNO_SHIFT 4

#define	SCB_CPUID_PARTNO(x) (((uint32_t)(((uint32_t)(x))<<SCB_CPUID_PARTNO_SHIFT))&SCB_CPUID_PARTNO_MASK)

#define	SCB_CPUID_VARIANT_MASK 0xF00000u

#define	SCB_CPUID_VARIANT_SHIFT 20

#define	SCB_CPUID_VARIANT(x) (((uint32_t)(((uint32_t)(x))<<SCB_CPUID_VARIANT_SHIFT))&SCB_CPUID_VARIANT_MASK)

#define	SCB_CPUID_IMPLEMENTER_MASK 0xFF000000u

#define	SCB_CPUID_IMPLEMENTER_SHIFT 24

#define	SCB_CPUID_IMPLEMENTER(x) (((uint32_t)(((uint32_t)(x))<<SCB_CPUID_IMPLEMENTER_SHIFT))&SCB_CPUID_IMPLEMENTER_MASK)

#define	SCB_ICSR_VECTACTIVE_MASK 0x1FFu

#define	SCB_ICSR_VECTACTIVE_SHIFT 0

#define	SCB_ICSR_VECTACTIVE(x) (((uint32_t)(((uint32_t)(x))<<SCB_ICSR_VECTACTIVE_SHIFT))&SCB_ICSR_VECTACTIVE_MASK)

#define	SCB_ICSR_RETTOBASE_MASK 0x800u

#define	SCB_ICSR_RETTOBASE_SHIFT 11

#define	SCB_ICSR_VECTPENDING_MASK 0x3F000u

#define	SCB_ICSR_VECTPENDING_SHIFT 12

#define	SCB_ICSR_VECTPENDING(x) (((uint32_t)(((uint32_t)(x))<<SCB_ICSR_VECTPENDING_SHIFT))&SCB_ICSR_VECTPENDING_MASK)

#define	SCB_ICSR_ISRPENDING_MASK 0x400000u

#define	SCB_ICSR_ISRPENDING_SHIFT 22

#define	SCB_ICSR_ISRPREEMPT_MASK 0x800000u

#define	SCB_ICSR_ISRPREEMPT_SHIFT 23

#define	SCB_ICSR_PENDSTCLR_MASK 0x2000000u

#define	SCB_ICSR_PENDSTCLR_SHIFT 25

#define	SCB_ICSR_PENDSTSET_MASK 0x4000000u

#define	SCB_ICSR_PENDSTSET_SHIFT 26

#define	SCB_ICSR_PENDSVCLR_MASK 0x8000000u

#define	SCB_ICSR_PENDSVCLR_SHIFT 27

#define	SCB_ICSR_PENDSVSET_MASK 0x10000000u

#define	SCB_ICSR_PENDSVSET_SHIFT 28

#define	SCB_ICSR_NMIPENDSET_MASK 0x80000000u

#define	SCB_ICSR_NMIPENDSET_SHIFT 31

#define	SCB_VTOR_TBLOFF_MASK 0xFFFFFF80u

#define	SCB_VTOR_TBLOFF_SHIFT 7

#define	SCB_VTOR_TBLOFF(x) (((uint32_t)(((uint32_t)(x))<<SCB_VTOR_TBLOFF_SHIFT))&SCB_VTOR_TBLOFF_MASK)

#define	SCB_AIRCR_VECTRESET_MASK 0x1u

#define	SCB_AIRCR_VECTRESET_SHIFT 0

#define	SCB_AIRCR_VECTCLRACTIVE_MASK 0x2u

#define	SCB_AIRCR_VECTCLRACTIVE_SHIFT 1

#define	SCB_AIRCR_SYSRESETREQ_MASK 0x4u

#define	SCB_AIRCR_SYSRESETREQ_SHIFT 2

#define	SCB_AIRCR_PRIGROUP_MASK 0x700u

#define	SCB_AIRCR_PRIGROUP_SHIFT 8

#define	SCB_AIRCR_PRIGROUP(x) (((uint32_t)(((uint32_t)(x))<<SCB_AIRCR_PRIGROUP_SHIFT))&SCB_AIRCR_PRIGROUP_MASK)

#define	SCB_AIRCR_ENDIANNESS_MASK 0x8000u

#define	SCB_AIRCR_ENDIANNESS_SHIFT 15

#define	SCB_AIRCR_VECTKEY_MASK 0xFFFF0000u

#define	SCB_AIRCR_VECTKEY_SHIFT 16

#define	SCB_AIRCR_VECTKEY(x) (((uint32_t)(((uint32_t)(x))<<SCB_AIRCR_VECTKEY_SHIFT))&SCB_AIRCR_VECTKEY_MASK)

#define	SCB_SCR_SLEEPONEXIT_MASK 0x2u

#define	SCB_SCR_SLEEPONEXIT_SHIFT 1

#define	SCB_SCR_SLEEPDEEP_MASK 0x4u

#define	SCB_SCR_SLEEPDEEP_SHIFT 2

#define	SCB_SCR_SEVONPEND_MASK 0x10u

#define	SCB_SCR_SEVONPEND_SHIFT 4

#define	SCB_CCR_NONBASETHRDENA_MASK 0x1u

#define	SCB_CCR_NONBASETHRDENA_SHIFT 0

#define	SCB_CCR_USERSETMPEND_MASK 0x2u

#define	SCB_CCR_USERSETMPEND_SHIFT 1

#define	SCB_CCR_UNALIGN_TRP_MASK 0x8u

#define	SCB_CCR_UNALIGN_TRP_SHIFT 3

#define	SCB_CCR_DIV_0_TRP_MASK 0x10u

#define	SCB_CCR_DIV_0_TRP_SHIFT 4

#define	SCB_CCR_BFHFNMIGN_MASK 0x100u

#define	SCB_CCR_BFHFNMIGN_SHIFT 8

#define	SCB_CCR_STKALIGN_MASK 0x200u

#define	SCB_CCR_STKALIGN_SHIFT 9

#define	SCB_SHPR1_PRI_4_MASK 0xFFu

#define	SCB_SHPR1_PRI_4_SHIFT 0

#define	SCB_SHPR1_PRI_4(x) (((uint32_t)(((uint32_t)(x))<<SCB_SHPR1_PRI_4_SHIFT))&SCB_SHPR1_PRI_4_MASK)

#define	SCB_SHPR1_PRI_5_MASK 0xFF00u

#define	SCB_SHPR1_PRI_5_SHIFT 8

#define	SCB_SHPR1_PRI_5(x) (((uint32_t)(((uint32_t)(x))<<SCB_SHPR1_PRI_5_SHIFT))&SCB_SHPR1_PRI_5_MASK)

#define	SCB_SHPR1_PRI_6_MASK 0xFF0000u

#define	SCB_SHPR1_PRI_6_SHIFT 16

#define	SCB_SHPR1_PRI_6(x) (((uint32_t)(((uint32_t)(x))<<SCB_SHPR1_PRI_6_SHIFT))&SCB_SHPR1_PRI_6_MASK)

#define	SCB_SHPR2_PRI_11_MASK 0xFF000000u

#define	SCB_SHPR2_PRI_11_SHIFT 24

#define	SCB_SHPR2_PRI_11(x) (((uint32_t)(((uint32_t)(x))<<SCB_SHPR2_PRI_11_SHIFT))&SCB_SHPR2_PRI_11_MASK)

#define	SCB_SHPR3_PRI_14_MASK 0xFF0000u

#define	SCB_SHPR3_PRI_14_SHIFT 16

#define	SCB_SHPR3_PRI_14(x) (((uint32_t)(((uint32_t)(x))<<SCB_SHPR3_PRI_14_SHIFT))&SCB_SHPR3_PRI_14_MASK)

#define	SCB_SHPR3_PRI_15_MASK 0xFF000000u

#define	SCB_SHPR3_PRI_15_SHIFT 24

#define	SCB_SHPR3_PRI_15(x) (((uint32_t)(((uint32_t)(x))<<SCB_SHPR3_PRI_15_SHIFT))&SCB_SHPR3_PRI_15_MASK)

#define	SCB_SHCSR_MEMFAULTACT_MASK 0x1u

#define	SCB_SHCSR_MEMFAULTACT_SHIFT 0

#define	SCB_SHCSR_BUSFAULTACT_MASK 0x2u

#define	SCB_SHCSR_BUSFAULTACT_SHIFT 1

#define	SCB_SHCSR_USGFAULTACT_MASK 0x8u

#define	SCB_SHCSR_USGFAULTACT_SHIFT 3

#define	SCB_SHCSR_SVCALLACT_MASK 0x80u

#define	SCB_SHCSR_SVCALLACT_SHIFT 7

#define	SCB_SHCSR_MONITORACT_MASK 0x100u

#define	SCB_SHCSR_MONITORACT_SHIFT 8

#define	SCB_SHCSR_PENDSVACT_MASK 0x400u

#define	SCB_SHCSR_PENDSVACT_SHIFT 10

#define	SCB_SHCSR_SYSTICKACT_MASK 0x800u

#define	SCB_SHCSR_SYSTICKACT_SHIFT 11

#define	SCB_SHCSR_USGFAULTPENDED_MASK 0x1000u

#define	SCB_SHCSR_USGFAULTPENDED_SHIFT 12

#define	SCB_SHCSR_MEMFAULTPENDED_MASK 0x2000u

#define	SCB_SHCSR_MEMFAULTPENDED_SHIFT 13

#define	SCB_SHCSR_BUSFAULTPENDED_MASK 0x4000u

#define	SCB_SHCSR_BUSFAULTPENDED_SHIFT 14

#define	SCB_SHCSR_SVCALLPENDED_MASK 0x8000u

#define	SCB_SHCSR_SVCALLPENDED_SHIFT 15

#define	SCB_SHCSR_MEMFAULTENA_MASK 0x10000u

#define	SCB_SHCSR_MEMFAULTENA_SHIFT 16

#define	SCB_SHCSR_BUSFAULTENA_MASK 0x20000u

#define	SCB_SHCSR_BUSFAULTENA_SHIFT 17

#define	SCB_SHCSR_USGFAULTENA_MASK 0x40000u

#define	SCB_SHCSR_USGFAULTENA_SHIFT 18

#define	SCB_CFSR_IACCVIOL_MASK 0x1u

#define	SCB_CFSR_IACCVIOL_SHIFT 0

#define	SCB_CFSR_DACCVIOL_MASK 0x2u

#define	SCB_CFSR_DACCVIOL_SHIFT 1

#define	SCB_CFSR_MUNSTKERR_MASK 0x8u

#define	SCB_CFSR_MUNSTKERR_SHIFT 3

#define	SCB_CFSR_MSTKERR_MASK 0x10u

#define	SCB_CFSR_MSTKERR_SHIFT 4

#define	SCB_CFSR_MLSPERR_MASK 0x20u

#define	SCB_CFSR_MLSPERR_SHIFT 5

#define	SCB_CFSR_MMARVALID_MASK 0x80u

#define	SCB_CFSR_MMARVALID_SHIFT 7

#define	SCB_CFSR_IBUSERR_MASK 0x100u

#define	SCB_CFSR_IBUSERR_SHIFT 8

#define	SCB_CFSR_PRECISERR_MASK 0x200u

#define	SCB_CFSR_PRECISERR_SHIFT 9

#define	SCB_CFSR_IMPRECISERR_MASK 0x400u

#define	SCB_CFSR_IMPRECISERR_SHIFT 10

#define	SCB_CFSR_UNSTKERR_MASK 0x800u

#define	SCB_CFSR_UNSTKERR_SHIFT 11

#define	SCB_CFSR_STKERR_MASK 0x1000u

#define	SCB_CFSR_STKERR_SHIFT 12

#define	SCB_CFSR_LSPERR_MASK 0x2000u

#define	SCB_CFSR_LSPERR_SHIFT 13

#define	SCB_CFSR_BFARVALID_MASK 0x8000u

#define	SCB_CFSR_BFARVALID_SHIFT 15

#define	SCB_CFSR_UNDEFINSTR_MASK 0x10000u

#define	SCB_CFSR_UNDEFINSTR_SHIFT 16

#define	SCB_CFSR_INVSTATE_MASK 0x20000u

#define	SCB_CFSR_INVSTATE_SHIFT 17

#define	SCB_CFSR_INVPC_MASK 0x40000u

#define	SCB_CFSR_INVPC_SHIFT 18

#define	SCB_CFSR_NOCP_MASK 0x80000u

#define	SCB_CFSR_NOCP_SHIFT 19

#define	SCB_CFSR_UNALIGNED_MASK 0x1000000u

#define	SCB_CFSR_UNALIGNED_SHIFT 24

#define	SCB_CFSR_DIVBYZERO_MASK 0x2000000u

#define	SCB_CFSR_DIVBYZERO_SHIFT 25

#define	SCB_HFSR_VECTTBL_MASK 0x2u

#define	SCB_HFSR_VECTTBL_SHIFT 1

#define	SCB_HFSR_FORCED_MASK 0x40000000u

#define	SCB_HFSR_FORCED_SHIFT 30

#define	SCB_HFSR_DEBUGEVT_MASK 0x80000000u

#define	SCB_HFSR_DEBUGEVT_SHIFT 31

#define	SCB_DFSR_HALTED_MASK 0x1u

#define	SCB_DFSR_HALTED_SHIFT 0

#define	SCB_DFSR_BKPT_MASK 0x2u

#define	SCB_DFSR_BKPT_SHIFT 1

#define	SCB_DFSR_DWTTRAP_MASK 0x4u

#define	SCB_DFSR_DWTTRAP_SHIFT 2

#define	SCB_DFSR_VCATCH_MASK 0x8u

#define	SCB_DFSR_VCATCH_SHIFT 3

#define	SCB_DFSR_EXTERNAL_MASK 0x10u

#define	SCB_DFSR_EXTERNAL_SHIFT 4

#define	SCB_MMFAR_ADDRESS_MASK 0xFFFFFFFFu

#define	SCB_MMFAR_ADDRESS_SHIFT 0

#define	SCB_MMFAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<SCB_MMFAR_ADDRESS_SHIFT))&SCB_MMFAR_ADDRESS_MASK)

#define	SCB_BFAR_ADDRESS_MASK 0xFFFFFFFFu

#define	SCB_BFAR_ADDRESS_SHIFT 0

#define	SCB_BFAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<SCB_BFAR_ADDRESS_SHIFT))&SCB_BFAR_ADDRESS_MASK)

#define	SCB_AFSR_AUXFAULT_MASK 0xFFFFFFFFu

#define	SCB_AFSR_AUXFAULT_SHIFT 0

#define	SCB_AFSR_AUXFAULT(x) (((uint32_t)(((uint32_t)(x))<<SCB_AFSR_AUXFAULT_SHIFT))&SCB_AFSR_AUXFAULT_MASK)

#define	SCB_CPACR_CP10_MASK 0x300000u

#define	SCB_CPACR_CP10_SHIFT 20

#define	SCB_CPACR_CP10(x) (((uint32_t)(((uint32_t)(x))<<SCB_CPACR_CP10_SHIFT))&SCB_CPACR_CP10_MASK)

#define	SCB_CPACR_CP11_MASK 0xC00000u

#define	SCB_CPACR_CP11_SHIFT 22

#define	SCB_CPACR_CP11(x) (((uint32_t)(((uint32_t)(x))<<SCB_CPACR_CP11_SHIFT))&SCB_CPACR_CP11_MASK)

#define	SystemControl_BASE_PTR ((SCB_MemMapPtr)0xE000E000u)

#define	SCB_BASE_PTRS { SystemControl_BASE_PTR }

#define	SCB_ACTLR SCB_ACTLR_REG(SystemControl_BASE_PTR)

#define	SCB_CPUID SCB_CPUID_REG(SystemControl_BASE_PTR)

#define	SCB_ICSR SCB_ICSR_REG(SystemControl_BASE_PTR)

#define	SCB_VTOR SCB_VTOR_REG(SystemControl_BASE_PTR)

#define	SCB_AIRCR SCB_AIRCR_REG(SystemControl_BASE_PTR)

#define	SCB_SCR SCB_SCR_REG(SystemControl_BASE_PTR)

#define	SCB_CCR SCB_CCR_REG(SystemControl_BASE_PTR)

#define	SCB_SHPR1 SCB_SHPR1_REG(SystemControl_BASE_PTR)

#define	SCB_SHPR2 SCB_SHPR2_REG(SystemControl_BASE_PTR)

#define	SCB_SHPR3 SCB_SHPR3_REG(SystemControl_BASE_PTR)

#define	SCB_SHCSR SCB_SHCSR_REG(SystemControl_BASE_PTR)

#define	SCB_CFSR SCB_CFSR_REG(SystemControl_BASE_PTR)

#define	SCB_HFSR SCB_HFSR_REG(SystemControl_BASE_PTR)

#define	SCB_DFSR SCB_DFSR_REG(SystemControl_BASE_PTR)

#define	SCB_MMFAR SCB_MMFAR_REG(SystemControl_BASE_PTR)

#define	SCB_BFAR SCB_BFAR_REG(SystemControl_BASE_PTR)

#define	SCB_AFSR SCB_AFSR_REG(SystemControl_BASE_PTR)

#define	SCB_CPACR SCB_CPACR_REG(SystemControl_BASE_PTR)

#define	SDHC_DSADDR_REG(base) ((base)->DSADDR)

#define	SDHC_BLKATTR_REG(base) ((base)->BLKATTR)

#define	SDHC_CMDARG_REG(base) ((base)->CMDARG)

#define	SDHC_XFERTYP_REG(base) ((base)->XFERTYP)

#define	SDHC_CMDRSP_REG(base, index) ((base)->CMDRSP[index])

#define	SDHC_DATPORT_REG(base) ((base)->DATPORT)

#define	SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT)

#define	SDHC_PROCTL_REG(base) ((base)->PROCTL)

#define	SDHC_SYSCTL_REG(base) ((base)->SYSCTL)

#define	SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT)

#define	SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN)

#define	SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN)

#define	SDHC_AC12ERR_REG(base) ((base)->AC12ERR)

#define	SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT)

#define	SDHC_WML_REG(base) ((base)->WML)

#define	SDHC_FEVT_REG(base) ((base)->FEVT)

#define	SDHC_ADMAES_REG(base) ((base)->ADMAES)

#define	SDHC_ADSADDR_REG(base) ((base)->ADSADDR)

#define	SDHC_VENDOR_REG(base) ((base)->VENDOR)

#define	SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT)

#define	SDHC_HOSTVER_REG(base) ((base)->HOSTVER)

#define	SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu

#define	SDHC_DSADDR_DSADDR_SHIFT 2

#define	SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)

#define	SDHC_BLKATTR_BLKSIZE_MASK 0x1FFFu

#define	SDHC_BLKATTR_BLKSIZE_SHIFT 0

#define	SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)

#define	SDHC_BLKATTR_BLKCNT_MASK 0xFFFF0000u

#define	SDHC_BLKATTR_BLKCNT_SHIFT 16

#define	SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)

#define	SDHC_CMDARG_CMDARG_MASK 0xFFFFFFFFu

#define	SDHC_CMDARG_CMDARG_SHIFT 0

#define	SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)

#define	SDHC_XFERTYP_DMAEN_MASK 0x1u

#define	SDHC_XFERTYP_DMAEN_SHIFT 0

#define	SDHC_XFERTYP_BCEN_MASK 0x2u

#define	SDHC_XFERTYP_BCEN_SHIFT 1

#define	SDHC_XFERTYP_AC12EN_MASK 0x4u

#define	SDHC_XFERTYP_AC12EN_SHIFT 2

#define	SDHC_XFERTYP_DTDSEL_MASK 0x10u

#define	SDHC_XFERTYP_DTDSEL_SHIFT 4

#define	SDHC_XFERTYP_MSBSEL_MASK 0x20u

#define	SDHC_XFERTYP_MSBSEL_SHIFT 5

#define	SDHC_XFERTYP_RSPTYP_MASK 0x30000u

#define	SDHC_XFERTYP_RSPTYP_SHIFT 16

#define	SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)

#define	SDHC_XFERTYP_CCCEN_MASK 0x80000u

#define	SDHC_XFERTYP_CCCEN_SHIFT 19

#define	SDHC_XFERTYP_CICEN_MASK 0x100000u

#define	SDHC_XFERTYP_CICEN_SHIFT 20

#define	SDHC_XFERTYP_DPSEL_MASK 0x200000u

#define	SDHC_XFERTYP_DPSEL_SHIFT 21

#define	SDHC_XFERTYP_CMDTYP_MASK 0xC00000u

#define	SDHC_XFERTYP_CMDTYP_SHIFT 22

#define	SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)

#define	SDHC_XFERTYP_CMDINX_MASK 0x3F000000u

#define	SDHC_XFERTYP_CMDINX_SHIFT 24

#define	SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)

#define	SDHC_CMDRSP_CMDRSP0_MASK 0xFFFFFFFFu

#define	SDHC_CMDRSP_CMDRSP0_SHIFT 0

#define	SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)

#define	SDHC_CMDRSP_CMDRSP1_MASK 0xFFFFFFFFu

#define	SDHC_CMDRSP_CMDRSP1_SHIFT 0

#define	SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)

#define	SDHC_CMDRSP_CMDRSP2_MASK 0xFFFFFFFFu

#define	SDHC_CMDRSP_CMDRSP2_SHIFT 0

#define	SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)

#define	SDHC_CMDRSP_CMDRSP3_MASK 0xFFFFFFFFu

#define	SDHC_CMDRSP_CMDRSP3_SHIFT 0

#define	SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)

#define	SDHC_DATPORT_DATCONT_MASK 0xFFFFFFFFu

#define	SDHC_DATPORT_DATCONT_SHIFT 0

#define	SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)

#define	SDHC_PRSSTAT_CIHB_MASK 0x1u

#define	SDHC_PRSSTAT_CIHB_SHIFT 0

#define	SDHC_PRSSTAT_CDIHB_MASK 0x2u

#define	SDHC_PRSSTAT_CDIHB_SHIFT 1

#define	SDHC_PRSSTAT_DLA_MASK 0x4u

#define	SDHC_PRSSTAT_DLA_SHIFT 2

#define	SDHC_PRSSTAT_SDSTB_MASK 0x8u

#define	SDHC_PRSSTAT_SDSTB_SHIFT 3

#define	SDHC_PRSSTAT_IPGOFF_MASK 0x10u

#define	SDHC_PRSSTAT_IPGOFF_SHIFT 4

#define	SDHC_PRSSTAT_HCKOFF_MASK 0x20u

#define	SDHC_PRSSTAT_HCKOFF_SHIFT 5

#define	SDHC_PRSSTAT_PEROFF_MASK 0x40u

#define	SDHC_PRSSTAT_PEROFF_SHIFT 6

#define	SDHC_PRSSTAT_SDOFF_MASK 0x80u

#define	SDHC_PRSSTAT_SDOFF_SHIFT 7

#define	SDHC_PRSSTAT_WTA_MASK 0x100u

#define	SDHC_PRSSTAT_WTA_SHIFT 8

#define	SDHC_PRSSTAT_RTA_MASK 0x200u

#define	SDHC_PRSSTAT_RTA_SHIFT 9

#define	SDHC_PRSSTAT_BWEN_MASK 0x400u

#define	SDHC_PRSSTAT_BWEN_SHIFT 10

#define	SDHC_PRSSTAT_BREN_MASK 0x800u

#define	SDHC_PRSSTAT_BREN_SHIFT 11

#define	SDHC_PRSSTAT_CINS_MASK 0x10000u

#define	SDHC_PRSSTAT_CINS_SHIFT 16

#define	SDHC_PRSSTAT_CLSL_MASK 0x800000u

#define	SDHC_PRSSTAT_CLSL_SHIFT 23

#define	SDHC_PRSSTAT_DLSL_MASK 0xFF000000u

#define	SDHC_PRSSTAT_DLSL_SHIFT 24

#define	SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)

#define	SDHC_PROCTL_LCTL_MASK 0x1u

#define	SDHC_PROCTL_LCTL_SHIFT 0

#define	SDHC_PROCTL_DTW_MASK 0x6u

#define	SDHC_PROCTL_DTW_SHIFT 1

#define	SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)

#define	SDHC_PROCTL_D3CD_MASK 0x8u

#define	SDHC_PROCTL_D3CD_SHIFT 3

#define	SDHC_PROCTL_EMODE_MASK 0x30u

#define	SDHC_PROCTL_EMODE_SHIFT 4

#define	SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)

#define	SDHC_PROCTL_CDTL_MASK 0x40u

#define	SDHC_PROCTL_CDTL_SHIFT 6

#define	SDHC_PROCTL_CDSS_MASK 0x80u

#define	SDHC_PROCTL_CDSS_SHIFT 7

#define	SDHC_PROCTL_DMAS_MASK 0x300u

#define	SDHC_PROCTL_DMAS_SHIFT 8

#define	SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)

#define	SDHC_PROCTL_SABGREQ_MASK 0x10000u

#define	SDHC_PROCTL_SABGREQ_SHIFT 16

#define	SDHC_PROCTL_CREQ_MASK 0x20000u

#define	SDHC_PROCTL_CREQ_SHIFT 17

#define	SDHC_PROCTL_RWCTL_MASK 0x40000u

#define	SDHC_PROCTL_RWCTL_SHIFT 18

#define	SDHC_PROCTL_IABG_MASK 0x80000u

#define	SDHC_PROCTL_IABG_SHIFT 19

#define	SDHC_PROCTL_WECINT_MASK 0x1000000u

#define	SDHC_PROCTL_WECINT_SHIFT 24

#define	SDHC_PROCTL_WECINS_MASK 0x2000000u

#define	SDHC_PROCTL_WECINS_SHIFT 25

#define	SDHC_PROCTL_WECRM_MASK 0x4000000u

#define	SDHC_PROCTL_WECRM_SHIFT 26

#define	SDHC_SYSCTL_IPGEN_MASK 0x1u

#define	SDHC_SYSCTL_IPGEN_SHIFT 0

#define	SDHC_SYSCTL_HCKEN_MASK 0x2u

#define	SDHC_SYSCTL_HCKEN_SHIFT 1

#define	SDHC_SYSCTL_PEREN_MASK 0x4u

#define	SDHC_SYSCTL_PEREN_SHIFT 2

#define	SDHC_SYSCTL_SDCLKEN_MASK 0x8u

#define	SDHC_SYSCTL_SDCLKEN_SHIFT 3

#define	SDHC_SYSCTL_DVS_MASK 0xF0u

#define	SDHC_SYSCTL_DVS_SHIFT 4

#define	SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)

#define	SDHC_SYSCTL_SDCLKFS_MASK 0xFF00u

#define	SDHC_SYSCTL_SDCLKFS_SHIFT 8

#define	SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)

#define	SDHC_SYSCTL_DTOCV_MASK 0xF0000u

#define	SDHC_SYSCTL_DTOCV_SHIFT 16

#define	SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)

#define	SDHC_SYSCTL_RSTA_MASK 0x1000000u

#define	SDHC_SYSCTL_RSTA_SHIFT 24

#define	SDHC_SYSCTL_RSTC_MASK 0x2000000u

#define	SDHC_SYSCTL_RSTC_SHIFT 25

#define	SDHC_SYSCTL_RSTD_MASK 0x4000000u

#define	SDHC_SYSCTL_RSTD_SHIFT 26

#define	SDHC_SYSCTL_INITA_MASK 0x8000000u

#define	SDHC_SYSCTL_INITA_SHIFT 27

#define	SDHC_IRQSTAT_CC_MASK 0x1u

#define	SDHC_IRQSTAT_CC_SHIFT 0

#define	SDHC_IRQSTAT_TC_MASK 0x2u

#define	SDHC_IRQSTAT_TC_SHIFT 1

#define	SDHC_IRQSTAT_BGE_MASK 0x4u

#define	SDHC_IRQSTAT_BGE_SHIFT 2

#define	SDHC_IRQSTAT_DINT_MASK 0x8u

#define	SDHC_IRQSTAT_DINT_SHIFT 3

#define	SDHC_IRQSTAT_BWR_MASK 0x10u

#define	SDHC_IRQSTAT_BWR_SHIFT 4

#define	SDHC_IRQSTAT_BRR_MASK 0x20u

#define	SDHC_IRQSTAT_BRR_SHIFT 5

#define	SDHC_IRQSTAT_CINS_MASK 0x40u

#define	SDHC_IRQSTAT_CINS_SHIFT 6

#define	SDHC_IRQSTAT_CRM_MASK 0x80u

#define	SDHC_IRQSTAT_CRM_SHIFT 7

#define	SDHC_IRQSTAT_CINT_MASK 0x100u

#define	SDHC_IRQSTAT_CINT_SHIFT 8

#define	SDHC_IRQSTAT_CTOE_MASK 0x10000u

#define	SDHC_IRQSTAT_CTOE_SHIFT 16

#define	SDHC_IRQSTAT_CCE_MASK 0x20000u

#define	SDHC_IRQSTAT_CCE_SHIFT 17

#define	SDHC_IRQSTAT_CEBE_MASK 0x40000u

#define	SDHC_IRQSTAT_CEBE_SHIFT 18

#define	SDHC_IRQSTAT_CIE_MASK 0x80000u

#define	SDHC_IRQSTAT_CIE_SHIFT 19

#define	SDHC_IRQSTAT_DTOE_MASK 0x100000u

#define	SDHC_IRQSTAT_DTOE_SHIFT 20

#define	SDHC_IRQSTAT_DCE_MASK 0x200000u

#define	SDHC_IRQSTAT_DCE_SHIFT 21

#define	SDHC_IRQSTAT_DEBE_MASK 0x400000u

#define	SDHC_IRQSTAT_DEBE_SHIFT 22

#define	SDHC_IRQSTAT_AC12E_MASK 0x1000000u

#define	SDHC_IRQSTAT_AC12E_SHIFT 24

#define	SDHC_IRQSTAT_DMAE_MASK 0x10000000u

#define	SDHC_IRQSTAT_DMAE_SHIFT 28

#define	SDHC_IRQSTATEN_CCSEN_MASK 0x1u

#define	SDHC_IRQSTATEN_CCSEN_SHIFT 0

#define	SDHC_IRQSTATEN_TCSEN_MASK 0x2u

#define	SDHC_IRQSTATEN_TCSEN_SHIFT 1

#define	SDHC_IRQSTATEN_BGESEN_MASK 0x4u

#define	SDHC_IRQSTATEN_BGESEN_SHIFT 2

#define	SDHC_IRQSTATEN_DINTSEN_MASK 0x8u

#define	SDHC_IRQSTATEN_DINTSEN_SHIFT 3

#define	SDHC_IRQSTATEN_BWRSEN_MASK 0x10u

#define	SDHC_IRQSTATEN_BWRSEN_SHIFT 4

#define	SDHC_IRQSTATEN_BRRSEN_MASK 0x20u

#define	SDHC_IRQSTATEN_BRRSEN_SHIFT 5

#define	SDHC_IRQSTATEN_CINSEN_MASK 0x40u

#define	SDHC_IRQSTATEN_CINSEN_SHIFT 6

#define	SDHC_IRQSTATEN_CRMSEN_MASK 0x80u

#define	SDHC_IRQSTATEN_CRMSEN_SHIFT 7

#define	SDHC_IRQSTATEN_CINTSEN_MASK 0x100u

#define	SDHC_IRQSTATEN_CINTSEN_SHIFT 8

#define	SDHC_IRQSTATEN_CTOESEN_MASK 0x10000u

#define	SDHC_IRQSTATEN_CTOESEN_SHIFT 16

#define	SDHC_IRQSTATEN_CCESEN_MASK 0x20000u

#define	SDHC_IRQSTATEN_CCESEN_SHIFT 17

#define	SDHC_IRQSTATEN_CEBESEN_MASK 0x40000u

#define	SDHC_IRQSTATEN_CEBESEN_SHIFT 18

#define	SDHC_IRQSTATEN_CIESEN_MASK 0x80000u

#define	SDHC_IRQSTATEN_CIESEN_SHIFT 19

#define	SDHC_IRQSTATEN_DTOESEN_MASK 0x100000u

#define	SDHC_IRQSTATEN_DTOESEN_SHIFT 20

#define	SDHC_IRQSTATEN_DCESEN_MASK 0x200000u

#define	SDHC_IRQSTATEN_DCESEN_SHIFT 21

#define	SDHC_IRQSTATEN_DEBESEN_MASK 0x400000u

#define	SDHC_IRQSTATEN_DEBESEN_SHIFT 22

#define	SDHC_IRQSTATEN_AC12ESEN_MASK 0x1000000u

#define	SDHC_IRQSTATEN_AC12ESEN_SHIFT 24

#define	SDHC_IRQSTATEN_DMAESEN_MASK 0x10000000u

#define	SDHC_IRQSTATEN_DMAESEN_SHIFT 28

#define	SDHC_IRQSIGEN_CCIEN_MASK 0x1u

#define	SDHC_IRQSIGEN_CCIEN_SHIFT 0

#define	SDHC_IRQSIGEN_TCIEN_MASK 0x2u

#define	SDHC_IRQSIGEN_TCIEN_SHIFT 1

#define	SDHC_IRQSIGEN_BGEIEN_MASK 0x4u

#define	SDHC_IRQSIGEN_BGEIEN_SHIFT 2

#define	SDHC_IRQSIGEN_DINTIEN_MASK 0x8u

#define	SDHC_IRQSIGEN_DINTIEN_SHIFT 3

#define	SDHC_IRQSIGEN_BWRIEN_MASK 0x10u

#define	SDHC_IRQSIGEN_BWRIEN_SHIFT 4

#define	SDHC_IRQSIGEN_BRRIEN_MASK 0x20u

#define	SDHC_IRQSIGEN_BRRIEN_SHIFT 5

#define	SDHC_IRQSIGEN_CINSIEN_MASK 0x40u

#define	SDHC_IRQSIGEN_CINSIEN_SHIFT 6

#define	SDHC_IRQSIGEN_CRMIEN_MASK 0x80u

#define	SDHC_IRQSIGEN_CRMIEN_SHIFT 7

#define	SDHC_IRQSIGEN_CINTIEN_MASK 0x100u

#define	SDHC_IRQSIGEN_CINTIEN_SHIFT 8

#define	SDHC_IRQSIGEN_CTOEIEN_MASK 0x10000u

#define	SDHC_IRQSIGEN_CTOEIEN_SHIFT 16

#define	SDHC_IRQSIGEN_CCEIEN_MASK 0x20000u

#define	SDHC_IRQSIGEN_CCEIEN_SHIFT 17

#define	SDHC_IRQSIGEN_CEBEIEN_MASK 0x40000u

#define	SDHC_IRQSIGEN_CEBEIEN_SHIFT 18

#define	SDHC_IRQSIGEN_CIEIEN_MASK 0x80000u

#define	SDHC_IRQSIGEN_CIEIEN_SHIFT 19

#define	SDHC_IRQSIGEN_DTOEIEN_MASK 0x100000u

#define	SDHC_IRQSIGEN_DTOEIEN_SHIFT 20

#define	SDHC_IRQSIGEN_DCEIEN_MASK 0x200000u

#define	SDHC_IRQSIGEN_DCEIEN_SHIFT 21

#define	SDHC_IRQSIGEN_DEBEIEN_MASK 0x400000u

#define	SDHC_IRQSIGEN_DEBEIEN_SHIFT 22

#define	SDHC_IRQSIGEN_AC12EIEN_MASK 0x1000000u

#define	SDHC_IRQSIGEN_AC12EIEN_SHIFT 24

#define	SDHC_IRQSIGEN_DMAEIEN_MASK 0x10000000u

#define	SDHC_IRQSIGEN_DMAEIEN_SHIFT 28

#define	SDHC_AC12ERR_AC12NE_MASK 0x1u

#define	SDHC_AC12ERR_AC12NE_SHIFT 0

#define	SDHC_AC12ERR_AC12TOE_MASK 0x2u

#define	SDHC_AC12ERR_AC12TOE_SHIFT 1

#define	SDHC_AC12ERR_AC12EBE_MASK 0x4u

#define	SDHC_AC12ERR_AC12EBE_SHIFT 2

#define	SDHC_AC12ERR_AC12CE_MASK 0x8u

#define	SDHC_AC12ERR_AC12CE_SHIFT 3

#define	SDHC_AC12ERR_AC12IE_MASK 0x10u

#define	SDHC_AC12ERR_AC12IE_SHIFT 4

#define	SDHC_AC12ERR_CNIBAC12E_MASK 0x80u

#define	SDHC_AC12ERR_CNIBAC12E_SHIFT 7

#define	SDHC_HTCAPBLT_MBL_MASK 0x70000u

#define	SDHC_HTCAPBLT_MBL_SHIFT 16

#define	SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)

#define	SDHC_HTCAPBLT_ADMAS_MASK 0x100000u

#define	SDHC_HTCAPBLT_ADMAS_SHIFT 20

#define	SDHC_HTCAPBLT_HSS_MASK 0x200000u

#define	SDHC_HTCAPBLT_HSS_SHIFT 21

#define	SDHC_HTCAPBLT_DMAS_MASK 0x400000u

#define	SDHC_HTCAPBLT_DMAS_SHIFT 22

#define	SDHC_HTCAPBLT_SRS_MASK 0x800000u

#define	SDHC_HTCAPBLT_SRS_SHIFT 23

#define	SDHC_HTCAPBLT_VS33_MASK 0x1000000u

#define	SDHC_HTCAPBLT_VS33_SHIFT 24

#define	SDHC_HTCAPBLT_VS30_MASK 0x2000000u

#define	SDHC_HTCAPBLT_VS30_SHIFT 25

#define	SDHC_HTCAPBLT_VS18_MASK 0x4000000u

#define	SDHC_HTCAPBLT_VS18_SHIFT 26

#define	SDHC_WML_RDWML_MASK 0xFFu

#define	SDHC_WML_RDWML_SHIFT 0

#define	SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)

#define	SDHC_WML_WRWML_MASK 0xFF0000u

#define	SDHC_WML_WRWML_SHIFT 16

#define	SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)

#define	SDHC_WML_WRBRSTLEN_MASK 0x1F000000u

#define	SDHC_WML_WRBRSTLEN_SHIFT 24

#define	SDHC_WML_WRBRSTLEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRBRSTLEN_SHIFT))&SDHC_WML_WRBRSTLEN_MASK)

#define	SDHC_FEVT_AC12NE_MASK 0x1u

#define	SDHC_FEVT_AC12NE_SHIFT 0

#define	SDHC_FEVT_AC12TOE_MASK 0x2u

#define	SDHC_FEVT_AC12TOE_SHIFT 1

#define	SDHC_FEVT_AC12CE_MASK 0x4u

#define	SDHC_FEVT_AC12CE_SHIFT 2

#define	SDHC_FEVT_AC12EBE_MASK 0x8u

#define	SDHC_FEVT_AC12EBE_SHIFT 3

#define	SDHC_FEVT_AC12IE_MASK 0x10u

#define	SDHC_FEVT_AC12IE_SHIFT 4

#define	SDHC_FEVT_CNIBAC12E_MASK 0x80u

#define	SDHC_FEVT_CNIBAC12E_SHIFT 7

#define	SDHC_FEVT_CTOE_MASK 0x10000u

#define	SDHC_FEVT_CTOE_SHIFT 16

#define	SDHC_FEVT_CCE_MASK 0x20000u

#define	SDHC_FEVT_CCE_SHIFT 17

#define	SDHC_FEVT_CEBE_MASK 0x40000u

#define	SDHC_FEVT_CEBE_SHIFT 18

#define	SDHC_FEVT_CIE_MASK 0x80000u

#define	SDHC_FEVT_CIE_SHIFT 19

#define	SDHC_FEVT_DTOE_MASK 0x100000u

#define	SDHC_FEVT_DTOE_SHIFT 20

#define	SDHC_FEVT_DCE_MASK 0x200000u

#define	SDHC_FEVT_DCE_SHIFT 21

#define	SDHC_FEVT_DEBE_MASK 0x400000u

#define	SDHC_FEVT_DEBE_SHIFT 22

#define	SDHC_FEVT_AC12E_MASK 0x1000000u

#define	SDHC_FEVT_AC12E_SHIFT 24

#define	SDHC_FEVT_DMAE_MASK 0x10000000u

#define	SDHC_FEVT_DMAE_SHIFT 28

#define	SDHC_FEVT_CINT_MASK 0x80000000u

#define	SDHC_FEVT_CINT_SHIFT 31

#define	SDHC_ADMAES_ADMAES_MASK 0x3u

#define	SDHC_ADMAES_ADMAES_SHIFT 0

#define	SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)

#define	SDHC_ADMAES_ADMALME_MASK 0x4u

#define	SDHC_ADMAES_ADMALME_SHIFT 2

#define	SDHC_ADMAES_ADMADCE_MASK 0x8u

#define	SDHC_ADMAES_ADMADCE_SHIFT 3

#define	SDHC_ADSADDR_ADSADDR_MASK 0xFFFFFFFCu

#define	SDHC_ADSADDR_ADSADDR_SHIFT 2

#define	SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)

#define	SDHC_VENDOR_EXTDMAEN_MASK 0x1u

#define	SDHC_VENDOR_EXTDMAEN_SHIFT 0

#define	SDHC_VENDOR_EXBLKNU_MASK 0x2u

#define	SDHC_VENDOR_EXBLKNU_SHIFT 1

#define	SDHC_VENDOR_INTSTVAL_MASK 0xFF0000u

#define	SDHC_VENDOR_INTSTVAL_SHIFT 16

#define	SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)

#define	SDHC_MMCBOOT_DTOCVACK_MASK 0xFu

#define	SDHC_MMCBOOT_DTOCVACK_SHIFT 0

#define	SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)

#define	SDHC_MMCBOOT_BOOTACK_MASK 0x10u

#define	SDHC_MMCBOOT_BOOTACK_SHIFT 4

#define	SDHC_MMCBOOT_BOOTMODE_MASK 0x20u

#define	SDHC_MMCBOOT_BOOTMODE_SHIFT 5

#define	SDHC_MMCBOOT_BOOTEN_MASK 0x40u

#define	SDHC_MMCBOOT_BOOTEN_SHIFT 6

#define	SDHC_MMCBOOT_AUTOSABGEN_MASK 0x80u

#define	SDHC_MMCBOOT_AUTOSABGEN_SHIFT 7

#define	SDHC_MMCBOOT_BOOTBLKCNT_MASK 0xFFFF0000u

#define	SDHC_MMCBOOT_BOOTBLKCNT_SHIFT 16

#define	SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)

#define	SDHC_HOSTVER_SVN_MASK 0xFFu

#define	SDHC_HOSTVER_SVN_SHIFT 0

#define	SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)

#define	SDHC_HOSTVER_VVN_MASK 0xFF00u

#define	SDHC_HOSTVER_VVN_SHIFT 8

#define	SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)

#define	SDHC_BASE_PTR ((SDHC_MemMapPtr)0x400B1000u)

#define	SDHC_BASE_PTRS { SDHC_BASE_PTR }

#define	SDHC_DSADDR SDHC_DSADDR_REG(SDHC_BASE_PTR)

#define	SDHC_BLKATTR SDHC_BLKATTR_REG(SDHC_BASE_PTR)

#define	SDHC_CMDARG SDHC_CMDARG_REG(SDHC_BASE_PTR)

#define	SDHC_XFERTYP SDHC_XFERTYP_REG(SDHC_BASE_PTR)

#define	SDHC_CMDRSP0 SDHC_CMDRSP_REG(SDHC_BASE_PTR,0)

#define	SDHC_CMDRSP1 SDHC_CMDRSP_REG(SDHC_BASE_PTR,1)

#define	SDHC_CMDRSP2 SDHC_CMDRSP_REG(SDHC_BASE_PTR,2)

#define	SDHC_CMDRSP3 SDHC_CMDRSP_REG(SDHC_BASE_PTR,3)

#define	SDHC_DATPORT SDHC_DATPORT_REG(SDHC_BASE_PTR)

#define	SDHC_PRSSTAT SDHC_PRSSTAT_REG(SDHC_BASE_PTR)

#define	SDHC_PROCTL SDHC_PROCTL_REG(SDHC_BASE_PTR)

#define	SDHC_SYSCTL SDHC_SYSCTL_REG(SDHC_BASE_PTR)

#define	SDHC_IRQSTAT SDHC_IRQSTAT_REG(SDHC_BASE_PTR)

#define	SDHC_IRQSTATEN SDHC_IRQSTATEN_REG(SDHC_BASE_PTR)

#define	SDHC_IRQSIGEN SDHC_IRQSIGEN_REG(SDHC_BASE_PTR)

#define	SDHC_AC12ERR SDHC_AC12ERR_REG(SDHC_BASE_PTR)

#define	SDHC_HTCAPBLT SDHC_HTCAPBLT_REG(SDHC_BASE_PTR)

#define	SDHC_WML SDHC_WML_REG(SDHC_BASE_PTR)

#define	SDHC_FEVT SDHC_FEVT_REG(SDHC_BASE_PTR)

#define	SDHC_ADMAES SDHC_ADMAES_REG(SDHC_BASE_PTR)

#define	SDHC_ADSADDR SDHC_ADSADDR_REG(SDHC_BASE_PTR)

#define	SDHC_VENDOR SDHC_VENDOR_REG(SDHC_BASE_PTR)

#define	SDHC_MMCBOOT SDHC_MMCBOOT_REG(SDHC_BASE_PTR)

#define	SDHC_HOSTVER SDHC_HOSTVER_REG(SDHC_BASE_PTR)

#define	SDHC_CMDRSP(index) SDHC_CMDRSP_REG(SDHC_BASE_PTR,index)

#define	SIM_SOPT1_REG(base) ((base)->SOPT1)

#define	SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)

#define	SIM_SOPT2_REG(base) ((base)->SOPT2)

#define	SIM_SOPT4_REG(base) ((base)->SOPT4)

#define	SIM_SOPT5_REG(base) ((base)->SOPT5)

#define	SIM_SOPT6_REG(base) ((base)->SOPT6)

#define	SIM_SOPT7_REG(base) ((base)->SOPT7)

#define	SIM_SDID_REG(base) ((base)->SDID)

#define	SIM_SCGC1_REG(base) ((base)->SCGC1)

#define	SIM_SCGC2_REG(base) ((base)->SCGC2)

#define	SIM_SCGC3_REG(base) ((base)->SCGC3)

#define	SIM_SCGC4_REG(base) ((base)->SCGC4)

#define	SIM_SCGC5_REG(base) ((base)->SCGC5)

#define	SIM_SCGC6_REG(base) ((base)->SCGC6)

#define	SIM_SCGC7_REG(base) ((base)->SCGC7)

#define	SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)

#define	SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)

#define	SIM_FCFG1_REG(base) ((base)->FCFG1)

#define	SIM_FCFG2_REG(base) ((base)->FCFG2)

#define	SIM_UIDH_REG(base) ((base)->UIDH)

#define	SIM_UIDMH_REG(base) ((base)->UIDMH)

#define	SIM_UIDML_REG(base) ((base)->UIDML)

#define	SIM_UIDL_REG(base) ((base)->UIDL)

#define	SIM_CLKDIV3_REG(base) ((base)->CLKDIV3)

#define	SIM_CLKDIV4_REG(base) ((base)->CLKDIV4)

#define	SIM_MCR_REG(base) ((base)->MCR)

#define	SIM_SOPT1_RAMSIZE_MASK 0xF000u

#define	SIM_SOPT1_RAMSIZE_SHIFT 12

#define	SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)

#define	SIM_SOPT1_OSC32KSEL_MASK 0x80000u

#define	SIM_SOPT1_OSC32KSEL_SHIFT 19

#define	SIM_SOPT1_USBVSTBY_MASK 0x20000000u

#define	SIM_SOPT1_USBVSTBY_SHIFT 29

#define	SIM_SOPT1_USBSSTBY_MASK 0x40000000u

#define	SIM_SOPT1_USBSSTBY_SHIFT 30

#define	SIM_SOPT1_USBREGEN_MASK 0x80000000u

#define	SIM_SOPT1_USBREGEN_SHIFT 31

#define	SIM_SOPT1CFG_URWE_MASK 0x1000000u

#define	SIM_SOPT1CFG_URWE_SHIFT 24

#define	SIM_SOPT1CFG_UVSWE_MASK 0x2000000u

#define	SIM_SOPT1CFG_UVSWE_SHIFT 25

#define	SIM_SOPT1CFG_USSWE_MASK 0x4000000u

#define	SIM_SOPT1CFG_USSWE_SHIFT 26

#define	SIM_SOPT2_USBHSRC_MASK 0xCu

#define	SIM_SOPT2_USBHSRC_SHIFT 2

#define	SIM_SOPT2_USBHSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_USBHSRC_SHIFT))&SIM_SOPT2_USBHSRC_MASK)

#define	SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u

#define	SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4

#define	SIM_SOPT2_CLKOUTSEL_MASK 0xE0u

#define	SIM_SOPT2_CLKOUTSEL_SHIFT 5

#define	SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)

#define	SIM_SOPT2_FBSL_MASK 0x300u

#define	SIM_SOPT2_FBSL_SHIFT 8

#define	SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)

#define	SIM_SOPT2_CMTUARTPAD_MASK 0x800u

#define	SIM_SOPT2_CMTUARTPAD_SHIFT 11

#define	SIM_SOPT2_TRACECLKSEL_MASK 0x1000u

#define	SIM_SOPT2_TRACECLKSEL_SHIFT 12

#define	SIM_SOPT2_LCDC_CLKSEL_MASK 0x4000u

#define	SIM_SOPT2_LCDC_CLKSEL_SHIFT 14

#define	SIM_SOPT2_NFC_CLKSEL_MASK 0x8000u

#define	SIM_SOPT2_NFC_CLKSEL_SHIFT 15

#define	SIM_SOPT2_PLLFLLSEL_MASK 0x30000u

#define	SIM_SOPT2_PLLFLLSEL_SHIFT 16

#define	SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)

#define	SIM_SOPT2_USBF_CLKSEL_MASK 0x40000u

#define	SIM_SOPT2_USBF_CLKSEL_SHIFT 18

#define	SIM_SOPT2_TIMESRC_MASK 0x300000u

#define	SIM_SOPT2_TIMESRC_SHIFT 20

#define	SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)

#define	SIM_SOPT2_USBFSRC_MASK 0xC00000u

#define	SIM_SOPT2_USBFSRC_SHIFT 22

#define	SIM_SOPT2_USBFSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_USBFSRC_SHIFT))&SIM_SOPT2_USBFSRC_MASK)

#define	SIM_SOPT2_LCDCSRC_MASK 0xC000000u

#define	SIM_SOPT2_LCDCSRC_SHIFT 26

#define	SIM_SOPT2_LCDCSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LCDCSRC_SHIFT))&SIM_SOPT2_LCDCSRC_MASK)

#define	SIM_SOPT2_ESDHCSRC_MASK 0x30000000u

#define	SIM_SOPT2_ESDHCSRC_SHIFT 28

#define	SIM_SOPT2_ESDHCSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_ESDHCSRC_SHIFT))&SIM_SOPT2_ESDHCSRC_MASK)

#define	SIM_SOPT2_NFCSRC_MASK 0xC0000000u

#define	SIM_SOPT2_NFCSRC_SHIFT 30

#define	SIM_SOPT2_NFCSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_NFCSRC_SHIFT))&SIM_SOPT2_NFCSRC_MASK)

#define	SIM_SOPT4_FTM0FLT0_MASK 0x1u

#define	SIM_SOPT4_FTM0FLT0_SHIFT 0

#define	SIM_SOPT4_FTM0FLT1_MASK 0x2u

#define	SIM_SOPT4_FTM0FLT1_SHIFT 1

#define	SIM_SOPT4_FTM0FLT2_MASK 0x4u

#define	SIM_SOPT4_FTM0FLT2_SHIFT 2

#define	SIM_SOPT4_FTM0FLT3_MASK 0x8u

#define	SIM_SOPT4_FTM0FLT3_SHIFT 3

#define	SIM_SOPT4_FTM1FLT0_MASK 0x10u

#define	SIM_SOPT4_FTM1FLT0_SHIFT 4

#define	SIM_SOPT4_FTM2FLT0_MASK 0x100u

#define	SIM_SOPT4_FTM2FLT0_SHIFT 8

#define	SIM_SOPT4_FTM3FLT0_MASK 0x1000u

#define	SIM_SOPT4_FTM3FLT0_SHIFT 12

#define	SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u

#define	SIM_SOPT4_FTM1CH0SRC_SHIFT 18

#define	SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)

#define	SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u

#define	SIM_SOPT4_FTM2CH0SRC_SHIFT 20

#define	SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)

#define	SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u

#define	SIM_SOPT4_FTM0CLKSEL_SHIFT 24

#define	SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u

#define	SIM_SOPT4_FTM1CLKSEL_SHIFT 25

#define	SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u

#define	SIM_SOPT4_FTM2CLKSEL_SHIFT 26

#define	SIM_SOPT4_FTM3CLKSEL_MASK 0x8000000u

#define	SIM_SOPT4_FTM3CLKSEL_SHIFT 27

#define	SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u

#define	SIM_SOPT4_FTM0TRG0SRC_SHIFT 28

#define	SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u

#define	SIM_SOPT4_FTM0TRG1SRC_SHIFT 29

#define	SIM_SOPT4_FTM3TRG0SRC_MASK 0x40000000u

#define	SIM_SOPT4_FTM3TRG0SRC_SHIFT 30

#define	SIM_SOPT4_FTM3TRG1SRC_MASK 0x80000000u

#define	SIM_SOPT4_FTM3TRG1SRC_SHIFT 31

#define	SIM_SOPT5_UART0TXSRC_MASK 0x3u

#define	SIM_SOPT5_UART0TXSRC_SHIFT 0

#define	SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)

#define	SIM_SOPT5_UART0RXSRC_MASK 0xCu

#define	SIM_SOPT5_UART0RXSRC_SHIFT 2

#define	SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)

#define	SIM_SOPT5_UART1TXSRC_MASK 0x30u

#define	SIM_SOPT5_UART1TXSRC_SHIFT 4

#define	SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)

#define	SIM_SOPT5_UART1RXSRC_MASK 0xC0u

#define	SIM_SOPT5_UART1RXSRC_SHIFT 6

#define	SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)

#define	SIM_SOPT6_MCC_MASK 0xFFFFu

#define	SIM_SOPT6_MCC_SHIFT 0

#define	SIM_SOPT6_MCC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT6_MCC_SHIFT))&SIM_SOPT6_MCC_MASK)

#define	SIM_SOPT6_PCR_MASK 0xF0000u

#define	SIM_SOPT6_PCR_SHIFT 16

#define	SIM_SOPT6_PCR(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT6_PCR_SHIFT))&SIM_SOPT6_PCR_MASK)

#define	SIM_SOPT7_ADC0TRGSEL_MASK 0xFu

#define	SIM_SOPT7_ADC0TRGSEL_SHIFT 0

#define	SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)

#define	SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u

#define	SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4

#define	SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u

#define	SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7

#define	SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u

#define	SIM_SOPT7_ADC1TRGSEL_SHIFT 8

#define	SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)

#define	SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u

#define	SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12

#define	SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u

#define	SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15

#define	SIM_SOPT7_ADC2TRGSEL_MASK 0xF0000u

#define	SIM_SOPT7_ADC2TRGSEL_SHIFT 16

#define	SIM_SOPT7_ADC2TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC2TRGSEL_SHIFT))&SIM_SOPT7_ADC2TRGSEL_MASK)

#define	SIM_SOPT7_ADC2PRETRGSEL_MASK 0x100000u

#define	SIM_SOPT7_ADC2PRETRGSEL_SHIFT 20

#define	SIM_SOPT7_ADC2ALTTRGEN_MASK 0x800000u

#define	SIM_SOPT7_ADC2ALTTRGEN_SHIFT 23

#define	SIM_SOPT7_ADC3TRGSEL_MASK 0xF000000u

#define	SIM_SOPT7_ADC3TRGSEL_SHIFT 24

#define	SIM_SOPT7_ADC3TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC3TRGSEL_SHIFT))&SIM_SOPT7_ADC3TRGSEL_MASK)

#define	SIM_SOPT7_ADC3PRETRGSEL_MASK 0x10000000u

#define	SIM_SOPT7_ADC3PRETRGSEL_SHIFT 28

#define	SIM_SOPT7_ADC3ALTTRGEN_MASK 0x80000000u

#define	SIM_SOPT7_ADC3ALTTRGEN_SHIFT 31

#define	SIM_SDID_PINID_MASK 0xFu

#define	SIM_SDID_PINID_SHIFT 0

#define	SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)

#define	SIM_SDID_FAMID_MASK 0x70u

#define	SIM_SDID_FAMID_SHIFT 4

#define	SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)

#define	SIM_SDID_REVID_MASK 0xF000u

#define	SIM_SDID_REVID_SHIFT 12

#define	SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)

#define	SIM_SCGC1_OSC1_MASK 0x20u

#define	SIM_SCGC1_OSC1_SHIFT 5

#define	SIM_SCGC1_UART4_MASK 0x400u

#define	SIM_SCGC1_UART4_SHIFT 10

#define	SIM_SCGC1_UART5_MASK 0x800u

#define	SIM_SCGC1_UART5_SHIFT 11

#define	SIM_SCGC2_ENET_MASK 0x1u

#define	SIM_SCGC2_ENET_SHIFT 0

#define	SIM_SCGC2_DAC0_MASK 0x1000u

#define	SIM_SCGC2_DAC0_SHIFT 12

#define	SIM_SCGC2_DAC1_MASK 0x2000u

#define	SIM_SCGC2_DAC1_SHIFT 13

#define	SIM_SCGC3_RNGA_MASK 0x1u

#define	SIM_SCGC3_RNGA_SHIFT 0

#define	SIM_SCGC3_FLEXCAN1_MASK 0x10u

#define	SIM_SCGC3_FLEXCAN1_SHIFT 4

#define	SIM_SCGC3_NFC_MASK 0x100u

#define	SIM_SCGC3_NFC_SHIFT 8

#define	SIM_SCGC3_DSPI2_MASK 0x1000u

#define	SIM_SCGC3_DSPI2_SHIFT 12

#define	SIM_SCGC3_DDR_MASK 0x4000u

#define	SIM_SCGC3_DDR_SHIFT 14

#define	SIM_SCGC3_SAI1_MASK 0x8000u

#define	SIM_SCGC3_SAI1_SHIFT 15

#define	SIM_SCGC3_ESDHC_MASK 0x20000u

#define	SIM_SCGC3_ESDHC_SHIFT 17

#define	SIM_SCGC3_LCDC_MASK 0x400000u

#define	SIM_SCGC3_LCDC_SHIFT 22

#define	SIM_SCGC3_FTM2_MASK 0x1000000u

#define	SIM_SCGC3_FTM2_SHIFT 24

#define	SIM_SCGC3_FTM3_MASK 0x2000000u

#define	SIM_SCGC3_FTM3_SHIFT 25

#define	SIM_SCGC3_ADC1_MASK 0x8000000u

#define	SIM_SCGC3_ADC1_SHIFT 27

#define	SIM_SCGC3_ADC3_MASK 0x10000000u

#define	SIM_SCGC3_ADC3_SHIFT 28

#define	SIM_SCGC4_EWM_MASK 0x2u

#define	SIM_SCGC4_EWM_SHIFT 1

#define	SIM_SCGC4_CMT_MASK 0x4u

#define	SIM_SCGC4_CMT_SHIFT 2

#define	SIM_SCGC4_IIC0_MASK 0x40u

#define	SIM_SCGC4_IIC0_SHIFT 6

#define	SIM_SCGC4_IIC1_MASK 0x80u

#define	SIM_SCGC4_IIC1_SHIFT 7

#define	SIM_SCGC4_UART0_MASK 0x400u

#define	SIM_SCGC4_UART0_SHIFT 10

#define	SIM_SCGC4_UART1_MASK 0x800u

#define	SIM_SCGC4_UART1_SHIFT 11

#define	SIM_SCGC4_UART2_MASK 0x1000u

#define	SIM_SCGC4_UART2_SHIFT 12

#define	SIM_SCGC4_UART3_MASK 0x2000u

#define	SIM_SCGC4_UART3_SHIFT 13

#define	SIM_SCGC4_USBFS_MASK 0x40000u

#define	SIM_SCGC4_USBFS_SHIFT 18

#define	SIM_SCGC4_CMP_MASK 0x80000u

#define	SIM_SCGC4_CMP_SHIFT 19

#define	SIM_SCGC4_VREF_MASK 0x100000u

#define	SIM_SCGC4_VREF_SHIFT 20

#define	SIM_SCGC4_LLWU_MASK 0x10000000u

#define	SIM_SCGC4_LLWU_SHIFT 28

#define	SIM_SCGC5_LPTIMER_MASK 0x1u

#define	SIM_SCGC5_LPTIMER_SHIFT 0

#define	SIM_SCGC5_REGFILE_MASK 0x2u

#define	SIM_SCGC5_REGFILE_SHIFT 1

#define	SIM_SCGC5_DRYICE_MASK 0x4u

#define	SIM_SCGC5_DRYICE_SHIFT 2

#define	SIM_SCGC5_DRYICESECREG_MASK 0x8u

#define	SIM_SCGC5_DRYICESECREG_SHIFT 3

#define	SIM_SCGC5_TSI_MASK 0x20u

#define	SIM_SCGC5_TSI_SHIFT 5

#define	SIM_SCGC5_PORTA_MASK 0x200u

#define	SIM_SCGC5_PORTA_SHIFT 9

#define	SIM_SCGC5_PORTB_MASK 0x400u

#define	SIM_SCGC5_PORTB_SHIFT 10

#define	SIM_SCGC5_PORTC_MASK 0x800u

#define	SIM_SCGC5_PORTC_SHIFT 11

#define	SIM_SCGC5_PORTD_MASK 0x1000u

#define	SIM_SCGC5_PORTD_SHIFT 12

#define	SIM_SCGC5_PORTE_MASK 0x2000u

#define	SIM_SCGC5_PORTE_SHIFT 13

#define	SIM_SCGC5_PORTF_MASK 0x4000u

#define	SIM_SCGC5_PORTF_SHIFT 14

#define	SIM_SCGC6_DMAMUX0_MASK 0x2u

#define	SIM_SCGC6_DMAMUX0_SHIFT 1

#define	SIM_SCGC6_DMAMUX1_MASK 0x4u

#define	SIM_SCGC6_DMAMUX1_SHIFT 2

#define	SIM_SCGC6_FLEXCAN0_MASK 0x10u

#define	SIM_SCGC6_FLEXCAN0_SHIFT 4

#define	SIM_SCGC6_DSPI0_MASK 0x1000u

#define	SIM_SCGC6_DSPI0_SHIFT 12

#define	SIM_SCGC6_DSPI1_MASK 0x2000u

#define	SIM_SCGC6_DSPI1_SHIFT 13

#define	SIM_SCGC6_SAI0_MASK 0x8000u

#define	SIM_SCGC6_SAI0_SHIFT 15

#define	SIM_SCGC6_CRC_MASK 0x40000u

#define	SIM_SCGC6_CRC_SHIFT 18

#define	SIM_SCGC6_USBHS_MASK 0x100000u

#define	SIM_SCGC6_USBHS_SHIFT 20

#define	SIM_SCGC6_USBDCD_MASK 0x200000u

#define	SIM_SCGC6_USBDCD_SHIFT 21

#define	SIM_SCGC6_PDB_MASK 0x400000u

#define	SIM_SCGC6_PDB_SHIFT 22

#define	SIM_SCGC6_PIT_MASK 0x800000u

#define	SIM_SCGC6_PIT_SHIFT 23

#define	SIM_SCGC6_FTM0_MASK 0x1000000u

#define	SIM_SCGC6_FTM0_SHIFT 24

#define	SIM_SCGC6_FTM1_MASK 0x2000000u

#define	SIM_SCGC6_FTM1_SHIFT 25

#define	SIM_SCGC6_ADC0_MASK 0x8000000u

#define	SIM_SCGC6_ADC0_SHIFT 27

#define	SIM_SCGC6_ADC2_MASK 0x10000000u

#define	SIM_SCGC6_ADC2_SHIFT 28

#define	SIM_SCGC6_RTC_MASK 0x20000000u

#define	SIM_SCGC6_RTC_SHIFT 29

#define	SIM_SCGC7_FLEXBUS_MASK 0x1u

#define	SIM_SCGC7_FLEXBUS_SHIFT 0

#define	SIM_SCGC7_DMA_MASK 0x2u

#define	SIM_SCGC7_DMA_SHIFT 1

#define	SIM_SCGC7_MPU_MASK 0x4u

#define	SIM_SCGC7_MPU_SHIFT 2

#define	SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u

#define	SIM_CLKDIV1_OUTDIV4_SHIFT 16

#define	SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)

#define	SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u

#define	SIM_CLKDIV1_OUTDIV3_SHIFT 20

#define	SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)

#define	SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u

#define	SIM_CLKDIV1_OUTDIV2_SHIFT 24

#define	SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)

#define	SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u

#define	SIM_CLKDIV1_OUTDIV1_SHIFT 28

#define	SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)

#define	SIM_CLKDIV2_USBFSFRAC_MASK 0x1u

#define	SIM_CLKDIV2_USBFSFRAC_SHIFT 0

#define	SIM_CLKDIV2_USBFSDIV_MASK 0xEu

#define	SIM_CLKDIV2_USBFSDIV_SHIFT 1

#define	SIM_CLKDIV2_USBFSDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBFSDIV_SHIFT))&SIM_CLKDIV2_USBFSDIV_MASK)

#define	SIM_CLKDIV2_USBHSFRAC_MASK 0x100u

#define	SIM_CLKDIV2_USBHSFRAC_SHIFT 8

#define	SIM_CLKDIV2_USBHSDIV_MASK 0xE00u

#define	SIM_CLKDIV2_USBHSDIV_SHIFT 9

#define	SIM_CLKDIV2_USBHSDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBHSDIV_SHIFT))&SIM_CLKDIV2_USBHSDIV_MASK)

#define	SIM_FCFG1_FTFDIS_MASK 0x1u

#define	SIM_FCFG1_FTFDIS_SHIFT 0

#define	SIM_FCFG1_DEPART_MASK 0xF00u

#define	SIM_FCFG1_DEPART_SHIFT 8

#define	SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)

#define	SIM_FCFG1_EESIZE_MASK 0xF0000u

#define	SIM_FCFG1_EESIZE_SHIFT 16

#define	SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)

#define	SIM_FCFG1_PFSIZE_MASK 0xF000000u

#define	SIM_FCFG1_PFSIZE_SHIFT 24

#define	SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)

#define	SIM_FCFG1_NVMSIZE_MASK 0xF0000000u

#define	SIM_FCFG1_NVMSIZE_SHIFT 28

#define	SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)

#define	SIM_FCFG2_MAXADDR23_MASK 0x3F0000u

#define	SIM_FCFG2_MAXADDR23_SHIFT 16

#define	SIM_FCFG2_MAXADDR23(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR23_SHIFT))&SIM_FCFG2_MAXADDR23_MASK)

#define	SIM_FCFG2_MAXADDR01_MASK 0x3F000000u

#define	SIM_FCFG2_MAXADDR01_SHIFT 24

#define	SIM_FCFG2_MAXADDR01(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR01_SHIFT))&SIM_FCFG2_MAXADDR01_MASK)

#define	SIM_UIDH_UID_MASK 0xFFFFFFFFu

#define	SIM_UIDH_UID_SHIFT 0

#define	SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)

#define	SIM_UIDMH_UID_MASK 0xFFFFFFFFu

#define	SIM_UIDMH_UID_SHIFT 0

#define	SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)

#define	SIM_UIDML_UID_MASK 0xFFFFFFFFu

#define	SIM_UIDML_UID_SHIFT 0

#define	SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)

#define	SIM_UIDL_UID_MASK 0xFFFFFFFFu

#define	SIM_UIDL_UID_SHIFT 0

#define	SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)

#define	SIM_CLKDIV3_LCDCFRAC_MASK 0xFF00u

#define	SIM_CLKDIV3_LCDCFRAC_SHIFT 8

#define	SIM_CLKDIV3_LCDCFRAC(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV3_LCDCFRAC_SHIFT))&SIM_CLKDIV3_LCDCFRAC_MASK)

#define	SIM_CLKDIV3_LCDCDIV_MASK 0xFFF0000u

#define	SIM_CLKDIV3_LCDCDIV_SHIFT 16

#define	SIM_CLKDIV3_LCDCDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV3_LCDCDIV_SHIFT))&SIM_CLKDIV3_LCDCDIV_MASK)

#define	SIM_CLKDIV4_TRACEFRAC_MASK 0x1u

#define	SIM_CLKDIV4_TRACEFRAC_SHIFT 0

#define	SIM_CLKDIV4_TRACEDIV_MASK 0xEu

#define	SIM_CLKDIV4_TRACEDIV_SHIFT 1

#define	SIM_CLKDIV4_TRACEDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV4_TRACEDIV_SHIFT))&SIM_CLKDIV4_TRACEDIV_MASK)

#define	SIM_CLKDIV4_NFCFRAC_MASK 0x7000000u

#define	SIM_CLKDIV4_NFCFRAC_SHIFT 24

#define	SIM_CLKDIV4_NFCFRAC(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV4_NFCFRAC_SHIFT))&SIM_CLKDIV4_NFCFRAC_MASK)

#define	SIM_CLKDIV4_NFCDIV_MASK 0xF8000000u

#define	SIM_CLKDIV4_NFCDIV_SHIFT 27

#define	SIM_CLKDIV4_NFCDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV4_NFCDIV_SHIFT))&SIM_CLKDIV4_NFCDIV_MASK)

#define	SIM_MCR_DDRSREN_MASK 0x1u

#define	SIM_MCR_DDRSREN_SHIFT 0

#define	SIM_MCR_DDRS_MASK 0x2u

#define	SIM_MCR_DDRS_SHIFT 1

#define	SIM_MCR_DDRPEN_MASK 0x4u

#define	SIM_MCR_DDRPEN_SHIFT 2

#define	SIM_MCR_DDRDQSDIS_MASK 0x8u

#define	SIM_MCR_DDRDQSDIS_SHIFT 3

#define	SIM_MCR_DDRCFG_MASK 0xE0u

#define	SIM_MCR_DDRCFG_SHIFT 5

#define	SIM_MCR_DDRCFG(x) (((uint32_t)(((uint32_t)(x))<<SIM_MCR_DDRCFG_SHIFT))&SIM_MCR_DDRCFG_MASK)

#define	SIM_MCR_RCRRSTEN_MASK 0x100u

#define	SIM_MCR_RCRRSTEN_SHIFT 8

#define	SIM_MCR_RCRRST_MASK 0x200u

#define	SIM_MCR_RCRRST_SHIFT 9

#define	SIM_MCR_LCDSTART_MASK 0x10000u

#define	SIM_MCR_LCDSTART_SHIFT 16

#define	SIM_MCR_PDBLOOP_MASK 0x20000000u

#define	SIM_MCR_PDBLOOP_SHIFT 29

#define	SIM_MCR_ULPICLKOBE_MASK 0x40000000u

#define	SIM_MCR_ULPICLKOBE_SHIFT 30

#define	SIM_MCR_TRACECLKDIS_MASK 0x80000000u

#define	SIM_MCR_TRACECLKDIS_SHIFT 31

#define	SIM_BASE_PTR ((SIM_MemMapPtr)0x40047000u)

#define	SIM_BASE_PTRS { SIM_BASE_PTR }

#define	SIM_SOPT1 SIM_SOPT1_REG(SIM_BASE_PTR)

#define	SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM_BASE_PTR)

#define	SIM_SOPT2 SIM_SOPT2_REG(SIM_BASE_PTR)

#define	SIM_SOPT4 SIM_SOPT4_REG(SIM_BASE_PTR)

#define	SIM_SOPT5 SIM_SOPT5_REG(SIM_BASE_PTR)

#define	SIM_SOPT6 SIM_SOPT6_REG(SIM_BASE_PTR)

#define	SIM_SOPT7 SIM_SOPT7_REG(SIM_BASE_PTR)

#define	SIM_SDID SIM_SDID_REG(SIM_BASE_PTR)

#define	SIM_SCGC1 SIM_SCGC1_REG(SIM_BASE_PTR)

#define	SIM_SCGC2 SIM_SCGC2_REG(SIM_BASE_PTR)

#define	SIM_SCGC3 SIM_SCGC3_REG(SIM_BASE_PTR)

#define	SIM_SCGC4 SIM_SCGC4_REG(SIM_BASE_PTR)

#define	SIM_SCGC5 SIM_SCGC5_REG(SIM_BASE_PTR)

#define	SIM_SCGC6 SIM_SCGC6_REG(SIM_BASE_PTR)

#define	SIM_SCGC7 SIM_SCGC7_REG(SIM_BASE_PTR)

#define	SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM_BASE_PTR)

#define	SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM_BASE_PTR)

#define	SIM_FCFG1 SIM_FCFG1_REG(SIM_BASE_PTR)

#define	SIM_FCFG2 SIM_FCFG2_REG(SIM_BASE_PTR)

#define	SIM_UIDH SIM_UIDH_REG(SIM_BASE_PTR)

#define	SIM_UIDMH SIM_UIDMH_REG(SIM_BASE_PTR)

#define	SIM_UIDML SIM_UIDML_REG(SIM_BASE_PTR)

#define	SIM_UIDL SIM_UIDL_REG(SIM_BASE_PTR)

#define	SIM_CLKDIV3 SIM_CLKDIV3_REG(SIM_BASE_PTR)

#define	SIM_CLKDIV4 SIM_CLKDIV4_REG(SIM_BASE_PTR)

#define	SIM_MCR SIM_MCR_REG(SIM_BASE_PTR)

#define	SMC_PMPROT_REG(base) ((base)->PMPROT)

#define	SMC_PMCTRL_REG(base) ((base)->PMCTRL)

#define	SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL)

#define	SMC_PMSTAT_REG(base) ((base)->PMSTAT)

#define	SMC_PMPROT_AVLLS_MASK 0x2u

#define	SMC_PMPROT_AVLLS_SHIFT 1

#define	SMC_PMPROT_ALLS_MASK 0x8u

#define	SMC_PMPROT_ALLS_SHIFT 3

#define	SMC_PMPROT_AVLP_MASK 0x20u

#define	SMC_PMPROT_AVLP_SHIFT 5

#define	SMC_PMCTRL_STOPM_MASK 0x7u

#define	SMC_PMCTRL_STOPM_SHIFT 0

#define	SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)

#define	SMC_PMCTRL_STOPA_MASK 0x8u

#define	SMC_PMCTRL_STOPA_SHIFT 3

#define	SMC_PMCTRL_RUNM_MASK 0x60u

#define	SMC_PMCTRL_RUNM_SHIFT 5

#define	SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)

#define	SMC_PMCTRL_LPWUI_MASK 0x80u

#define	SMC_PMCTRL_LPWUI_SHIFT 7

#define	SMC_VLLSCTRL_VLLSM_MASK 0x7u

#define	SMC_VLLSCTRL_VLLSM_SHIFT 0

#define	SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)

#define	SMC_PMSTAT_PMSTAT_MASK 0x7Fu

#define	SMC_PMSTAT_PMSTAT_SHIFT 0

#define	SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)

#define	SMC_BASE_PTR ((SMC_MemMapPtr)0x4007E000u)

#define	SMC_BASE_PTRS { SMC_BASE_PTR }

#define	SMC_PMPROT SMC_PMPROT_REG(SMC_BASE_PTR)

#define	SMC_PMCTRL SMC_PMCTRL_REG(SMC_BASE_PTR)

#define	SMC_VLLSCTRL SMC_VLLSCTRL_REG(SMC_BASE_PTR)

#define	SMC_PMSTAT SMC_PMSTAT_REG(SMC_BASE_PTR)

#define	SPI_MCR_REG(base) ((base)->MCR)

#define	SPI_TCR_REG(base) ((base)->TCR)

#define	SPI_CTAR_REG(base, index2) ((base)->CTAR[index2])

#define	SPI_CTAR_SLAVE_REG(base, index2) ((base)->CTAR_SLAVE[index2])

#define	SPI_SR_REG(base) ((base)->SR)

#define	SPI_RSER_REG(base) ((base)->RSER)

#define	SPI_PUSHR_REG(base) ((base)->PUSHR)

#define	SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)

#define	SPI_POPR_REG(base) ((base)->POPR)

#define	SPI_TXFR0_REG(base) ((base)->TXFR0)

#define	SPI_TXFR1_REG(base) ((base)->TXFR1)

#define	SPI_TXFR2_REG(base) ((base)->TXFR2)

#define	SPI_TXFR3_REG(base) ((base)->TXFR3)

#define	SPI_RXFR0_REG(base) ((base)->RXFR0)

#define	SPI_RXFR1_REG(base) ((base)->RXFR1)

#define	SPI_RXFR2_REG(base) ((base)->RXFR2)

#define	SPI_RXFR3_REG(base) ((base)->RXFR3)

#define	SPI_MCR_HALT_MASK 0x1u

#define	SPI_MCR_HALT_SHIFT 0

#define	SPI_MCR_SMPL_PT_MASK 0x300u

#define	SPI_MCR_SMPL_PT_SHIFT 8

#define	SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)

#define	SPI_MCR_CLR_RXF_MASK 0x400u

#define	SPI_MCR_CLR_RXF_SHIFT 10

#define	SPI_MCR_CLR_TXF_MASK 0x800u

#define	SPI_MCR_CLR_TXF_SHIFT 11

#define	SPI_MCR_DIS_RXF_MASK 0x1000u

#define	SPI_MCR_DIS_RXF_SHIFT 12

#define	SPI_MCR_DIS_TXF_MASK 0x2000u

#define	SPI_MCR_DIS_TXF_SHIFT 13

#define	SPI_MCR_MDIS_MASK 0x4000u

#define	SPI_MCR_MDIS_SHIFT 14

#define	SPI_MCR_DOZE_MASK 0x8000u

#define	SPI_MCR_DOZE_SHIFT 15

#define	SPI_MCR_PCSIS_MASK 0x3F0000u

#define	SPI_MCR_PCSIS_SHIFT 16

#define	SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)

#define	SPI_MCR_ROOE_MASK 0x1000000u

#define	SPI_MCR_ROOE_SHIFT 24

#define	SPI_MCR_PCSSE_MASK 0x2000000u

#define	SPI_MCR_PCSSE_SHIFT 25

#define	SPI_MCR_MTFE_MASK 0x4000000u

#define	SPI_MCR_MTFE_SHIFT 26

#define	SPI_MCR_FRZ_MASK 0x8000000u

#define	SPI_MCR_FRZ_SHIFT 27

#define	SPI_MCR_DCONF_MASK 0x30000000u

#define	SPI_MCR_DCONF_SHIFT 28

#define	SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)

#define	SPI_MCR_CONT_SCKE_MASK 0x40000000u

#define	SPI_MCR_CONT_SCKE_SHIFT 30

#define	SPI_MCR_MSTR_MASK 0x80000000u

#define	SPI_MCR_MSTR_SHIFT 31

#define	SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u

#define	SPI_TCR_SPI_TCNT_SHIFT 16

#define	SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)

#define	SPI_CTAR_BR_MASK 0xFu

#define	SPI_CTAR_BR_SHIFT 0

#define	SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)

#define	SPI_CTAR_DT_MASK 0xF0u

#define	SPI_CTAR_DT_SHIFT 4

#define	SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)

#define	SPI_CTAR_ASC_MASK 0xF00u

#define	SPI_CTAR_ASC_SHIFT 8

#define	SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)

#define	SPI_CTAR_CSSCK_MASK 0xF000u

#define	SPI_CTAR_CSSCK_SHIFT 12

#define	SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)

#define	SPI_CTAR_PBR_MASK 0x30000u

#define	SPI_CTAR_PBR_SHIFT 16

#define	SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)

#define	SPI_CTAR_PDT_MASK 0xC0000u

#define	SPI_CTAR_PDT_SHIFT 18

#define	SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)

#define	SPI_CTAR_PASC_MASK 0x300000u

#define	SPI_CTAR_PASC_SHIFT 20

#define	SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)

#define	SPI_CTAR_PCSSCK_MASK 0xC00000u

#define	SPI_CTAR_PCSSCK_SHIFT 22

#define	SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)

#define	SPI_CTAR_LSBFE_MASK 0x1000000u

#define	SPI_CTAR_LSBFE_SHIFT 24

#define	SPI_CTAR_CPHA_MASK 0x2000000u

#define	SPI_CTAR_CPHA_SHIFT 25

#define	SPI_CTAR_CPOL_MASK 0x4000000u

#define	SPI_CTAR_CPOL_SHIFT 26

#define	SPI_CTAR_FMSZ_MASK 0x78000000u

#define	SPI_CTAR_FMSZ_SHIFT 27

#define	SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)

#define	SPI_CTAR_DBR_MASK 0x80000000u

#define	SPI_CTAR_DBR_SHIFT 31

#define	SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u

#define	SPI_CTAR_SLAVE_CPHA_SHIFT 25

#define	SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u

#define	SPI_CTAR_SLAVE_CPOL_SHIFT 26

#define	SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u

#define	SPI_CTAR_SLAVE_FMSZ_SHIFT 27

#define	SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)

#define	SPI_SR_POPNXTPTR_MASK 0xFu

#define	SPI_SR_POPNXTPTR_SHIFT 0

#define	SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)

#define	SPI_SR_RXCTR_MASK 0xF0u

#define	SPI_SR_RXCTR_SHIFT 4

#define	SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)

#define	SPI_SR_TXNXTPTR_MASK 0xF00u

#define	SPI_SR_TXNXTPTR_SHIFT 8

#define	SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)

#define	SPI_SR_TXCTR_MASK 0xF000u

#define	SPI_SR_TXCTR_SHIFT 12

#define	SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)

#define	SPI_SR_RFDF_MASK 0x20000u

#define	SPI_SR_RFDF_SHIFT 17

#define	SPI_SR_RFOF_MASK 0x80000u

#define	SPI_SR_RFOF_SHIFT 19

#define	SPI_SR_TFFF_MASK 0x2000000u

#define	SPI_SR_TFFF_SHIFT 25

#define	SPI_SR_TFUF_MASK 0x8000000u

#define	SPI_SR_TFUF_SHIFT 27

#define	SPI_SR_EOQF_MASK 0x10000000u

#define	SPI_SR_EOQF_SHIFT 28

#define	SPI_SR_TXRXS_MASK 0x40000000u

#define	SPI_SR_TXRXS_SHIFT 30

#define	SPI_SR_TCF_MASK 0x80000000u

#define	SPI_SR_TCF_SHIFT 31

#define	SPI_RSER_RFDF_DIRS_MASK 0x10000u

#define	SPI_RSER_RFDF_DIRS_SHIFT 16

#define	SPI_RSER_RFDF_RE_MASK 0x20000u

#define	SPI_RSER_RFDF_RE_SHIFT 17

#define	SPI_RSER_RFOF_RE_MASK 0x80000u

#define	SPI_RSER_RFOF_RE_SHIFT 19

#define	SPI_RSER_TFFF_DIRS_MASK 0x1000000u

#define	SPI_RSER_TFFF_DIRS_SHIFT 24

#define	SPI_RSER_TFFF_RE_MASK 0x2000000u

#define	SPI_RSER_TFFF_RE_SHIFT 25

#define	SPI_RSER_TFUF_RE_MASK 0x8000000u

#define	SPI_RSER_TFUF_RE_SHIFT 27

#define	SPI_RSER_EOQF_RE_MASK 0x10000000u

#define	SPI_RSER_EOQF_RE_SHIFT 28

#define	SPI_RSER_TCF_RE_MASK 0x80000000u

#define	SPI_RSER_TCF_RE_SHIFT 31

#define	SPI_PUSHR_TXDATA_MASK 0xFFFFu

#define	SPI_PUSHR_TXDATA_SHIFT 0

#define	SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)

#define	SPI_PUSHR_PCS_MASK 0x3F0000u

#define	SPI_PUSHR_PCS_SHIFT 16

#define	SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)

#define	SPI_PUSHR_CTCNT_MASK 0x4000000u

#define	SPI_PUSHR_CTCNT_SHIFT 26

#define	SPI_PUSHR_EOQ_MASK 0x8000000u

#define	SPI_PUSHR_EOQ_SHIFT 27

#define	SPI_PUSHR_CTAS_MASK 0x70000000u

#define	SPI_PUSHR_CTAS_SHIFT 28

#define	SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)

#define	SPI_PUSHR_CONT_MASK 0x80000000u

#define	SPI_PUSHR_CONT_SHIFT 31

#define	SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFu

#define	SPI_PUSHR_SLAVE_TXDATA_SHIFT 0

#define	SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)

#define	SPI_POPR_RXDATA_MASK 0xFFFFFFFFu

#define	SPI_POPR_RXDATA_SHIFT 0

#define	SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)

#define	SPI_TXFR0_TXDATA_MASK 0xFFFFu

#define	SPI_TXFR0_TXDATA_SHIFT 0

#define	SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)

#define	SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u

#define	SPI_TXFR0_TXCMD_TXDATA_SHIFT 16

#define	SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)

#define	SPI_TXFR1_TXDATA_MASK 0xFFFFu

#define	SPI_TXFR1_TXDATA_SHIFT 0

#define	SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)

#define	SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u

#define	SPI_TXFR1_TXCMD_TXDATA_SHIFT 16

#define	SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)

#define	SPI_TXFR2_TXDATA_MASK 0xFFFFu

#define	SPI_TXFR2_TXDATA_SHIFT 0

#define	SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)

#define	SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u

#define	SPI_TXFR2_TXCMD_TXDATA_SHIFT 16

#define	SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)

#define	SPI_TXFR3_TXDATA_MASK 0xFFFFu

#define	SPI_TXFR3_TXDATA_SHIFT 0

#define	SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)

#define	SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u

#define	SPI_TXFR3_TXCMD_TXDATA_SHIFT 16

#define	SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)

#define	SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu

#define	SPI_RXFR0_RXDATA_SHIFT 0

#define	SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)

#define	SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu

#define	SPI_RXFR1_RXDATA_SHIFT 0

#define	SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)

#define	SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu

#define	SPI_RXFR2_RXDATA_SHIFT 0

#define	SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)

#define	SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu

#define	SPI_RXFR3_RXDATA_SHIFT 0

#define	SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)

#define	SPI0_BASE_PTR ((SPI_MemMapPtr)0x4002C000u)

#define	SPI1_BASE_PTR ((SPI_MemMapPtr)0x4002D000u)

#define	SPI2_BASE_PTR ((SPI_MemMapPtr)0x400AC000u)

#define	SPI_BASE_PTRS { SPI0_BASE_PTR, SPI1_BASE_PTR, SPI2_BASE_PTR }

#define	SPI0_MCR SPI_MCR_REG(SPI0_BASE_PTR)

#define	SPI0_TCR SPI_TCR_REG(SPI0_BASE_PTR)

#define	SPI0_CTAR0 SPI_CTAR_REG(SPI0_BASE_PTR,0)

#define	SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0_BASE_PTR,0)

#define	SPI0_CTAR1 SPI_CTAR_REG(SPI0_BASE_PTR,1)

#define	SPI0_SR SPI_SR_REG(SPI0_BASE_PTR)

#define	SPI0_RSER SPI_RSER_REG(SPI0_BASE_PTR)

#define	SPI0_PUSHR SPI_PUSHR_REG(SPI0_BASE_PTR)

#define	SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0_BASE_PTR)

#define	SPI0_POPR SPI_POPR_REG(SPI0_BASE_PTR)

#define	SPI0_TXFR0 SPI_TXFR0_REG(SPI0_BASE_PTR)

#define	SPI0_TXFR1 SPI_TXFR1_REG(SPI0_BASE_PTR)

#define	SPI0_TXFR2 SPI_TXFR2_REG(SPI0_BASE_PTR)

#define	SPI0_TXFR3 SPI_TXFR3_REG(SPI0_BASE_PTR)

#define	SPI0_RXFR0 SPI_RXFR0_REG(SPI0_BASE_PTR)

#define	SPI0_RXFR1 SPI_RXFR1_REG(SPI0_BASE_PTR)

#define	SPI0_RXFR2 SPI_RXFR2_REG(SPI0_BASE_PTR)

#define	SPI0_RXFR3 SPI_RXFR3_REG(SPI0_BASE_PTR)

#define	SPI1_MCR SPI_MCR_REG(SPI1_BASE_PTR)

#define	SPI1_TCR SPI_TCR_REG(SPI1_BASE_PTR)

#define	SPI1_CTAR0 SPI_CTAR_REG(SPI1_BASE_PTR,0)

#define	SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1_BASE_PTR,0)

#define	SPI1_CTAR1 SPI_CTAR_REG(SPI1_BASE_PTR,1)

#define	SPI1_SR SPI_SR_REG(SPI1_BASE_PTR)

#define	SPI1_RSER SPI_RSER_REG(SPI1_BASE_PTR)

#define	SPI1_PUSHR SPI_PUSHR_REG(SPI1_BASE_PTR)

#define	SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1_BASE_PTR)

#define	SPI1_POPR SPI_POPR_REG(SPI1_BASE_PTR)

#define	SPI1_TXFR0 SPI_TXFR0_REG(SPI1_BASE_PTR)

#define	SPI1_TXFR1 SPI_TXFR1_REG(SPI1_BASE_PTR)

#define	SPI1_TXFR2 SPI_TXFR2_REG(SPI1_BASE_PTR)

#define	SPI1_TXFR3 SPI_TXFR3_REG(SPI1_BASE_PTR)

#define	SPI1_RXFR0 SPI_RXFR0_REG(SPI1_BASE_PTR)

#define	SPI1_RXFR1 SPI_RXFR1_REG(SPI1_BASE_PTR)

#define	SPI1_RXFR2 SPI_RXFR2_REG(SPI1_BASE_PTR)

#define	SPI1_RXFR3 SPI_RXFR3_REG(SPI1_BASE_PTR)

#define	SPI2_MCR SPI_MCR_REG(SPI2_BASE_PTR)

#define	SPI2_TCR SPI_TCR_REG(SPI2_BASE_PTR)

#define	SPI2_CTAR0 SPI_CTAR_REG(SPI2_BASE_PTR,0)

#define	SPI2_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI2_BASE_PTR,0)

#define	SPI2_CTAR1 SPI_CTAR_REG(SPI2_BASE_PTR,1)

#define	SPI2_SR SPI_SR_REG(SPI2_BASE_PTR)

#define	SPI2_RSER SPI_RSER_REG(SPI2_BASE_PTR)

#define	SPI2_PUSHR SPI_PUSHR_REG(SPI2_BASE_PTR)

#define	SPI2_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI2_BASE_PTR)

#define	SPI2_POPR SPI_POPR_REG(SPI2_BASE_PTR)

#define	SPI2_TXFR0 SPI_TXFR0_REG(SPI2_BASE_PTR)

#define	SPI2_TXFR1 SPI_TXFR1_REG(SPI2_BASE_PTR)

#define	SPI2_TXFR2 SPI_TXFR2_REG(SPI2_BASE_PTR)

#define	SPI2_TXFR3 SPI_TXFR3_REG(SPI2_BASE_PTR)

#define	SPI2_RXFR0 SPI_RXFR0_REG(SPI2_BASE_PTR)

#define	SPI2_RXFR1 SPI_RXFR1_REG(SPI2_BASE_PTR)

#define	SPI2_RXFR2 SPI_RXFR2_REG(SPI2_BASE_PTR)

#define	SPI2_RXFR3 SPI_RXFR3_REG(SPI2_BASE_PTR)

#define	SPI0_CTAR(index2) SPI_CTAR_REG(SPI0_BASE_PTR,index2)

#define	SPI1_CTAR(index2) SPI_CTAR_REG(SPI1_BASE_PTR,index2)

#define	SPI2_CTAR(index2) SPI_CTAR_REG(SPI2_BASE_PTR,index2)

#define	SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0_BASE_PTR,index2)

#define	SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1_BASE_PTR,index2)

#define	SPI2_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI2_BASE_PTR,index2)

#define	SysTick_CSR_REG(base) ((base)->CSR)

#define	SysTick_RVR_REG(base) ((base)->RVR)

#define	SysTick_CVR_REG(base) ((base)->CVR)

#define	SysTick_CALIB_REG(base) ((base)->CALIB)

#define	SysTick_CSR_ENABLE_MASK 0x1u

#define	SysTick_CSR_ENABLE_SHIFT 0

#define	SysTick_CSR_TICKINT_MASK 0x2u

#define	SysTick_CSR_TICKINT_SHIFT 1

#define	SysTick_CSR_CLKSOURCE_MASK 0x4u

#define	SysTick_CSR_CLKSOURCE_SHIFT 2

#define	SysTick_CSR_COUNTFLAG_MASK 0x10000u

#define	SysTick_CSR_COUNTFLAG_SHIFT 16

#define	SysTick_RVR_RELOAD_MASK 0xFFFFFFu

#define	SysTick_RVR_RELOAD_SHIFT 0

#define	SysTick_RVR_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<SysTick_RVR_RELOAD_SHIFT))&SysTick_RVR_RELOAD_MASK)

#define	SysTick_CVR_CURRENT_MASK 0xFFFFFFu

#define	SysTick_CVR_CURRENT_SHIFT 0

#define	SysTick_CVR_CURRENT(x) (((uint32_t)(((uint32_t)(x))<<SysTick_CVR_CURRENT_SHIFT))&SysTick_CVR_CURRENT_MASK)

#define	SysTick_CALIB_TENMS_MASK 0xFFFFFFu

#define	SysTick_CALIB_TENMS_SHIFT 0

#define	SysTick_CALIB_TENMS(x) (((uint32_t)(((uint32_t)(x))<<SysTick_CALIB_TENMS_SHIFT))&SysTick_CALIB_TENMS_MASK)

#define	SysTick_CALIB_SKEW_MASK 0x40000000u

#define	SysTick_CALIB_SKEW_SHIFT 30

#define	SysTick_CALIB_NOREF_MASK 0x80000000u

#define	SysTick_CALIB_NOREF_SHIFT 31

#define	SysTick_BASE_PTR ((SysTick_MemMapPtr)0xE000E010u)

#define	SysTick_BASE_PTRS { SysTick_BASE_PTR }

#define	SYST_CSR SysTick_CSR_REG(SysTick_BASE_PTR)

#define	SYST_RVR SysTick_RVR_REG(SysTick_BASE_PTR)

#define	SYST_CVR SysTick_CVR_REG(SysTick_BASE_PTR)

#define	SYST_CALIB SysTick_CALIB_REG(SysTick_BASE_PTR)

#define	TPIU_SSPSR_REG(base) ((base)->SSPSR)

#define	TPIU_CSPSR_REG(base) ((base)->CSPSR)

#define	TPIU_ACPR_REG(base) ((base)->ACPR)

#define	TPIU_SPPR_REG(base) ((base)->SPPR)

#define	TPIU_FFSR_REG(base) ((base)->FFSR)

#define	TPIU_FFCR_REG(base) ((base)->FFCR)

#define	TPIU_FSCR_REG(base) ((base)->FSCR)

#define	TPIU_TRIGGER_REG(base) ((base)->TRIGGER)

#define	TPIU_FIFODATA0_REG(base) ((base)->FIFODATA0)

#define	TPIU_ITATBCTR2_REG(base) ((base)->ITATBCTR2)

#define	TPIU_ITATBCTR0_REG(base) ((base)->ITATBCTR0)

#define	TPIU_FIFODATA1_REG(base) ((base)->FIFODATA1)

#define	TPIU_ITCTRL_REG(base) ((base)->ITCTRL)

#define	TPIU_CLAIMSET_REG(base) ((base)->CLAIMSET)

#define	TPIU_CLAIMCLR_REG(base) ((base)->CLAIMCLR)

#define	TPIU_DEVID_REG(base) ((base)->DEVID)

#define	TPIU_PID4_REG(base) ((base)->PID4)

#define	TPIU_PID5_REG(base) ((base)->PID5)

#define	TPIU_PID6_REG(base) ((base)->PID6)

#define	TPIU_PID7_REG(base) ((base)->PID7)

#define	TPIU_PID0_REG(base) ((base)->PID0)

#define	TPIU_PID1_REG(base) ((base)->PID1)

#define	TPIU_PID2_REG(base) ((base)->PID2)

#define	TPIU_PID3_REG(base) ((base)->PID3)

#define	TPIU_CID0_REG(base) ((base)->CID0)

#define	TPIU_CID1_REG(base) ((base)->CID1)

#define	TPIU_CID2_REG(base) ((base)->CID2)

#define	TPIU_CID4_REG(base) ((base)->CID4)

#define	TPIU_BASE_PTR ((TPIU_MemMapPtr)0xE0040000u)

#define	TPIU_BASE_PTRS { TPIU_BASE_PTR }

#define	TPIU_SSPSR TPIU_SSPSR_REG(TPIU_BASE_PTR)

#define	TPIU_CSPSR TPIU_CSPSR_REG(TPIU_BASE_PTR)

#define	TPIU_ACPR TPIU_ACPR_REG(TPIU_BASE_PTR)

#define	TPIU_SPPR TPIU_SPPR_REG(TPIU_BASE_PTR)

#define	TPIU_FFSR TPIU_FFSR_REG(TPIU_BASE_PTR)

#define	TPIU_FFCR TPIU_FFCR_REG(TPIU_BASE_PTR)

#define	TPIU_FSCR TPIU_FSCR_REG(TPIU_BASE_PTR)

#define	TPIU_TRIGGER TPIU_TRIGGER_REG(TPIU_BASE_PTR)

#define	TPIU_FIFODATA0 TPIU_FIFODATA0_REG(TPIU_BASE_PTR)

#define	TPIU_ITATBCTR2 TPIU_ITATBCTR2_REG(TPIU_BASE_PTR)

#define	TPIU_ITATBCTR0 TPIU_ITATBCTR0_REG(TPIU_BASE_PTR)

#define	TPIU_FIFODATA1 TPIU_FIFODATA1_REG(TPIU_BASE_PTR)

#define	TPIU_ITCTRL TPIU_ITCTRL_REG(TPIU_BASE_PTR)

#define	TPIU_CLAIMSET TPIU_CLAIMSET_REG(TPIU_BASE_PTR)

#define	TPIU_CLAIMCLR TPIU_CLAIMCLR_REG(TPIU_BASE_PTR)

#define	TPIU_DEVID TPIU_DEVID_REG(TPIU_BASE_PTR)

#define	TPIU_PID4 TPIU_PID4_REG(TPIU_BASE_PTR)

#define	TPIU_PID5 TPIU_PID5_REG(TPIU_BASE_PTR)

#define	TPIU_PID6 TPIU_PID6_REG(TPIU_BASE_PTR)

#define	TPIU_PID7 TPIU_PID7_REG(TPIU_BASE_PTR)

#define	TPIU_PID0 TPIU_PID0_REG(TPIU_BASE_PTR)

#define	TPIU_PID1 TPIU_PID1_REG(TPIU_BASE_PTR)

#define	TPIU_PID2 TPIU_PID2_REG(TPIU_BASE_PTR)

#define	TPIU_PID3 TPIU_PID3_REG(TPIU_BASE_PTR)

#define	TPIU_CID0 TPIU_CID0_REG(TPIU_BASE_PTR)

#define	TPIU_CID1 TPIU_CID1_REG(TPIU_BASE_PTR)

#define	TPIU_CID2 TPIU_CID2_REG(TPIU_BASE_PTR)

#define	TPIU_CID3 TPIU_CID4_REG(TPIU_BASE_PTR)

#define	TSI_GENCS_REG(base) ((base)->GENCS)

#define	TSI_SCANC_REG(base) ((base)->SCANC)

#define	TSI_PEN_REG(base) ((base)->PEN)

#define	TSI_WUCNTR_REG(base) ((base)->WUCNTR)

#define	TSI_CNTR1_REG(base) ((base)->CNTR1)

#define	TSI_CNTR3_REG(base) ((base)->CNTR3)

#define	TSI_CNTR5_REG(base) ((base)->CNTR5)

#define	TSI_CNTR7_REG(base) ((base)->CNTR7)

#define	TSI_CNTR9_REG(base) ((base)->CNTR9)

#define	TSI_CNTR11_REG(base) ((base)->CNTR11)

#define	TSI_CNTR13_REG(base) ((base)->CNTR13)

#define	TSI_CNTR15_REG(base) ((base)->CNTR15)

#define	TSI_THRESHOLD_REG(base) ((base)->THRESHOLD)

#define	TSI_GENCS_STPE_MASK 0x1u

#define	TSI_GENCS_STPE_SHIFT 0

#define	TSI_GENCS_STM_MASK 0x2u

#define	TSI_GENCS_STM_SHIFT 1

#define	TSI_GENCS_ESOR_MASK 0x10u

#define	TSI_GENCS_ESOR_SHIFT 4

#define	TSI_GENCS_ERIE_MASK 0x20u

#define	TSI_GENCS_ERIE_SHIFT 5

#define	TSI_GENCS_TSIIE_MASK 0x40u

#define	TSI_GENCS_TSIIE_SHIFT 6

#define	TSI_GENCS_TSIEN_MASK 0x80u

#define	TSI_GENCS_TSIEN_SHIFT 7

#define	TSI_GENCS_SWTS_MASK 0x100u

#define	TSI_GENCS_SWTS_SHIFT 8

#define	TSI_GENCS_SCNIP_MASK 0x200u

#define	TSI_GENCS_SCNIP_SHIFT 9

#define	TSI_GENCS_OVRF_MASK 0x1000u

#define	TSI_GENCS_OVRF_SHIFT 12

#define	TSI_GENCS_EXTERF_MASK 0x2000u

#define	TSI_GENCS_EXTERF_SHIFT 13

#define	TSI_GENCS_OUTRGF_MASK 0x4000u

#define	TSI_GENCS_OUTRGF_SHIFT 14

#define	TSI_GENCS_EOSF_MASK 0x8000u

#define	TSI_GENCS_EOSF_SHIFT 15

#define	TSI_GENCS_PS_MASK 0x70000u

#define	TSI_GENCS_PS_SHIFT 16

#define	TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)

#define	TSI_GENCS_NSCN_MASK 0xF80000u

#define	TSI_GENCS_NSCN_SHIFT 19

#define	TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)

#define	TSI_GENCS_LPSCNITV_MASK 0xF000000u

#define	TSI_GENCS_LPSCNITV_SHIFT 24

#define	TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)

#define	TSI_GENCS_LPCLKS_MASK 0x10000000u

#define	TSI_GENCS_LPCLKS_SHIFT 28

#define	TSI_SCANC_AMPSC_MASK 0x7u

#define	TSI_SCANC_AMPSC_SHIFT 0

#define	TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)

#define	TSI_SCANC_AMCLKS_MASK 0x18u

#define	TSI_SCANC_AMCLKS_SHIFT 3

#define	TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)

#define	TSI_SCANC_SMOD_MASK 0xFF00u

#define	TSI_SCANC_SMOD_SHIFT 8

#define	TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)

#define	TSI_SCANC_EXTCHRG_MASK 0xF0000u

#define	TSI_SCANC_EXTCHRG_SHIFT 16

#define	TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)

#define	TSI_SCANC_REFCHRG_MASK 0xF000000u

#define	TSI_SCANC_REFCHRG_SHIFT 24

#define	TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)

#define	TSI_PEN_PEN0_MASK 0x1u

#define	TSI_PEN_PEN0_SHIFT 0

#define	TSI_PEN_PEN1_MASK 0x2u

#define	TSI_PEN_PEN1_SHIFT 1

#define	TSI_PEN_PEN2_MASK 0x4u

#define	TSI_PEN_PEN2_SHIFT 2

#define	TSI_PEN_PEN3_MASK 0x8u

#define	TSI_PEN_PEN3_SHIFT 3

#define	TSI_PEN_PEN4_MASK 0x10u

#define	TSI_PEN_PEN4_SHIFT 4

#define	TSI_PEN_PEN5_MASK 0x20u

#define	TSI_PEN_PEN5_SHIFT 5

#define	TSI_PEN_PEN6_MASK 0x40u

#define	TSI_PEN_PEN6_SHIFT 6

#define	TSI_PEN_PEN7_MASK 0x80u

#define	TSI_PEN_PEN7_SHIFT 7

#define	TSI_PEN_PEN8_MASK 0x100u

#define	TSI_PEN_PEN8_SHIFT 8

#define	TSI_PEN_PEN9_MASK 0x200u

#define	TSI_PEN_PEN9_SHIFT 9

#define	TSI_PEN_PEN10_MASK 0x400u

#define	TSI_PEN_PEN10_SHIFT 10

#define	TSI_PEN_PEN11_MASK 0x800u

#define	TSI_PEN_PEN11_SHIFT 11

#define	TSI_PEN_PEN12_MASK 0x1000u

#define	TSI_PEN_PEN12_SHIFT 12

#define	TSI_PEN_PEN13_MASK 0x2000u

#define	TSI_PEN_PEN13_SHIFT 13

#define	TSI_PEN_PEN14_MASK 0x4000u

#define	TSI_PEN_PEN14_SHIFT 14

#define	TSI_PEN_PEN15_MASK 0x8000u

#define	TSI_PEN_PEN15_SHIFT 15

#define	TSI_PEN_LPSP_MASK 0xF0000u

#define	TSI_PEN_LPSP_SHIFT 16

#define	TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)

#define	TSI_WUCNTR_WUCNT_MASK 0xFFFFu

#define	TSI_WUCNTR_WUCNT_SHIFT 0

#define	TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK)

#define	TSI_CNTR1_CTN1_MASK 0xFFFFu

#define	TSI_CNTR1_CTN1_SHIFT 0

#define	TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK)

#define	TSI_CNTR1_CTN_MASK 0xFFFF0000u

#define	TSI_CNTR1_CTN_SHIFT 16

#define	TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK)

#define	TSI_CNTR3_CTN1_MASK 0xFFFFu

#define	TSI_CNTR3_CTN1_SHIFT 0

#define	TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK)

#define	TSI_CNTR3_CTN_MASK 0xFFFF0000u

#define	TSI_CNTR3_CTN_SHIFT 16

#define	TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK)

#define	TSI_CNTR5_CTN1_MASK 0xFFFFu

#define	TSI_CNTR5_CTN1_SHIFT 0

#define	TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK)

#define	TSI_CNTR5_CTN_MASK 0xFFFF0000u

#define	TSI_CNTR5_CTN_SHIFT 16

#define	TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK)

#define	TSI_CNTR7_CTN1_MASK 0xFFFFu

#define	TSI_CNTR7_CTN1_SHIFT 0

#define	TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK)

#define	TSI_CNTR7_CTN_MASK 0xFFFF0000u

#define	TSI_CNTR7_CTN_SHIFT 16

#define	TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK)

#define	TSI_CNTR9_CTN1_MASK 0xFFFFu

#define	TSI_CNTR9_CTN1_SHIFT 0

#define	TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK)

#define	TSI_CNTR9_CTN_MASK 0xFFFF0000u

#define	TSI_CNTR9_CTN_SHIFT 16

#define	TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK)

#define	TSI_CNTR11_CTN1_MASK 0xFFFFu

#define	TSI_CNTR11_CTN1_SHIFT 0

#define	TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK)

#define	TSI_CNTR11_CTN_MASK 0xFFFF0000u

#define	TSI_CNTR11_CTN_SHIFT 16

#define	TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK)

#define	TSI_CNTR13_CTN1_MASK 0xFFFFu

#define	TSI_CNTR13_CTN1_SHIFT 0

#define	TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK)

#define	TSI_CNTR13_CTN_MASK 0xFFFF0000u

#define	TSI_CNTR13_CTN_SHIFT 16

#define	TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK)

#define	TSI_CNTR15_CTN1_MASK 0xFFFFu

#define	TSI_CNTR15_CTN1_SHIFT 0

#define	TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK)

#define	TSI_CNTR15_CTN_MASK 0xFFFF0000u

#define	TSI_CNTR15_CTN_SHIFT 16

#define	TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK)

#define	TSI_THRESHOLD_HTHH_MASK 0xFFFFu

#define	TSI_THRESHOLD_HTHH_SHIFT 0

#define	TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK)

#define	TSI_THRESHOLD_LTHH_MASK 0xFFFF0000u

#define	TSI_THRESHOLD_LTHH_SHIFT 16

#define	TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK)

#define	TSI0_BASE_PTR ((TSI_MemMapPtr)0x40045000u)

#define	TSI_BASE_PTRS { TSI0_BASE_PTR }

#define	TSI0_GENCS TSI_GENCS_REG(TSI0_BASE_PTR)

#define	TSI0_SCANC TSI_SCANC_REG(TSI0_BASE_PTR)

#define	TSI0_PEN TSI_PEN_REG(TSI0_BASE_PTR)

#define	TSI0_WUCNTR TSI_WUCNTR_REG(TSI0_BASE_PTR)

#define	TSI0_CNTR1 TSI_CNTR1_REG(TSI0_BASE_PTR)

#define	TSI0_CNTR3 TSI_CNTR3_REG(TSI0_BASE_PTR)

#define	TSI0_CNTR5 TSI_CNTR5_REG(TSI0_BASE_PTR)

#define	TSI0_CNTR7 TSI_CNTR7_REG(TSI0_BASE_PTR)

#define	TSI0_CNTR9 TSI_CNTR9_REG(TSI0_BASE_PTR)

#define	TSI0_CNTR11 TSI_CNTR11_REG(TSI0_BASE_PTR)

#define	TSI0_CNTR13 TSI_CNTR13_REG(TSI0_BASE_PTR)

#define	TSI0_CNTR15 TSI_CNTR15_REG(TSI0_BASE_PTR)

#define	TSI0_THRESHOLD TSI_THRESHOLD_REG(TSI0_BASE_PTR)

#define	UART_BDH_REG(base) ((base)->BDH)

#define	UART_BDL_REG(base) ((base)->BDL)

#define	UART_C1_REG(base) ((base)->C1)

#define	UART_C2_REG(base) ((base)->C2)

#define	UART_S1_REG(base) ((base)->S1)

#define	UART_S2_REG(base) ((base)->S2)

#define	UART_C3_REG(base) ((base)->C3)

#define	UART_D_REG(base) ((base)->D)

#define	UART_MA1_REG(base) ((base)->MA1)

#define	UART_MA2_REG(base) ((base)->MA2)

#define	UART_C4_REG(base) ((base)->C4)

#define	UART_C5_REG(base) ((base)->C5)

#define	UART_ED_REG(base) ((base)->ED)

#define	UART_MODEM_REG(base) ((base)->MODEM)

#define	UART_IR_REG(base) ((base)->IR)

#define	UART_PFIFO_REG(base) ((base)->PFIFO)

#define	UART_CFIFO_REG(base) ((base)->CFIFO)

#define	UART_SFIFO_REG(base) ((base)->SFIFO)

#define	UART_TWFIFO_REG(base) ((base)->TWFIFO)

#define	UART_TCFIFO_REG(base) ((base)->TCFIFO)

#define	UART_RWFIFO_REG(base) ((base)->RWFIFO)

#define	UART_RCFIFO_REG(base) ((base)->RCFIFO)

#define	UART_C7816_REG(base) ((base)->C7816)

#define	UART_IE7816_REG(base) ((base)->IE7816)

#define	UART_IS7816_REG(base) ((base)->IS7816)

#define	UART_WP7816T0_REG(base) ((base)->WP7816T0)

#define	UART_WP7816T1_REG(base) ((base)->WP7816T1)

#define	UART_WN7816_REG(base) ((base)->WN7816)

#define	UART_WF7816_REG(base) ((base)->WF7816)

#define	UART_ET7816_REG(base) ((base)->ET7816)

#define	UART_TL7816_REG(base) ((base)->TL7816)

#define	UART_C6_REG(base) ((base)->C6)

#define	UART_PCTH_REG(base) ((base)->PCTH)

#define	UART_PCTL_REG(base) ((base)->PCTL)

#define	UART_B1T_REG(base) ((base)->B1T)

#define	UART_SDTH_REG(base) ((base)->SDTH)

#define	UART_SDTL_REG(base) ((base)->SDTL)

#define	UART_PRE_REG(base) ((base)->PRE)

#define	UART_TPL_REG(base) ((base)->TPL)

#define	UART_IE_REG(base) ((base)->IE)

#define	UART_WB_REG(base) ((base)->WB)

#define	UART_S3_REG(base) ((base)->S3)

#define	UART_S4_REG(base) ((base)->S4)

#define	UART_RPL_REG(base) ((base)->RPL)

#define	UART_RPREL_REG(base) ((base)->RPREL)

#define	UART_CPW_REG(base) ((base)->CPW)

#define	UART_RIDT_REG(base) ((base)->RIDT)

#define	UART_TIDT_REG(base) ((base)->TIDT)

#define	UART_BDH_SBR_MASK 0x1Fu

#define	UART_BDH_SBR_SHIFT 0

#define	UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)

#define	UART_BDH_RXEDGIE_MASK 0x40u

#define	UART_BDH_RXEDGIE_SHIFT 6

#define	UART_BDH_LBKDIE_MASK 0x80u

#define	UART_BDH_LBKDIE_SHIFT 7

#define	UART_BDL_SBR_MASK 0xFFu

#define	UART_BDL_SBR_SHIFT 0

#define	UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)

#define	UART_C1_PT_MASK 0x1u

#define	UART_C1_PT_SHIFT 0

#define	UART_C1_PE_MASK 0x2u

#define	UART_C1_PE_SHIFT 1

#define	UART_C1_ILT_MASK 0x4u

#define	UART_C1_ILT_SHIFT 2

#define	UART_C1_WAKE_MASK 0x8u

#define	UART_C1_WAKE_SHIFT 3

#define	UART_C1_M_MASK 0x10u

#define	UART_C1_M_SHIFT 4

#define	UART_C1_RSRC_MASK 0x20u

#define	UART_C1_RSRC_SHIFT 5

#define	UART_C1_UARTSWAI_MASK 0x40u

#define	UART_C1_UARTSWAI_SHIFT 6

#define	UART_C1_LOOPS_MASK 0x80u

#define	UART_C1_LOOPS_SHIFT 7

#define	UART_C2_SBK_MASK 0x1u

#define	UART_C2_SBK_SHIFT 0

#define	UART_C2_RWU_MASK 0x2u

#define	UART_C2_RWU_SHIFT 1

#define	UART_C2_RE_MASK 0x4u

#define	UART_C2_RE_SHIFT 2

#define	UART_C2_TE_MASK 0x8u

#define	UART_C2_TE_SHIFT 3

#define	UART_C2_ILIE_MASK 0x10u

#define	UART_C2_ILIE_SHIFT 4

#define	UART_C2_RIE_MASK 0x20u

#define	UART_C2_RIE_SHIFT 5

#define	UART_C2_TCIE_MASK 0x40u

#define	UART_C2_TCIE_SHIFT 6

#define	UART_C2_TIE_MASK 0x80u

#define	UART_C2_TIE_SHIFT 7

#define	UART_S1_PF_MASK 0x1u

#define	UART_S1_PF_SHIFT 0

#define	UART_S1_FE_MASK 0x2u

#define	UART_S1_FE_SHIFT 1

#define	UART_S1_NF_MASK 0x4u

#define	UART_S1_NF_SHIFT 2

#define	UART_S1_OR_MASK 0x8u

#define	UART_S1_OR_SHIFT 3

#define	UART_S1_IDLE_MASK 0x10u

#define	UART_S1_IDLE_SHIFT 4

#define	UART_S1_RDRF_MASK 0x20u

#define	UART_S1_RDRF_SHIFT 5

#define	UART_S1_TC_MASK 0x40u

#define	UART_S1_TC_SHIFT 6

#define	UART_S1_TDRE_MASK 0x80u

#define	UART_S1_TDRE_SHIFT 7

#define	UART_S2_RAF_MASK 0x1u

#define	UART_S2_RAF_SHIFT 0

#define	UART_S2_LBKDE_MASK 0x2u

#define	UART_S2_LBKDE_SHIFT 1

#define	UART_S2_BRK13_MASK 0x4u

#define	UART_S2_BRK13_SHIFT 2

#define	UART_S2_RWUID_MASK 0x8u

#define	UART_S2_RWUID_SHIFT 3

#define	UART_S2_RXINV_MASK 0x10u

#define	UART_S2_RXINV_SHIFT 4

#define	UART_S2_MSBF_MASK 0x20u

#define	UART_S2_MSBF_SHIFT 5

#define	UART_S2_RXEDGIF_MASK 0x40u

#define	UART_S2_RXEDGIF_SHIFT 6

#define	UART_S2_LBKDIF_MASK 0x80u

#define	UART_S2_LBKDIF_SHIFT 7

#define	UART_C3_PEIE_MASK 0x1u

#define	UART_C3_PEIE_SHIFT 0

#define	UART_C3_FEIE_MASK 0x2u

#define	UART_C3_FEIE_SHIFT 1

#define	UART_C3_NEIE_MASK 0x4u

#define	UART_C3_NEIE_SHIFT 2

#define	UART_C3_ORIE_MASK 0x8u

#define	UART_C3_ORIE_SHIFT 3

#define	UART_C3_TXINV_MASK 0x10u

#define	UART_C3_TXINV_SHIFT 4

#define	UART_C3_TXDIR_MASK 0x20u

#define	UART_C3_TXDIR_SHIFT 5

#define	UART_C3_T8_MASK 0x40u

#define	UART_C3_T8_SHIFT 6

#define	UART_C3_R8_MASK 0x80u

#define	UART_C3_R8_SHIFT 7

#define	UART_D_RT_MASK 0xFFu

#define	UART_D_RT_SHIFT 0

#define	UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)

#define	UART_MA1_MA_MASK 0xFFu

#define	UART_MA1_MA_SHIFT 0

#define	UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)

#define	UART_MA2_MA_MASK 0xFFu

#define	UART_MA2_MA_SHIFT 0

#define	UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)

#define	UART_C4_BRFA_MASK 0x1Fu

#define	UART_C4_BRFA_SHIFT 0

#define	UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)

#define	UART_C4_M10_MASK 0x20u

#define	UART_C4_M10_SHIFT 5

#define	UART_C4_MAEN2_MASK 0x40u

#define	UART_C4_MAEN2_SHIFT 6

#define	UART_C4_MAEN1_MASK 0x80u

#define	UART_C4_MAEN1_SHIFT 7

#define	UART_C5_RDMAS_MASK 0x20u

#define	UART_C5_RDMAS_SHIFT 5

#define	UART_C5_TDMAS_MASK 0x80u

#define	UART_C5_TDMAS_SHIFT 7

#define	UART_ED_PARITYE_MASK 0x40u

#define	UART_ED_PARITYE_SHIFT 6

#define	UART_ED_NOISY_MASK 0x80u

#define	UART_ED_NOISY_SHIFT 7

#define	UART_MODEM_TXCTSE_MASK 0x1u

#define	UART_MODEM_TXCTSE_SHIFT 0

#define	UART_MODEM_TXRTSE_MASK 0x2u

#define	UART_MODEM_TXRTSE_SHIFT 1

#define	UART_MODEM_TXRTSPOL_MASK 0x4u

#define	UART_MODEM_TXRTSPOL_SHIFT 2

#define	UART_MODEM_RXRTSE_MASK 0x8u

#define	UART_MODEM_RXRTSE_SHIFT 3

#define	UART_IR_TNP_MASK 0x3u

#define	UART_IR_TNP_SHIFT 0

#define	UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)

#define	UART_IR_IREN_MASK 0x4u

#define	UART_IR_IREN_SHIFT 2

#define	UART_PFIFO_RXFIFOSIZE_MASK 0x7u

#define	UART_PFIFO_RXFIFOSIZE_SHIFT 0

#define	UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)

#define	UART_PFIFO_RXFE_MASK 0x8u

#define	UART_PFIFO_RXFE_SHIFT 3

#define	UART_PFIFO_TXFIFOSIZE_MASK 0x70u

#define	UART_PFIFO_TXFIFOSIZE_SHIFT 4

#define	UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)

#define	UART_PFIFO_TXFE_MASK 0x80u

#define	UART_PFIFO_TXFE_SHIFT 7

#define	UART_CFIFO_RXUFE_MASK 0x1u

#define	UART_CFIFO_RXUFE_SHIFT 0

#define	UART_CFIFO_TXOFE_MASK 0x2u

#define	UART_CFIFO_TXOFE_SHIFT 1

#define	UART_CFIFO_RXOFE_MASK 0x4u

#define	UART_CFIFO_RXOFE_SHIFT 2

#define	UART_CFIFO_RXFLUSH_MASK 0x40u

#define	UART_CFIFO_RXFLUSH_SHIFT 6

#define	UART_CFIFO_TXFLUSH_MASK 0x80u

#define	UART_CFIFO_TXFLUSH_SHIFT 7

#define	UART_SFIFO_RXUF_MASK 0x1u

#define	UART_SFIFO_RXUF_SHIFT 0

#define	UART_SFIFO_TXOF_MASK 0x2u

#define	UART_SFIFO_TXOF_SHIFT 1

#define	UART_SFIFO_RXOF_MASK 0x4u

#define	UART_SFIFO_RXOF_SHIFT 2

#define	UART_SFIFO_RXEMPT_MASK 0x40u

#define	UART_SFIFO_RXEMPT_SHIFT 6

#define	UART_SFIFO_TXEMPT_MASK 0x80u

#define	UART_SFIFO_TXEMPT_SHIFT 7

#define	UART_TWFIFO_TXWATER_MASK 0xFFu

#define	UART_TWFIFO_TXWATER_SHIFT 0

#define	UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)

#define	UART_TCFIFO_TXCOUNT_MASK 0xFFu

#define	UART_TCFIFO_TXCOUNT_SHIFT 0

#define	UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)

#define	UART_RWFIFO_RXWATER_MASK 0xFFu

#define	UART_RWFIFO_RXWATER_SHIFT 0

#define	UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)

#define	UART_RCFIFO_RXCOUNT_MASK 0xFFu

#define	UART_RCFIFO_RXCOUNT_SHIFT 0

#define	UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)

#define	UART_C7816_ISO_7816E_MASK 0x1u

#define	UART_C7816_ISO_7816E_SHIFT 0

#define	UART_C7816_TTYPE_MASK 0x2u

#define	UART_C7816_TTYPE_SHIFT 1

#define	UART_C7816_INIT_MASK 0x4u

#define	UART_C7816_INIT_SHIFT 2

#define	UART_C7816_ANACK_MASK 0x8u

#define	UART_C7816_ANACK_SHIFT 3

#define	UART_C7816_ONACK_MASK 0x10u

#define	UART_C7816_ONACK_SHIFT 4

#define	UART_IE7816_RXTE_MASK 0x1u

#define	UART_IE7816_RXTE_SHIFT 0

#define	UART_IE7816_TXTE_MASK 0x2u

#define	UART_IE7816_TXTE_SHIFT 1

#define	UART_IE7816_GTVE_MASK 0x4u

#define	UART_IE7816_GTVE_SHIFT 2

#define	UART_IE7816_INITDE_MASK 0x10u

#define	UART_IE7816_INITDE_SHIFT 4

#define	UART_IE7816_BWTE_MASK 0x20u

#define	UART_IE7816_BWTE_SHIFT 5

#define	UART_IE7816_CWTE_MASK 0x40u

#define	UART_IE7816_CWTE_SHIFT 6

#define	UART_IE7816_WTE_MASK 0x80u

#define	UART_IE7816_WTE_SHIFT 7

#define	UART_IS7816_RXT_MASK 0x1u

#define	UART_IS7816_RXT_SHIFT 0

#define	UART_IS7816_TXT_MASK 0x2u

#define	UART_IS7816_TXT_SHIFT 1

#define	UART_IS7816_GTV_MASK 0x4u

#define	UART_IS7816_GTV_SHIFT 2

#define	UART_IS7816_INITD_MASK 0x10u

#define	UART_IS7816_INITD_SHIFT 4

#define	UART_IS7816_BWT_MASK 0x20u

#define	UART_IS7816_BWT_SHIFT 5

#define	UART_IS7816_CWT_MASK 0x40u

#define	UART_IS7816_CWT_SHIFT 6

#define	UART_IS7816_WT_MASK 0x80u

#define	UART_IS7816_WT_SHIFT 7

#define	UART_WP7816T0_WI_MASK 0xFFu

#define	UART_WP7816T0_WI_SHIFT 0

#define	UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T0_WI_SHIFT))&UART_WP7816T0_WI_MASK)

#define	UART_WP7816T1_BWI_MASK 0xFu

#define	UART_WP7816T1_BWI_SHIFT 0

#define	UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_BWI_SHIFT))&UART_WP7816T1_BWI_MASK)

#define	UART_WP7816T1_CWI_MASK 0xF0u

#define	UART_WP7816T1_CWI_SHIFT 4

#define	UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_CWI_SHIFT))&UART_WP7816T1_CWI_MASK)

#define	UART_WN7816_GTN_MASK 0xFFu

#define	UART_WN7816_GTN_SHIFT 0

#define	UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)

#define	UART_WF7816_GTFD_MASK 0xFFu

#define	UART_WF7816_GTFD_SHIFT 0

#define	UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)

#define	UART_ET7816_RXTHRESHOLD_MASK 0xFu

#define	UART_ET7816_RXTHRESHOLD_SHIFT 0

#define	UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)

#define	UART_ET7816_TXTHRESHOLD_MASK 0xF0u

#define	UART_ET7816_TXTHRESHOLD_SHIFT 4

#define	UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)

#define	UART_TL7816_TLEN_MASK 0xFFu

#define	UART_TL7816_TLEN_SHIFT 0

#define	UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)

#define	UART_C6_CP_MASK 0x10u

#define	UART_C6_CP_SHIFT 4

#define	UART_C6_CE_MASK 0x20u

#define	UART_C6_CE_SHIFT 5

#define	UART_C6_TX709_MASK 0x40u

#define	UART_C6_TX709_SHIFT 6

#define	UART_C6_EN709_MASK 0x80u

#define	UART_C6_EN709_SHIFT 7

#define	UART_PCTH_PCTH_MASK 0xFFu

#define	UART_PCTH_PCTH_SHIFT 0

#define	UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK)

#define	UART_PCTL_PCTL_MASK 0xFFu

#define	UART_PCTL_PCTL_SHIFT 0

#define	UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK)

#define	UART_B1T_B1T_MASK 0xFFu

#define	UART_B1T_B1T_SHIFT 0

#define	UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK)

#define	UART_SDTH_SDTH_MASK 0xFFu

#define	UART_SDTH_SDTH_SHIFT 0

#define	UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK)

#define	UART_SDTL_SDTL_MASK 0xFFu

#define	UART_SDTL_SDTL_SHIFT 0

#define	UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK)

#define	UART_PRE_PREAMBLE_MASK 0xFFu

#define	UART_PRE_PREAMBLE_SHIFT 0

#define	UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK)

#define	UART_TPL_TPL_MASK 0xFFu

#define	UART_TPL_TPL_SHIFT 0

#define	UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK)

#define	UART_IE_TXFIE_MASK 0x1u

#define	UART_IE_TXFIE_SHIFT 0

#define	UART_IE_PSIE_MASK 0x2u

#define	UART_IE_PSIE_SHIFT 1

#define	UART_IE_PCTEIE_MASK 0x4u

#define	UART_IE_PCTEIE_SHIFT 2

#define	UART_IE_PTXIE_MASK 0x8u

#define	UART_IE_PTXIE_SHIFT 3

#define	UART_IE_PRXIE_MASK 0x10u

#define	UART_IE_PRXIE_SHIFT 4

#define	UART_IE_ISDIE_MASK 0x20u

#define	UART_IE_ISDIE_SHIFT 5

#define	UART_IE_WBEIE_MASK 0x40u

#define	UART_IE_WBEIE_SHIFT 6

#define	UART_WB_WBASE_MASK 0xFFu

#define	UART_WB_WBASE_SHIFT 0

#define	UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK)

#define	UART_S3_TXFF_MASK 0x1u

#define	UART_S3_TXFF_SHIFT 0

#define	UART_S3_PSF_MASK 0x2u

#define	UART_S3_PSF_SHIFT 1

#define	UART_S3_PCTEF_MASK 0x4u

#define	UART_S3_PCTEF_SHIFT 2

#define	UART_S3_PTXF_MASK 0x8u

#define	UART_S3_PTXF_SHIFT 3

#define	UART_S3_PRXF_MASK 0x10u

#define	UART_S3_PRXF_SHIFT 4

#define	UART_S3_ISD_MASK 0x20u

#define	UART_S3_ISD_SHIFT 5

#define	UART_S3_WBEF_MASK 0x40u

#define	UART_S3_WBEF_SHIFT 6

#define	UART_S3_PEF_MASK 0x80u

#define	UART_S3_PEF_SHIFT 7

#define	UART_S4_FE_MASK 0x1u

#define	UART_S4_FE_SHIFT 0

#define	UART_S4_ILCV_MASK 0x2u

#define	UART_S4_ILCV_SHIFT 1

#define	UART_S4_CDET_MASK 0xCu

#define	UART_S4_CDET_SHIFT 2

#define	UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK)

#define	UART_S4_INITF_MASK 0x10u

#define	UART_S4_INITF_SHIFT 4

#define	UART_RPL_RPL_MASK 0xFFu

#define	UART_RPL_RPL_SHIFT 0

#define	UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK)

#define	UART_RPREL_RPREL_MASK 0xFFu

#define	UART_RPREL_RPREL_SHIFT 0

#define	UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK)

#define	UART_CPW_CPW_MASK 0xFFu

#define	UART_CPW_CPW_SHIFT 0

#define	UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK)

#define	UART_RIDT_RIDT_MASK 0xFFu

#define	UART_RIDT_RIDT_SHIFT 0

#define	UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK)

#define	UART_TIDT_TIDT_MASK 0xFFu

#define	UART_TIDT_TIDT_SHIFT 0

#define	UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK)

#define	UART0_BASE_PTR ((UART_MemMapPtr)0x4006A000u)

#define	UART1_BASE_PTR ((UART_MemMapPtr)0x4006B000u)

#define	UART2_BASE_PTR ((UART_MemMapPtr)0x4006C000u)

#define	UART3_BASE_PTR ((UART_MemMapPtr)0x4006D000u)

#define	UART4_BASE_PTR ((UART_MemMapPtr)0x400EA000u)

#define	UART5_BASE_PTR ((UART_MemMapPtr)0x400EB000u)

#define	UART_BASE_PTRS { UART0_BASE_PTR, UART1_BASE_PTR, UART2_BASE_PTR, UART3_BASE_PTR, UART4_BASE_PTR, UART5_BASE_PTR }

#define	UART0_BDH UART_BDH_REG(UART0_BASE_PTR)

#define	UART0_BDL UART_BDL_REG(UART0_BASE_PTR)

#define	UART0_C1 UART_C1_REG(UART0_BASE_PTR)

#define	UART0_C2 UART_C2_REG(UART0_BASE_PTR)

#define	UART0_S1 UART_S1_REG(UART0_BASE_PTR)

#define	UART0_S2 UART_S2_REG(UART0_BASE_PTR)

#define	UART0_C3 UART_C3_REG(UART0_BASE_PTR)

#define	UART0_D UART_D_REG(UART0_BASE_PTR)

#define	UART0_MA1 UART_MA1_REG(UART0_BASE_PTR)

#define	UART0_MA2 UART_MA2_REG(UART0_BASE_PTR)

#define	UART0_C4 UART_C4_REG(UART0_BASE_PTR)

#define	UART0_C5 UART_C5_REG(UART0_BASE_PTR)

#define	UART0_ED UART_ED_REG(UART0_BASE_PTR)

#define	UART0_MODEM UART_MODEM_REG(UART0_BASE_PTR)

#define	UART0_IR UART_IR_REG(UART0_BASE_PTR)

#define	UART0_PFIFO UART_PFIFO_REG(UART0_BASE_PTR)

#define	UART0_CFIFO UART_CFIFO_REG(UART0_BASE_PTR)

#define	UART0_SFIFO UART_SFIFO_REG(UART0_BASE_PTR)

#define	UART0_TWFIFO UART_TWFIFO_REG(UART0_BASE_PTR)

#define	UART0_TCFIFO UART_TCFIFO_REG(UART0_BASE_PTR)

#define	UART0_RWFIFO UART_RWFIFO_REG(UART0_BASE_PTR)

#define	UART0_RCFIFO UART_RCFIFO_REG(UART0_BASE_PTR)

#define	UART0_C7816 UART_C7816_REG(UART0_BASE_PTR)

#define	UART0_IE7816 UART_IE7816_REG(UART0_BASE_PTR)

#define	UART0_IS7816 UART_IS7816_REG(UART0_BASE_PTR)

#define	UART0_WP7816T0 UART_WP7816T0_REG(UART0_BASE_PTR)

#define	UART0_WP7816T1 UART_WP7816T1_REG(UART0_BASE_PTR)

#define	UART0_WN7816 UART_WN7816_REG(UART0_BASE_PTR)

#define	UART0_WF7816 UART_WF7816_REG(UART0_BASE_PTR)

#define	UART0_ET7816 UART_ET7816_REG(UART0_BASE_PTR)

#define	UART0_TL7816 UART_TL7816_REG(UART0_BASE_PTR)

#define	UART0_C6 UART_C6_REG(UART0_BASE_PTR)

#define	UART0_PCTH UART_PCTH_REG(UART0_BASE_PTR)

#define	UART0_PCTL UART_PCTL_REG(UART0_BASE_PTR)

#define	UART0_B1T UART_B1T_REG(UART0_BASE_PTR)

#define	UART0_SDTH UART_SDTH_REG(UART0_BASE_PTR)

#define	UART0_SDTL UART_SDTL_REG(UART0_BASE_PTR)

#define	UART0_PRE UART_PRE_REG(UART0_BASE_PTR)

#define	UART0_TPL UART_TPL_REG(UART0_BASE_PTR)

#define	UART0_IE UART_IE_REG(UART0_BASE_PTR)

#define	UART0_WB UART_WB_REG(UART0_BASE_PTR)

#define	UART0_S3 UART_S3_REG(UART0_BASE_PTR)

#define	UART0_S4 UART_S4_REG(UART0_BASE_PTR)

#define	UART0_RPL UART_RPL_REG(UART0_BASE_PTR)

#define	UART0_RPREL UART_RPREL_REG(UART0_BASE_PTR)

#define	UART0_CPW UART_CPW_REG(UART0_BASE_PTR)

#define	UART0_RIDT UART_RIDT_REG(UART0_BASE_PTR)

#define	UART0_TIDT UART_TIDT_REG(UART0_BASE_PTR)

#define	UART1_BDH UART_BDH_REG(UART1_BASE_PTR)

#define	UART1_BDL UART_BDL_REG(UART1_BASE_PTR)

#define	UART1_C1 UART_C1_REG(UART1_BASE_PTR)

#define	UART1_C2 UART_C2_REG(UART1_BASE_PTR)

#define	UART1_S1 UART_S1_REG(UART1_BASE_PTR)

#define	UART1_S2 UART_S2_REG(UART1_BASE_PTR)

#define	UART1_C3 UART_C3_REG(UART1_BASE_PTR)

#define	UART1_D UART_D_REG(UART1_BASE_PTR)

#define	UART1_MA1 UART_MA1_REG(UART1_BASE_PTR)

#define	UART1_MA2 UART_MA2_REG(UART1_BASE_PTR)

#define	UART1_C4 UART_C4_REG(UART1_BASE_PTR)

#define	UART1_C5 UART_C5_REG(UART1_BASE_PTR)

#define	UART1_ED UART_ED_REG(UART1_BASE_PTR)

#define	UART1_MODEM UART_MODEM_REG(UART1_BASE_PTR)

#define	UART1_IR UART_IR_REG(UART1_BASE_PTR)

#define	UART1_PFIFO UART_PFIFO_REG(UART1_BASE_PTR)

#define	UART1_CFIFO UART_CFIFO_REG(UART1_BASE_PTR)

#define	UART1_SFIFO UART_SFIFO_REG(UART1_BASE_PTR)

#define	UART1_TWFIFO UART_TWFIFO_REG(UART1_BASE_PTR)

#define	UART1_TCFIFO UART_TCFIFO_REG(UART1_BASE_PTR)

#define	UART1_RWFIFO UART_RWFIFO_REG(UART1_BASE_PTR)

#define	UART1_RCFIFO UART_RCFIFO_REG(UART1_BASE_PTR)

#define	UART1_C7816 UART_C7816_REG(UART1_BASE_PTR)

#define	UART1_IE7816 UART_IE7816_REG(UART1_BASE_PTR)

#define	UART1_IS7816 UART_IS7816_REG(UART1_BASE_PTR)

#define	UART1_WP7816T0 UART_WP7816T0_REG(UART1_BASE_PTR)

#define	UART1_WP7816T1 UART_WP7816T1_REG(UART1_BASE_PTR)

#define	UART1_WN7816 UART_WN7816_REG(UART1_BASE_PTR)

#define	UART1_WF7816 UART_WF7816_REG(UART1_BASE_PTR)

#define	UART1_ET7816 UART_ET7816_REG(UART1_BASE_PTR)

#define	UART1_TL7816 UART_TL7816_REG(UART1_BASE_PTR)

#define	UART2_BDH UART_BDH_REG(UART2_BASE_PTR)

#define	UART2_BDL UART_BDL_REG(UART2_BASE_PTR)

#define	UART2_C1 UART_C1_REG(UART2_BASE_PTR)

#define	UART2_C2 UART_C2_REG(UART2_BASE_PTR)

#define	UART2_S1 UART_S1_REG(UART2_BASE_PTR)

#define	UART2_S2 UART_S2_REG(UART2_BASE_PTR)

#define	UART2_C3 UART_C3_REG(UART2_BASE_PTR)

#define	UART2_D UART_D_REG(UART2_BASE_PTR)

#define	UART2_MA1 UART_MA1_REG(UART2_BASE_PTR)

#define	UART2_MA2 UART_MA2_REG(UART2_BASE_PTR)

#define	UART2_C4 UART_C4_REG(UART2_BASE_PTR)

#define	UART2_C5 UART_C5_REG(UART2_BASE_PTR)

#define	UART2_ED UART_ED_REG(UART2_BASE_PTR)

#define	UART2_MODEM UART_MODEM_REG(UART2_BASE_PTR)

#define	UART2_IR UART_IR_REG(UART2_BASE_PTR)

#define	UART2_PFIFO UART_PFIFO_REG(UART2_BASE_PTR)

#define	UART2_CFIFO UART_CFIFO_REG(UART2_BASE_PTR)

#define	UART2_SFIFO UART_SFIFO_REG(UART2_BASE_PTR)

#define	UART2_TWFIFO UART_TWFIFO_REG(UART2_BASE_PTR)

#define	UART2_TCFIFO UART_TCFIFO_REG(UART2_BASE_PTR)

#define	UART2_RWFIFO UART_RWFIFO_REG(UART2_BASE_PTR)

#define	UART2_RCFIFO UART_RCFIFO_REG(UART2_BASE_PTR)

#define	UART3_BDH UART_BDH_REG(UART3_BASE_PTR)

#define	UART3_BDL UART_BDL_REG(UART3_BASE_PTR)

#define	UART3_C1 UART_C1_REG(UART3_BASE_PTR)

#define	UART3_C2 UART_C2_REG(UART3_BASE_PTR)

#define	UART3_S1 UART_S1_REG(UART3_BASE_PTR)

#define	UART3_S2 UART_S2_REG(UART3_BASE_PTR)

#define	UART3_C3 UART_C3_REG(UART3_BASE_PTR)

#define	UART3_D UART_D_REG(UART3_BASE_PTR)

#define	UART3_MA1 UART_MA1_REG(UART3_BASE_PTR)

#define	UART3_MA2 UART_MA2_REG(UART3_BASE_PTR)

#define	UART3_C4 UART_C4_REG(UART3_BASE_PTR)

#define	UART3_C5 UART_C5_REG(UART3_BASE_PTR)

#define	UART3_ED UART_ED_REG(UART3_BASE_PTR)

#define	UART3_MODEM UART_MODEM_REG(UART3_BASE_PTR)

#define	UART3_IR UART_IR_REG(UART3_BASE_PTR)

#define	UART3_PFIFO UART_PFIFO_REG(UART3_BASE_PTR)

#define	UART3_CFIFO UART_CFIFO_REG(UART3_BASE_PTR)

#define	UART3_SFIFO UART_SFIFO_REG(UART3_BASE_PTR)

#define	UART3_TWFIFO UART_TWFIFO_REG(UART3_BASE_PTR)

#define	UART3_TCFIFO UART_TCFIFO_REG(UART3_BASE_PTR)

#define	UART3_RWFIFO UART_RWFIFO_REG(UART3_BASE_PTR)

#define	UART3_RCFIFO UART_RCFIFO_REG(UART3_BASE_PTR)

#define	UART4_BDH UART_BDH_REG(UART4_BASE_PTR)

#define	UART4_BDL UART_BDL_REG(UART4_BASE_PTR)

#define	UART4_C1 UART_C1_REG(UART4_BASE_PTR)

#define	UART4_C2 UART_C2_REG(UART4_BASE_PTR)

#define	UART4_S1 UART_S1_REG(UART4_BASE_PTR)

#define	UART4_S2 UART_S2_REG(UART4_BASE_PTR)

#define	UART4_C3 UART_C3_REG(UART4_BASE_PTR)

#define	UART4_D UART_D_REG(UART4_BASE_PTR)

#define	UART4_MA1 UART_MA1_REG(UART4_BASE_PTR)

#define	UART4_MA2 UART_MA2_REG(UART4_BASE_PTR)

#define	UART4_C4 UART_C4_REG(UART4_BASE_PTR)

#define	UART4_C5 UART_C5_REG(UART4_BASE_PTR)

#define	UART4_ED UART_ED_REG(UART4_BASE_PTR)

#define	UART4_MODEM UART_MODEM_REG(UART4_BASE_PTR)

#define	UART4_IR UART_IR_REG(UART4_BASE_PTR)

#define	UART4_PFIFO UART_PFIFO_REG(UART4_BASE_PTR)

#define	UART4_CFIFO UART_CFIFO_REG(UART4_BASE_PTR)

#define	UART4_SFIFO UART_SFIFO_REG(UART4_BASE_PTR)

#define	UART4_TWFIFO UART_TWFIFO_REG(UART4_BASE_PTR)

#define	UART4_TCFIFO UART_TCFIFO_REG(UART4_BASE_PTR)

#define	UART4_RWFIFO UART_RWFIFO_REG(UART4_BASE_PTR)

#define	UART4_RCFIFO UART_RCFIFO_REG(UART4_BASE_PTR)

#define	UART5_BDH UART_BDH_REG(UART5_BASE_PTR)

#define	UART5_BDL UART_BDL_REG(UART5_BASE_PTR)

#define	UART5_C1 UART_C1_REG(UART5_BASE_PTR)

#define	UART5_C2 UART_C2_REG(UART5_BASE_PTR)

#define	UART5_S1 UART_S1_REG(UART5_BASE_PTR)

#define	UART5_S2 UART_S2_REG(UART5_BASE_PTR)

#define	UART5_C3 UART_C3_REG(UART5_BASE_PTR)

#define	UART5_D UART_D_REG(UART5_BASE_PTR)

#define	UART5_MA1 UART_MA1_REG(UART5_BASE_PTR)

#define	UART5_MA2 UART_MA2_REG(UART5_BASE_PTR)

#define	UART5_C4 UART_C4_REG(UART5_BASE_PTR)

#define	UART5_C5 UART_C5_REG(UART5_BASE_PTR)

#define	UART5_ED UART_ED_REG(UART5_BASE_PTR)

#define	UART5_MODEM UART_MODEM_REG(UART5_BASE_PTR)

#define	UART5_IR UART_IR_REG(UART5_BASE_PTR)

#define	UART5_PFIFO UART_PFIFO_REG(UART5_BASE_PTR)

#define	UART5_CFIFO UART_CFIFO_REG(UART5_BASE_PTR)

#define	UART5_SFIFO UART_SFIFO_REG(UART5_BASE_PTR)

#define	UART5_TWFIFO UART_TWFIFO_REG(UART5_BASE_PTR)

#define	UART5_TCFIFO UART_TCFIFO_REG(UART5_BASE_PTR)

#define	UART5_RWFIFO UART_RWFIFO_REG(UART5_BASE_PTR)

#define	UART5_RCFIFO UART_RCFIFO_REG(UART5_BASE_PTR)

#define	USB_PERID_REG(base) ((base)->PERID)

#define	USB_IDCOMP_REG(base) ((base)->IDCOMP)

#define	USB_REV_REG(base) ((base)->REV)

#define	USB_ADDINFO_REG(base) ((base)->ADDINFO)

#define	USB_OTGISTAT_REG(base) ((base)->OTGISTAT)

#define	USB_OTGICR_REG(base) ((base)->OTGICR)

#define	USB_OTGSTAT_REG(base) ((base)->OTGSTAT)

#define	USB_OTGCTL_REG(base) ((base)->OTGCTL)

#define	USB_ISTAT_REG(base) ((base)->ISTAT)

#define	USB_INTEN_REG(base) ((base)->INTEN)

#define	USB_ERRSTAT_REG(base) ((base)->ERRSTAT)

#define	USB_ERREN_REG(base) ((base)->ERREN)

#define	USB_STAT_REG(base) ((base)->STAT)

#define	USB_CTL_REG(base) ((base)->CTL)

#define	USB_ADDR_REG(base) ((base)->ADDR)

#define	USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)

#define	USB_FRMNUML_REG(base) ((base)->FRMNUML)

#define	USB_FRMNUMH_REG(base) ((base)->FRMNUMH)

#define	USB_TOKEN_REG(base) ((base)->TOKEN)

#define	USB_SOFTHLD_REG(base) ((base)->SOFTHLD)

#define	USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)

#define	USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)

#define	USB_ENDPT_REG(base, index) ((base)->ENDPOINT[index].ENDPT)

#define	USB_USBCTRL_REG(base) ((base)->USBCTRL)

#define	USB_OBSERVE_REG(base) ((base)->OBSERVE)

#define	USB_CONTROL_REG(base) ((base)->CONTROL)

#define	USB_USBTRC0_REG(base) ((base)->USBTRC0)

#define	USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)

#define	USB_PERID_ID_MASK 0x3Fu

#define	USB_PERID_ID_SHIFT 0

#define	USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)

#define	USB_IDCOMP_NID_MASK 0x3Fu

#define	USB_IDCOMP_NID_SHIFT 0

#define	USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)

#define	USB_REV_REV_MASK 0xFFu

#define	USB_REV_REV_SHIFT 0

#define	USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)

#define	USB_ADDINFO_IEHOST_MASK 0x1u

#define	USB_ADDINFO_IEHOST_SHIFT 0

#define	USB_ADDINFO_IRQNUM_MASK 0xF8u

#define	USB_ADDINFO_IRQNUM_SHIFT 3

#define	USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)

#define	USB_OTGISTAT_AVBUSCHG_MASK 0x1u

#define	USB_OTGISTAT_AVBUSCHG_SHIFT 0

#define	USB_OTGISTAT_B_SESS_CHG_MASK 0x4u

#define	USB_OTGISTAT_B_SESS_CHG_SHIFT 2

#define	USB_OTGISTAT_SESSVLDCHG_MASK 0x8u

#define	USB_OTGISTAT_SESSVLDCHG_SHIFT 3

#define	USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u

#define	USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5

#define	USB_OTGISTAT_ONEMSEC_MASK 0x40u

#define	USB_OTGISTAT_ONEMSEC_SHIFT 6

#define	USB_OTGISTAT_IDCHG_MASK 0x80u

#define	USB_OTGISTAT_IDCHG_SHIFT 7

#define	USB_OTGICR_AVBUSEN_MASK 0x1u

#define	USB_OTGICR_AVBUSEN_SHIFT 0

#define	USB_OTGICR_BSESSEN_MASK 0x4u

#define	USB_OTGICR_BSESSEN_SHIFT 2

#define	USB_OTGICR_SESSVLDEN_MASK 0x8u

#define	USB_OTGICR_SESSVLDEN_SHIFT 3

#define	USB_OTGICR_LINESTATEEN_MASK 0x20u

#define	USB_OTGICR_LINESTATEEN_SHIFT 5

#define	USB_OTGICR_ONEMSECEN_MASK 0x40u

#define	USB_OTGICR_ONEMSECEN_SHIFT 6

#define	USB_OTGICR_IDEN_MASK 0x80u

#define	USB_OTGICR_IDEN_SHIFT 7

#define	USB_OTGSTAT_AVBUSVLD_MASK 0x1u

#define	USB_OTGSTAT_AVBUSVLD_SHIFT 0

#define	USB_OTGSTAT_BSESSEND_MASK 0x4u

#define	USB_OTGSTAT_BSESSEND_SHIFT 2

#define	USB_OTGSTAT_SESS_VLD_MASK 0x8u

#define	USB_OTGSTAT_SESS_VLD_SHIFT 3

#define	USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u

#define	USB_OTGSTAT_LINESTATESTABLE_SHIFT 5

#define	USB_OTGSTAT_ONEMSECEN_MASK 0x40u

#define	USB_OTGSTAT_ONEMSECEN_SHIFT 6

#define	USB_OTGSTAT_ID_MASK 0x80u

#define	USB_OTGSTAT_ID_SHIFT 7

#define	USB_OTGCTL_OTGEN_MASK 0x4u

#define	USB_OTGCTL_OTGEN_SHIFT 2

#define	USB_OTGCTL_DMLOW_MASK 0x10u

#define	USB_OTGCTL_DMLOW_SHIFT 4

#define	USB_OTGCTL_DPLOW_MASK 0x20u

#define	USB_OTGCTL_DPLOW_SHIFT 5

#define	USB_OTGCTL_DPHIGH_MASK 0x80u

#define	USB_OTGCTL_DPHIGH_SHIFT 7

#define	USB_ISTAT_USBRST_MASK 0x1u

#define	USB_ISTAT_USBRST_SHIFT 0

#define	USB_ISTAT_ERROR_MASK 0x2u

#define	USB_ISTAT_ERROR_SHIFT 1

#define	USB_ISTAT_SOFTOK_MASK 0x4u

#define	USB_ISTAT_SOFTOK_SHIFT 2

#define	USB_ISTAT_TOKDNE_MASK 0x8u

#define	USB_ISTAT_TOKDNE_SHIFT 3

#define	USB_ISTAT_SLEEP_MASK 0x10u

#define	USB_ISTAT_SLEEP_SHIFT 4

#define	USB_ISTAT_RESUME_MASK 0x20u

#define	USB_ISTAT_RESUME_SHIFT 5

#define	USB_ISTAT_ATTACH_MASK 0x40u

#define	USB_ISTAT_ATTACH_SHIFT 6

#define	USB_ISTAT_STALL_MASK 0x80u

#define	USB_ISTAT_STALL_SHIFT 7

#define	USB_INTEN_USBRSTEN_MASK 0x1u

#define	USB_INTEN_USBRSTEN_SHIFT 0

#define	USB_INTEN_ERROREN_MASK 0x2u

#define	USB_INTEN_ERROREN_SHIFT 1

#define	USB_INTEN_SOFTOKEN_MASK 0x4u

#define	USB_INTEN_SOFTOKEN_SHIFT 2

#define	USB_INTEN_TOKDNEEN_MASK 0x8u

#define	USB_INTEN_TOKDNEEN_SHIFT 3

#define	USB_INTEN_SLEEPEN_MASK 0x10u

#define	USB_INTEN_SLEEPEN_SHIFT 4

#define	USB_INTEN_RESUMEEN_MASK 0x20u

#define	USB_INTEN_RESUMEEN_SHIFT 5

#define	USB_INTEN_ATTACHEN_MASK 0x40u

#define	USB_INTEN_ATTACHEN_SHIFT 6

#define	USB_INTEN_STALLEN_MASK 0x80u

#define	USB_INTEN_STALLEN_SHIFT 7

#define	USB_ERRSTAT_PIDERR_MASK 0x1u

#define	USB_ERRSTAT_PIDERR_SHIFT 0

#define	USB_ERRSTAT_CRC5EOF_MASK 0x2u

#define	USB_ERRSTAT_CRC5EOF_SHIFT 1

#define	USB_ERRSTAT_CRC16_MASK 0x4u

#define	USB_ERRSTAT_CRC16_SHIFT 2

#define	USB_ERRSTAT_DFN8_MASK 0x8u

#define	USB_ERRSTAT_DFN8_SHIFT 3

#define	USB_ERRSTAT_BTOERR_MASK 0x10u

#define	USB_ERRSTAT_BTOERR_SHIFT 4

#define	USB_ERRSTAT_DMAERR_MASK 0x20u

#define	USB_ERRSTAT_DMAERR_SHIFT 5

#define	USB_ERRSTAT_BTSERR_MASK 0x80u

#define	USB_ERRSTAT_BTSERR_SHIFT 7

#define	USB_ERREN_PIDERREN_MASK 0x1u

#define	USB_ERREN_PIDERREN_SHIFT 0

#define	USB_ERREN_CRC5EOFEN_MASK 0x2u

#define	USB_ERREN_CRC5EOFEN_SHIFT 1

#define	USB_ERREN_CRC16EN_MASK 0x4u

#define	USB_ERREN_CRC16EN_SHIFT 2

#define	USB_ERREN_DFN8EN_MASK 0x8u

#define	USB_ERREN_DFN8EN_SHIFT 3

#define	USB_ERREN_BTOERREN_MASK 0x10u

#define	USB_ERREN_BTOERREN_SHIFT 4

#define	USB_ERREN_DMAERREN_MASK 0x20u

#define	USB_ERREN_DMAERREN_SHIFT 5

#define	USB_ERREN_BTSERREN_MASK 0x80u

#define	USB_ERREN_BTSERREN_SHIFT 7

#define	USB_STAT_ODD_MASK 0x4u

#define	USB_STAT_ODD_SHIFT 2

#define	USB_STAT_TX_MASK 0x8u

#define	USB_STAT_TX_SHIFT 3

#define	USB_STAT_ENDP_MASK 0xF0u

#define	USB_STAT_ENDP_SHIFT 4

#define	USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)

#define	USB_CTL_USBENSOFEN_MASK 0x1u

#define	USB_CTL_USBENSOFEN_SHIFT 0

#define	USB_CTL_ODDRST_MASK 0x2u

#define	USB_CTL_ODDRST_SHIFT 1

#define	USB_CTL_RESUME_MASK 0x4u

#define	USB_CTL_RESUME_SHIFT 2

#define	USB_CTL_HOSTMODEEN_MASK 0x8u

#define	USB_CTL_HOSTMODEEN_SHIFT 3

#define	USB_CTL_RESET_MASK 0x10u

#define	USB_CTL_RESET_SHIFT 4

#define	USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u

#define	USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5

#define	USB_CTL_SE0_MASK 0x40u

#define	USB_CTL_SE0_SHIFT 6

#define	USB_CTL_JSTATE_MASK 0x80u

#define	USB_CTL_JSTATE_SHIFT 7

#define	USB_ADDR_ADDR_MASK 0x7Fu

#define	USB_ADDR_ADDR_SHIFT 0

#define	USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)

#define	USB_ADDR_LSEN_MASK 0x80u

#define	USB_ADDR_LSEN_SHIFT 7

#define	USB_BDTPAGE1_BDTBA_MASK 0xFEu

#define	USB_BDTPAGE1_BDTBA_SHIFT 1

#define	USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)

#define	USB_FRMNUML_FRM_MASK 0xFFu

#define	USB_FRMNUML_FRM_SHIFT 0

#define	USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)

#define	USB_FRMNUMH_FRM_MASK 0x7u

#define	USB_FRMNUMH_FRM_SHIFT 0

#define	USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)

#define	USB_TOKEN_TOKENENDPT_MASK 0xFu

#define	USB_TOKEN_TOKENENDPT_SHIFT 0

#define	USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)

#define	USB_TOKEN_TOKENPID_MASK 0xF0u

#define	USB_TOKEN_TOKENPID_SHIFT 4

#define	USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)

#define	USB_SOFTHLD_CNT_MASK 0xFFu

#define	USB_SOFTHLD_CNT_SHIFT 0

#define	USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)

#define	USB_BDTPAGE2_BDTBA_MASK 0xFFu

#define	USB_BDTPAGE2_BDTBA_SHIFT 0

#define	USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)

#define	USB_BDTPAGE3_BDTBA_MASK 0xFFu

#define	USB_BDTPAGE3_BDTBA_SHIFT 0

#define	USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)

#define	USB_ENDPT_EPHSHK_MASK 0x1u

#define	USB_ENDPT_EPHSHK_SHIFT 0

#define	USB_ENDPT_EPSTALL_MASK 0x2u

#define	USB_ENDPT_EPSTALL_SHIFT 1

#define	USB_ENDPT_EPTXEN_MASK 0x4u

#define	USB_ENDPT_EPTXEN_SHIFT 2

#define	USB_ENDPT_EPRXEN_MASK 0x8u

#define	USB_ENDPT_EPRXEN_SHIFT 3

#define	USB_ENDPT_EPCTLDIS_MASK 0x10u

#define	USB_ENDPT_EPCTLDIS_SHIFT 4

#define	USB_ENDPT_RETRYDIS_MASK 0x40u

#define	USB_ENDPT_RETRYDIS_SHIFT 6

#define	USB_ENDPT_HOSTWOHUB_MASK 0x80u

#define	USB_ENDPT_HOSTWOHUB_SHIFT 7

#define	USB_USBCTRL_PDE_MASK 0x40u

#define	USB_USBCTRL_PDE_SHIFT 6

#define	USB_USBCTRL_SUSP_MASK 0x80u

#define	USB_USBCTRL_SUSP_SHIFT 7

#define	USB_OBSERVE_DMPD_MASK 0x10u

#define	USB_OBSERVE_DMPD_SHIFT 4

#define	USB_OBSERVE_DPPD_MASK 0x40u

#define	USB_OBSERVE_DPPD_SHIFT 6

#define	USB_OBSERVE_DPPU_MASK 0x80u

#define	USB_OBSERVE_DPPU_SHIFT 7

#define	USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u

#define	USB_CONTROL_DPPULLUPNONOTG_SHIFT 4

#define	USB_USBTRC0_USB_RESUME_INT_MASK 0x1u

#define	USB_USBTRC0_USB_RESUME_INT_SHIFT 0

#define	USB_USBTRC0_SYNC_DET_MASK 0x2u

#define	USB_USBTRC0_SYNC_DET_SHIFT 1

#define	USB_USBTRC0_USBRESMEN_MASK 0x20u

#define	USB_USBTRC0_USBRESMEN_SHIFT 5

#define	USB_USBTRC0_USBRESET_MASK 0x80u

#define	USB_USBTRC0_USBRESET_SHIFT 7

#define	USB_USBFRMADJUST_ADJ_MASK 0xFFu

#define	USB_USBFRMADJUST_ADJ_SHIFT 0

#define	USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)

#define	USB0_BASE_PTR ((USB_MemMapPtr)0x40072000u)

#define	USB_BASE_PTRS { USB0_BASE_PTR }

#define	USB0_PERID USB_PERID_REG(USB0_BASE_PTR)

#define	USB0_IDCOMP USB_IDCOMP_REG(USB0_BASE_PTR)

#define	USB0_REV USB_REV_REG(USB0_BASE_PTR)

#define	USB0_ADDINFO USB_ADDINFO_REG(USB0_BASE_PTR)

#define	USB0_OTGISTAT USB_OTGISTAT_REG(USB0_BASE_PTR)

#define	USB0_OTGICR USB_OTGICR_REG(USB0_BASE_PTR)

#define	USB0_OTGSTAT USB_OTGSTAT_REG(USB0_BASE_PTR)

#define	USB0_OTGCTL USB_OTGCTL_REG(USB0_BASE_PTR)

#define	USB0_ISTAT USB_ISTAT_REG(USB0_BASE_PTR)

#define	USB0_INTEN USB_INTEN_REG(USB0_BASE_PTR)

#define	USB0_ERRSTAT USB_ERRSTAT_REG(USB0_BASE_PTR)

#define	USB0_ERREN USB_ERREN_REG(USB0_BASE_PTR)

#define	USB0_STAT USB_STAT_REG(USB0_BASE_PTR)

#define	USB0_CTL USB_CTL_REG(USB0_BASE_PTR)

#define	USB0_ADDR USB_ADDR_REG(USB0_BASE_PTR)

#define	USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0_BASE_PTR)

#define	USB0_FRMNUML USB_FRMNUML_REG(USB0_BASE_PTR)

#define	USB0_FRMNUMH USB_FRMNUMH_REG(USB0_BASE_PTR)

#define	USB0_TOKEN USB_TOKEN_REG(USB0_BASE_PTR)

#define	USB0_SOFTHLD USB_SOFTHLD_REG(USB0_BASE_PTR)

#define	USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0_BASE_PTR)

#define	USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0_BASE_PTR)

#define	USB0_ENDPT0 USB_ENDPT_REG(USB0_BASE_PTR,0)

#define	USB0_ENDPT1 USB_ENDPT_REG(USB0_BASE_PTR,1)

#define	USB0_ENDPT2 USB_ENDPT_REG(USB0_BASE_PTR,2)

#define	USB0_ENDPT3 USB_ENDPT_REG(USB0_BASE_PTR,3)

#define	USB0_ENDPT4 USB_ENDPT_REG(USB0_BASE_PTR,4)

#define	USB0_ENDPT5 USB_ENDPT_REG(USB0_BASE_PTR,5)

#define	USB0_ENDPT6 USB_ENDPT_REG(USB0_BASE_PTR,6)

#define	USB0_ENDPT7 USB_ENDPT_REG(USB0_BASE_PTR,7)

#define	USB0_ENDPT8 USB_ENDPT_REG(USB0_BASE_PTR,8)

#define	USB0_ENDPT9 USB_ENDPT_REG(USB0_BASE_PTR,9)

#define	USB0_ENDPT10 USB_ENDPT_REG(USB0_BASE_PTR,10)

#define	USB0_ENDPT11 USB_ENDPT_REG(USB0_BASE_PTR,11)

#define	USB0_ENDPT12 USB_ENDPT_REG(USB0_BASE_PTR,12)

#define	USB0_ENDPT13 USB_ENDPT_REG(USB0_BASE_PTR,13)

#define	USB0_ENDPT14 USB_ENDPT_REG(USB0_BASE_PTR,14)

#define	USB0_ENDPT15 USB_ENDPT_REG(USB0_BASE_PTR,15)

#define	USB0_USBCTRL USB_USBCTRL_REG(USB0_BASE_PTR)

#define	USB0_OBSERVE USB_OBSERVE_REG(USB0_BASE_PTR)

#define	USB0_CONTROL USB_CONTROL_REG(USB0_BASE_PTR)

#define	USB0_USBTRC0 USB_USBTRC0_REG(USB0_BASE_PTR)

#define	USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0_BASE_PTR)

#define	USB0_ENDPT(index) USB_ENDPT_REG(USB0_BASE_PTR,index)

#define	USBDCD_CONTROL_REG(base) ((base)->CONTROL)

#define	USBDCD_CLOCK_REG(base) ((base)->CLOCK)

#define	USBDCD_STATUS_REG(base) ((base)->STATUS)

#define	USBDCD_TIMER0_REG(base) ((base)->TIMER0)

#define	USBDCD_TIMER1_REG(base) ((base)->TIMER1)

#define	USBDCD_TIMER2_REG(base) ((base)->TIMER2)

#define	USBDCD_CONTROL_IACK_MASK 0x1u

#define	USBDCD_CONTROL_IACK_SHIFT 0

#define	USBDCD_CONTROL_IF_MASK 0x100u

#define	USBDCD_CONTROL_IF_SHIFT 8

#define	USBDCD_CONTROL_IE_MASK 0x10000u

#define	USBDCD_CONTROL_IE_SHIFT 16

#define	USBDCD_CONTROL_START_MASK 0x1000000u

#define	USBDCD_CONTROL_START_SHIFT 24

#define	USBDCD_CONTROL_SR_MASK 0x2000000u

#define	USBDCD_CONTROL_SR_SHIFT 25

#define	USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u

#define	USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0

#define	USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu

#define	USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2

#define	USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)

#define	USBDCD_STATUS_SEQ_RES_MASK 0x30000u

#define	USBDCD_STATUS_SEQ_RES_SHIFT 16

#define	USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)

#define	USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u

#define	USBDCD_STATUS_SEQ_STAT_SHIFT 18

#define	USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)

#define	USBDCD_STATUS_ERR_MASK 0x100000u

#define	USBDCD_STATUS_ERR_SHIFT 20

#define	USBDCD_STATUS_TO_MASK 0x200000u

#define	USBDCD_STATUS_TO_SHIFT 21

#define	USBDCD_STATUS_ACTIVE_MASK 0x400000u

#define	USBDCD_STATUS_ACTIVE_SHIFT 22

#define	USBDCD_TIMER0_TUNITCON_MASK 0xFFFu

#define	USBDCD_TIMER0_TUNITCON_SHIFT 0

#define	USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)

#define	USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u

#define	USBDCD_TIMER0_TSEQ_INIT_SHIFT 16

#define	USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)

#define	USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu

#define	USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0

#define	USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)

#define	USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u

#define	USBDCD_TIMER1_TDCD_DBNC_SHIFT 16

#define	USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)

#define	USBDCD_TIMER2_CHECK_DM_MASK 0xFu

#define	USBDCD_TIMER2_CHECK_DM_SHIFT 0

#define	USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)

#define	USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u

#define	USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16

#define	USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)

#define	USBDCD_BASE_PTR ((USBDCD_MemMapPtr)0x40035000u)

#define	USBDCD_BASE_PTRS { USBDCD_BASE_PTR }

#define	USBDCD_CONTROL USBDCD_CONTROL_REG(USBDCD_BASE_PTR)

#define	USBDCD_CLOCK USBDCD_CLOCK_REG(USBDCD_BASE_PTR)

#define	USBDCD_STATUS USBDCD_STATUS_REG(USBDCD_BASE_PTR)

#define	USBDCD_TIMER0 USBDCD_TIMER0_REG(USBDCD_BASE_PTR)

#define	USBDCD_TIMER1 USBDCD_TIMER1_REG(USBDCD_BASE_PTR)

#define	USBDCD_TIMER2 USBDCD_TIMER2_REG(USBDCD_BASE_PTR)

#define	USBHS_ID_REG(base) ((base)->ID)

#define	USBHS_HWGENERAL_REG(base) ((base)->HWGENERAL)

#define	USBHS_HWHOST_REG(base) ((base)->HWHOST)

#define	USBHS_HWDEVICE_REG(base) ((base)->HWDEVICE)

#define	USBHS_HWTXBUF_REG(base) ((base)->HWTXBUF)

#define	USBHS_HWRXBUF_REG(base) ((base)->HWRXBUF)

#define	USBHS_GPTIMER0LD_REG(base) ((base)->GPTIMER0LD)

#define	USBHS_GPTIMER0CTL_REG(base) ((base)->GPTIMER0CTL)

#define	USBHS_GPTIMER1LD_REG(base) ((base)->GPTIMER1LD)

#define	USBHS_GPTIMER1CTL_REG(base) ((base)->GPTIMER1CTL)

#define	USBHS_USB_SBUSCFG_REG(base) ((base)->USB_SBUSCFG)

#define	USBHS_HCIVERSION_REG(base) ((base)->HCIVERSION)

#define	USBHS_HCSPARAMS_REG(base) ((base)->HCSPARAMS)

#define	USBHS_HCCPARAMS_REG(base) ((base)->HCCPARAMS)

#define	USBHS_DCIVERSION_REG(base) ((base)->DCIVERSION)

#define	USBHS_DCCPARAMS_REG(base) ((base)->DCCPARAMS)

#define	USBHS_USBCMD_REG(base) ((base)->USBCMD)

#define	USBHS_USBSTS_REG(base) ((base)->USBSTS)

#define	USBHS_USBINTR_REG(base) ((base)->USBINTR)

#define	USBHS_FRINDEX_REG(base) ((base)->FRINDEX)

#define	USBHS_DEVICEADDR_REG(base) ((base)->DEVICEADDR)

#define	USBHS_PERIODICLISTBASE_REG(base) ((base)->PERIODICLISTBASE)

#define	USBHS_ASYNCLISTADDR_REG(base) ((base)->ASYNCLISTADDR)

#define	USBHS_EPLISTADDR_REG(base) ((base)->EPLISTADDR)

#define	USBHS_TTCTRL_REG(base) ((base)->TTCTRL)

#define	USBHS_BURSTSIZE_REG(base) ((base)->BURSTSIZE)

#define	USBHS_TXFILLTUNING_REG(base) ((base)->TXFILLTUNING)

#define	USBHS_ULPI_VIEWPORT_REG(base) ((base)->ULPI_VIEWPORT)

#define	USBHS_ENDPTNAK_REG(base) ((base)->ENDPTNAK)

#define	USBHS_ENDPTNAKEN_REG(base) ((base)->ENDPTNAKEN)

#define	USBHS_CONFIGFLAG_REG(base) ((base)->CONFIGFLAG)

#define	USBHS_PORTSC1_REG(base) ((base)->PORTSC1)

#define	USBHS_OTGSC_REG(base) ((base)->OTGSC)

#define	USBHS_USBMODE_REG(base) ((base)->USBMODE)

#define	USBHS_EPSETUPSR_REG(base) ((base)->EPSETUPSR)

#define	USBHS_EPPRIME_REG(base) ((base)->EPPRIME)

#define	USBHS_EPFLUSH_REG(base) ((base)->EPFLUSH)

#define	USBHS_EPSR_REG(base) ((base)->EPSR)

#define	USBHS_EPCOMPLETE_REG(base) ((base)->EPCOMPLETE)

#define	USBHS_EPCR0_REG(base) ((base)->EPCR0)

#define	USBHS_EPCR_REG(base, index) ((base)->EPCR[index])

#define	USBHS_USBGENCTRL_REG(base) ((base)->USBGENCTRL)

#define	USBHS_ID_ID_MASK 0x3Fu

#define	USBHS_ID_ID_SHIFT 0

#define	USBHS_ID_ID(x) (((uint32_t)(((uint32_t)(x))<<USBHS_ID_ID_SHIFT))&USBHS_ID_ID_MASK)

#define	USBHS_ID_NID_MASK 0x3F00u

#define	USBHS_ID_NID_SHIFT 8

#define	USBHS_ID_NID(x) (((uint32_t)(((uint32_t)(x))<<USBHS_ID_NID_SHIFT))&USBHS_ID_NID_MASK)

#define	USBHS_ID_TAG_MASK 0x1F0000u

#define	USBHS_ID_TAG_SHIFT 16

#define	USBHS_ID_TAG(x) (((uint32_t)(((uint32_t)(x))<<USBHS_ID_TAG_SHIFT))&USBHS_ID_TAG_MASK)

#define	USBHS_ID_REVISION_MASK 0x1E00000u

#define	USBHS_ID_REVISION_SHIFT 21

#define	USBHS_ID_REVISION(x) (((uint32_t)(((uint32_t)(x))<<USBHS_ID_REVISION_SHIFT))&USBHS_ID_REVISION_MASK)

#define	USBHS_ID_VERSION_MASK 0x1E000000u

#define	USBHS_ID_VERSION_SHIFT 25

#define	USBHS_ID_VERSION(x) (((uint32_t)(((uint32_t)(x))<<USBHS_ID_VERSION_SHIFT))&USBHS_ID_VERSION_MASK)

#define	USBHS_ID_VERSIONID_MASK 0xE0000000u

#define	USBHS_ID_VERSIONID_SHIFT 29

#define	USBHS_ID_VERSIONID(x) (((uint32_t)(((uint32_t)(x))<<USBHS_ID_VERSIONID_SHIFT))&USBHS_ID_VERSIONID_MASK)

#define	USBHS_HWGENERAL_PHYM_MASK 0x1C0u

#define	USBHS_HWGENERAL_PHYM_SHIFT 6

#define	USBHS_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HWGENERAL_PHYM_SHIFT))&USBHS_HWGENERAL_PHYM_MASK)

#define	USBHS_HWGENERAL_SM_MASK 0x600u

#define	USBHS_HWGENERAL_SM_SHIFT 9

#define	USBHS_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HWGENERAL_SM_SHIFT))&USBHS_HWGENERAL_SM_MASK)

#define	USBHS_HWHOST_HC_MASK 0x1u

#define	USBHS_HWHOST_HC_SHIFT 0

#define	USBHS_HWHOST_NPORT_MASK 0xEu

#define	USBHS_HWHOST_NPORT_SHIFT 1

#define	USBHS_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HWHOST_NPORT_SHIFT))&USBHS_HWHOST_NPORT_MASK)

#define	USBHS_HWHOST_TTASY_MASK 0xFF0000u

#define	USBHS_HWHOST_TTASY_SHIFT 16

#define	USBHS_HWHOST_TTASY(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HWHOST_TTASY_SHIFT))&USBHS_HWHOST_TTASY_MASK)

#define	USBHS_HWHOST_TTPER_MASK 0xFF000000u

#define	USBHS_HWHOST_TTPER_SHIFT 24

#define	USBHS_HWHOST_TTPER(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HWHOST_TTPER_SHIFT))&USBHS_HWHOST_TTPER_MASK)

#define	USBHS_HWDEVICE_DC_MASK 0x1u

#define	USBHS_HWDEVICE_DC_SHIFT 0

#define	USBHS_HWDEVICE_DEVEP_MASK 0x3Eu

#define	USBHS_HWDEVICE_DEVEP_SHIFT 1

#define	USBHS_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HWDEVICE_DEVEP_SHIFT))&USBHS_HWDEVICE_DEVEP_MASK)

#define	USBHS_HWTXBUF_TXBURST_MASK 0xFFu

#define	USBHS_HWTXBUF_TXBURST_SHIFT 0

#define	USBHS_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HWTXBUF_TXBURST_SHIFT))&USBHS_HWTXBUF_TXBURST_MASK)

#define	USBHS_HWTXBUF_TXADD_MASK 0xFF00u

#define	USBHS_HWTXBUF_TXADD_SHIFT 8

#define	USBHS_HWTXBUF_TXADD(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HWTXBUF_TXADD_SHIFT))&USBHS_HWTXBUF_TXADD_MASK)

#define	USBHS_HWTXBUF_TXCHANADD_MASK 0xFF0000u

#define	USBHS_HWTXBUF_TXCHANADD_SHIFT 16

#define	USBHS_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HWTXBUF_TXCHANADD_SHIFT))&USBHS_HWTXBUF_TXCHANADD_MASK)

#define	USBHS_HWTXBUF_TXLC_MASK 0x80000000u

#define	USBHS_HWTXBUF_TXLC_SHIFT 31

#define	USBHS_HWRXBUF_RXBURST_MASK 0xFFu

#define	USBHS_HWRXBUF_RXBURST_SHIFT 0

#define	USBHS_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HWRXBUF_RXBURST_SHIFT))&USBHS_HWRXBUF_RXBURST_MASK)

#define	USBHS_HWRXBUF_RXADD_MASK 0xFF00u

#define	USBHS_HWRXBUF_RXADD_SHIFT 8

#define	USBHS_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HWRXBUF_RXADD_SHIFT))&USBHS_HWRXBUF_RXADD_MASK)

#define	USBHS_GPTIMER0LD_GPTLD_MASK 0xFFFFFFu

#define	USBHS_GPTIMER0LD_GPTLD_SHIFT 0

#define	USBHS_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x))<<USBHS_GPTIMER0LD_GPTLD_SHIFT))&USBHS_GPTIMER0LD_GPTLD_MASK)

#define	USBHS_GPTIMER0CTL_GPTCNT_MASK 0xFFFFFFu

#define	USBHS_GPTIMER0CTL_GPTCNT_SHIFT 0

#define	USBHS_GPTIMER0CTL_GPTCNT(x) (((uint32_t)(((uint32_t)(x))<<USBHS_GPTIMER0CTL_GPTCNT_SHIFT))&USBHS_GPTIMER0CTL_GPTCNT_MASK)

#define	USBHS_GPTIMER0CTL_MODE_MASK 0x1000000u

#define	USBHS_GPTIMER0CTL_MODE_SHIFT 24

#define	USBHS_GPTIMER0CTL_RST_MASK 0x40000000u

#define	USBHS_GPTIMER0CTL_RST_SHIFT 30

#define	USBHS_GPTIMER0CTL_RUN_MASK 0x80000000u

#define	USBHS_GPTIMER0CTL_RUN_SHIFT 31

#define	USBHS_GPTIMER1LD_GPTLD_MASK 0xFFFFFFu

#define	USBHS_GPTIMER1LD_GPTLD_SHIFT 0

#define	USBHS_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x))<<USBHS_GPTIMER1LD_GPTLD_SHIFT))&USBHS_GPTIMER1LD_GPTLD_MASK)

#define	USBHS_GPTIMER1CTL_GPTCNT_MASK 0xFFFFFFu

#define	USBHS_GPTIMER1CTL_GPTCNT_SHIFT 0

#define	USBHS_GPTIMER1CTL_GPTCNT(x) (((uint32_t)(((uint32_t)(x))<<USBHS_GPTIMER1CTL_GPTCNT_SHIFT))&USBHS_GPTIMER1CTL_GPTCNT_MASK)

#define	USBHS_GPTIMER1CTL_MODE_MASK 0x1000000u

#define	USBHS_GPTIMER1CTL_MODE_SHIFT 24

#define	USBHS_GPTIMER1CTL_RST_MASK 0x40000000u

#define	USBHS_GPTIMER1CTL_RST_SHIFT 30

#define	USBHS_GPTIMER1CTL_RUN_MASK 0x80000000u

#define	USBHS_GPTIMER1CTL_RUN_SHIFT 31

#define	USBHS_USB_SBUSCFG_BURSTMODE_MASK 0x7u

#define	USBHS_USB_SBUSCFG_BURSTMODE_SHIFT 0

#define	USBHS_USB_SBUSCFG_BURSTMODE(x) (((uint32_t)(((uint32_t)(x))<<USBHS_USB_SBUSCFG_BURSTMODE_SHIFT))&USBHS_USB_SBUSCFG_BURSTMODE_MASK)

#define	USBHS_HCIVERSION_CAPLENGTH_MASK 0xFFu

#define	USBHS_HCIVERSION_CAPLENGTH_SHIFT 0

#define	USBHS_HCIVERSION_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HCIVERSION_CAPLENGTH_SHIFT))&USBHS_HCIVERSION_CAPLENGTH_MASK)

#define	USBHS_HCIVERSION_HCIVERSION_MASK 0xFFFF0000u

#define	USBHS_HCIVERSION_HCIVERSION_SHIFT 16

#define	USBHS_HCIVERSION_HCIVERSION(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HCIVERSION_HCIVERSION_SHIFT))&USBHS_HCIVERSION_HCIVERSION_MASK)

#define	USBHS_HCSPARAMS_N_PORTS_MASK 0xFu

#define	USBHS_HCSPARAMS_N_PORTS_SHIFT 0

#define	USBHS_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HCSPARAMS_N_PORTS_SHIFT))&USBHS_HCSPARAMS_N_PORTS_MASK)

#define	USBHS_HCSPARAMS_PPC_MASK 0x10u

#define	USBHS_HCSPARAMS_PPC_SHIFT 4

#define	USBHS_HCSPARAMS_N_PCC_MASK 0xF00u

#define	USBHS_HCSPARAMS_N_PCC_SHIFT 8

#define	USBHS_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HCSPARAMS_N_PCC_SHIFT))&USBHS_HCSPARAMS_N_PCC_MASK)

#define	USBHS_HCSPARAMS_N_CC_MASK 0xF000u

#define	USBHS_HCSPARAMS_N_CC_SHIFT 12

#define	USBHS_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HCSPARAMS_N_CC_SHIFT))&USBHS_HCSPARAMS_N_CC_MASK)

#define	USBHS_HCSPARAMS_PI_MASK 0x10000u

#define	USBHS_HCSPARAMS_PI_SHIFT 16

#define	USBHS_HCSPARAMS_N_PTT_MASK 0xF00000u

#define	USBHS_HCSPARAMS_N_PTT_SHIFT 20

#define	USBHS_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HCSPARAMS_N_PTT_SHIFT))&USBHS_HCSPARAMS_N_PTT_MASK)

#define	USBHS_HCSPARAMS_N_TT_MASK 0xF000000u

#define	USBHS_HCSPARAMS_N_TT_SHIFT 24

#define	USBHS_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HCSPARAMS_N_TT_SHIFT))&USBHS_HCSPARAMS_N_TT_MASK)

#define	USBHS_HCCPARAMS_ADC_MASK 0x1u

#define	USBHS_HCCPARAMS_ADC_SHIFT 0

#define	USBHS_HCCPARAMS_PFL_MASK 0x2u

#define	USBHS_HCCPARAMS_PFL_SHIFT 1

#define	USBHS_HCCPARAMS_ASP_MASK 0x4u

#define	USBHS_HCCPARAMS_ASP_SHIFT 2

#define	USBHS_HCCPARAMS_IST_MASK 0xF0u

#define	USBHS_HCCPARAMS_IST_SHIFT 4

#define	USBHS_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HCCPARAMS_IST_SHIFT))&USBHS_HCCPARAMS_IST_MASK)

#define	USBHS_HCCPARAMS_EECP_MASK 0xFF00u

#define	USBHS_HCCPARAMS_EECP_SHIFT 8

#define	USBHS_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x))<<USBHS_HCCPARAMS_EECP_SHIFT))&USBHS_HCCPARAMS_EECP_MASK)

#define	USBHS_DCIVERSION_DCIVERSION_MASK 0xFFFFu

#define	USBHS_DCIVERSION_DCIVERSION_SHIFT 0

#define	USBHS_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x))<<USBHS_DCIVERSION_DCIVERSION_SHIFT))&USBHS_DCIVERSION_DCIVERSION_MASK)

#define	USBHS_DCCPARAMS_DEN_MASK 0x1Fu

#define	USBHS_DCCPARAMS_DEN_SHIFT 0

#define	USBHS_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x))<<USBHS_DCCPARAMS_DEN_SHIFT))&USBHS_DCCPARAMS_DEN_MASK)

#define	USBHS_DCCPARAMS_DC_MASK 0x80u

#define	USBHS_DCCPARAMS_DC_SHIFT 7

#define	USBHS_DCCPARAMS_HC_MASK 0x100u

#define	USBHS_DCCPARAMS_HC_SHIFT 8

#define	USBHS_USBCMD_RS_MASK 0x1u

#define	USBHS_USBCMD_RS_SHIFT 0

#define	USBHS_USBCMD_RST_MASK 0x2u

#define	USBHS_USBCMD_RST_SHIFT 1

#define	USBHS_USBCMD_FS_MASK 0xCu

#define	USBHS_USBCMD_FS_SHIFT 2

#define	USBHS_USBCMD_FS(x) (((uint32_t)(((uint32_t)(x))<<USBHS_USBCMD_FS_SHIFT))&USBHS_USBCMD_FS_MASK)

#define	USBHS_USBCMD_PSE_MASK 0x10u

#define	USBHS_USBCMD_PSE_SHIFT 4

#define	USBHS_USBCMD_ASE_MASK 0x20u

#define	USBHS_USBCMD_ASE_SHIFT 5

#define	USBHS_USBCMD_IAA_MASK 0x40u

#define	USBHS_USBCMD_IAA_SHIFT 6

#define	USBHS_USBCMD_ASP_MASK 0x300u

#define	USBHS_USBCMD_ASP_SHIFT 8

#define	USBHS_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x))<<USBHS_USBCMD_ASP_SHIFT))&USBHS_USBCMD_ASP_MASK)

#define	USBHS_USBCMD_ASPE_MASK 0x800u

#define	USBHS_USBCMD_ASPE_SHIFT 11

#define	USBHS_USBCMD_SUTW_MASK 0x2000u

#define	USBHS_USBCMD_SUTW_SHIFT 13

#define	USBHS_USBCMD_ATDTW_MASK 0x4000u

#define	USBHS_USBCMD_ATDTW_SHIFT 14

#define	USBHS_USBCMD_FS2_MASK 0x8000u

#define	USBHS_USBCMD_FS2_SHIFT 15

#define	USBHS_USBCMD_ITC_MASK 0xFF0000u

#define	USBHS_USBCMD_ITC_SHIFT 16

#define	USBHS_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x))<<USBHS_USBCMD_ITC_SHIFT))&USBHS_USBCMD_ITC_MASK)

#define	USBHS_USBSTS_UI_MASK 0x1u

#define	USBHS_USBSTS_UI_SHIFT 0

#define	USBHS_USBSTS_UEI_MASK 0x2u

#define	USBHS_USBSTS_UEI_SHIFT 1

#define	USBHS_USBSTS_PCI_MASK 0x4u

#define	USBHS_USBSTS_PCI_SHIFT 2

#define	USBHS_USBSTS_FRI_MASK 0x8u

#define	USBHS_USBSTS_FRI_SHIFT 3

#define	USBHS_USBSTS_SEI_MASK 0x10u

#define	USBHS_USBSTS_SEI_SHIFT 4

#define	USBHS_USBSTS_AAI_MASK 0x20u

#define	USBHS_USBSTS_AAI_SHIFT 5

#define	USBHS_USBSTS_URI_MASK 0x40u

#define	USBHS_USBSTS_URI_SHIFT 6

#define	USBHS_USBSTS_SRI_MASK 0x80u

#define	USBHS_USBSTS_SRI_SHIFT 7

#define	USBHS_USBSTS_SLI_MASK 0x100u

#define	USBHS_USBSTS_SLI_SHIFT 8

#define	USBHS_USBSTS_ULPII_MASK 0x400u

#define	USBHS_USBSTS_ULPII_SHIFT 10

#define	USBHS_USBSTS_HCH_MASK 0x1000u

#define	USBHS_USBSTS_HCH_SHIFT 12

#define	USBHS_USBSTS_RCL_MASK 0x2000u

#define	USBHS_USBSTS_RCL_SHIFT 13

#define	USBHS_USBSTS_PS_MASK 0x4000u

#define	USBHS_USBSTS_PS_SHIFT 14

#define	USBHS_USBSTS_AS_MASK 0x8000u

#define	USBHS_USBSTS_AS_SHIFT 15

#define	USBHS_USBSTS_NAKI_MASK 0x10000u

#define	USBHS_USBSTS_NAKI_SHIFT 16

#define	USBHS_USBSTS_UAI_MASK 0x40000u

#define	USBHS_USBSTS_UAI_SHIFT 18

#define	USBHS_USBSTS_UPI_MASK 0x80000u

#define	USBHS_USBSTS_UPI_SHIFT 19

#define	USBHS_USBSTS_TI0_MASK 0x1000000u

#define	USBHS_USBSTS_TI0_SHIFT 24

#define	USBHS_USBSTS_TI1_MASK 0x2000000u

#define	USBHS_USBSTS_TI1_SHIFT 25

#define	USBHS_USBINTR_UE_MASK 0x1u

#define	USBHS_USBINTR_UE_SHIFT 0

#define	USBHS_USBINTR_UEE_MASK 0x2u

#define	USBHS_USBINTR_UEE_SHIFT 1

#define	USBHS_USBINTR_PCE_MASK 0x4u

#define	USBHS_USBINTR_PCE_SHIFT 2

#define	USBHS_USBINTR_FRE_MASK 0x8u

#define	USBHS_USBINTR_FRE_SHIFT 3

#define	USBHS_USBINTR_SEE_MASK 0x10u

#define	USBHS_USBINTR_SEE_SHIFT 4

#define	USBHS_USBINTR_AAE_MASK 0x20u

#define	USBHS_USBINTR_AAE_SHIFT 5

#define	USBHS_USBINTR_URE_MASK 0x40u

#define	USBHS_USBINTR_URE_SHIFT 6

#define	USBHS_USBINTR_SRE_MASK 0x80u

#define	USBHS_USBINTR_SRE_SHIFT 7

#define	USBHS_USBINTR_SLE_MASK 0x100u

#define	USBHS_USBINTR_SLE_SHIFT 8

#define	USBHS_USBINTR_ULPIE_MASK 0x400u

#define	USBHS_USBINTR_ULPIE_SHIFT 10

#define	USBHS_USBINTR_NAKE_MASK 0x10000u

#define	USBHS_USBINTR_NAKE_SHIFT 16

#define	USBHS_USBINTR_UAIE_MASK 0x40000u

#define	USBHS_USBINTR_UAIE_SHIFT 18

#define	USBHS_USBINTR_UPIE_MASK 0x80000u

#define	USBHS_USBINTR_UPIE_SHIFT 19

#define	USBHS_USBINTR_TIE0_MASK 0x1000000u

#define	USBHS_USBINTR_TIE0_SHIFT 24

#define	USBHS_USBINTR_TIE1_MASK 0x2000000u

#define	USBHS_USBINTR_TIE1_SHIFT 25

#define	USBHS_FRINDEX_FRINDEX_MASK 0x3FFFu

#define	USBHS_FRINDEX_FRINDEX_SHIFT 0

#define	USBHS_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x))<<USBHS_FRINDEX_FRINDEX_SHIFT))&USBHS_FRINDEX_FRINDEX_MASK)

#define	USBHS_FRINDEX_Reerved_MASK 0xFFFFC000u

#define	USBHS_FRINDEX_Reerved_SHIFT 14

#define	USBHS_FRINDEX_Reerved(x) (((uint32_t)(((uint32_t)(x))<<USBHS_FRINDEX_Reerved_SHIFT))&USBHS_FRINDEX_Reerved_MASK)

#define	USBHS_DEVICEADDR_USBADRA_MASK 0x1000000u

#define	USBHS_DEVICEADDR_USBADRA_SHIFT 24

#define	USBHS_DEVICEADDR_USBADR_MASK 0xFE000000u

#define	USBHS_DEVICEADDR_USBADR_SHIFT 25

#define	USBHS_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x))<<USBHS_DEVICEADDR_USBADR_SHIFT))&USBHS_DEVICEADDR_USBADR_MASK)

#define	USBHS_PERIODICLISTBASE_PERBASE_MASK 0xFFFFF000u

#define	USBHS_PERIODICLISTBASE_PERBASE_SHIFT 12

#define	USBHS_PERIODICLISTBASE_PERBASE(x) (((uint32_t)(((uint32_t)(x))<<USBHS_PERIODICLISTBASE_PERBASE_SHIFT))&USBHS_PERIODICLISTBASE_PERBASE_MASK)

#define	USBHS_ASYNCLISTADDR_ASYBASE_MASK 0xFFFFFFE0u

#define	USBHS_ASYNCLISTADDR_ASYBASE_SHIFT 5

#define	USBHS_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x))<<USBHS_ASYNCLISTADDR_ASYBASE_SHIFT))&USBHS_ASYNCLISTADDR_ASYBASE_MASK)

#define	USBHS_EPLISTADDR_EPBASE_MASK 0xFFFFF800u

#define	USBHS_EPLISTADDR_EPBASE_SHIFT 11

#define	USBHS_EPLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x))<<USBHS_EPLISTADDR_EPBASE_SHIFT))&USBHS_EPLISTADDR_EPBASE_MASK)

#define	USBHS_TTCTRL_TTHA_MASK 0x7F000000u

#define	USBHS_TTCTRL_TTHA_SHIFT 24

#define	USBHS_TTCTRL_TTHA(x) (((uint32_t)(((uint32_t)(x))<<USBHS_TTCTRL_TTHA_SHIFT))&USBHS_TTCTRL_TTHA_MASK)

#define	USBHS_TTCTRL_Reerved_MASK 0x80000000u

#define	USBHS_TTCTRL_Reerved_SHIFT 31

#define	USBHS_BURSTSIZE_RXPBURST_MASK 0xFFu

#define	USBHS_BURSTSIZE_RXPBURST_SHIFT 0

#define	USBHS_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x))<<USBHS_BURSTSIZE_RXPBURST_SHIFT))&USBHS_BURSTSIZE_RXPBURST_MASK)

#define	USBHS_BURSTSIZE_TXPBURST_MASK 0xFF00u

#define	USBHS_BURSTSIZE_TXPBURST_SHIFT 8

#define	USBHS_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x))<<USBHS_BURSTSIZE_TXPBURST_SHIFT))&USBHS_BURSTSIZE_TXPBURST_MASK)

#define	USBHS_TXFILLTUNING_TXSCHOH_MASK 0x7Fu

#define	USBHS_TXFILLTUNING_TXSCHOH_SHIFT 0

#define	USBHS_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x))<<USBHS_TXFILLTUNING_TXSCHOH_SHIFT))&USBHS_TXFILLTUNING_TXSCHOH_MASK)

#define	USBHS_TXFILLTUNING_TXSCHHEALTH_MASK 0x1F00u

#define	USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT 8

#define	USBHS_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x))<<USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT))&USBHS_TXFILLTUNING_TXSCHHEALTH_MASK)

#define	USBHS_TXFILLTUNING_TXFIFOTHRES_MASK 0x3F0000u

#define	USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT 16

#define	USBHS_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x))<<USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT))&USBHS_TXFILLTUNING_TXFIFOTHRES_MASK)

#define	USBHS_ULPI_VIEWPORT_ULPI_DATWR_MASK 0xFFu

#define	USBHS_ULPI_VIEWPORT_ULPI_DATWR_SHIFT 0

#define	USBHS_ULPI_VIEWPORT_ULPI_DATWR(x) (((uint32_t)(((uint32_t)(x))<<USBHS_ULPI_VIEWPORT_ULPI_DATWR_SHIFT))&USBHS_ULPI_VIEWPORT_ULPI_DATWR_MASK)

#define	USBHS_ULPI_VIEWPORT_ULPI_DATRD_MASK 0xFF00u

#define	USBHS_ULPI_VIEWPORT_ULPI_DATRD_SHIFT 8

#define	USBHS_ULPI_VIEWPORT_ULPI_DATRD(x) (((uint32_t)(((uint32_t)(x))<<USBHS_ULPI_VIEWPORT_ULPI_DATRD_SHIFT))&USBHS_ULPI_VIEWPORT_ULPI_DATRD_MASK)

#define	USBHS_ULPI_VIEWPORT_ULPI_ADDR_MASK 0xFF0000u

#define	USBHS_ULPI_VIEWPORT_ULPI_ADDR_SHIFT 16

#define	USBHS_ULPI_VIEWPORT_ULPI_ADDR(x) (((uint32_t)(((uint32_t)(x))<<USBHS_ULPI_VIEWPORT_ULPI_ADDR_SHIFT))&USBHS_ULPI_VIEWPORT_ULPI_ADDR_MASK)

#define	USBHS_ULPI_VIEWPORT_ULPI_PORT_MASK 0x7000000u

#define	USBHS_ULPI_VIEWPORT_ULPI_PORT_SHIFT 24

#define	USBHS_ULPI_VIEWPORT_ULPI_PORT(x) (((uint32_t)(((uint32_t)(x))<<USBHS_ULPI_VIEWPORT_ULPI_PORT_SHIFT))&USBHS_ULPI_VIEWPORT_ULPI_PORT_MASK)

#define	USBHS_ULPI_VIEWPORT_ULPI_SS_MASK 0x8000000u

#define	USBHS_ULPI_VIEWPORT_ULPI_SS_SHIFT 27

#define	USBHS_ULPI_VIEWPORT_ULPI_RW_MASK 0x20000000u

#define	USBHS_ULPI_VIEWPORT_ULPI_RW_SHIFT 29

#define	USBHS_ULPI_VIEWPORT_ULPI_RUN_MASK 0x40000000u

#define	USBHS_ULPI_VIEWPORT_ULPI_RUN_SHIFT 30

#define	USBHS_ULPI_VIEWPORT_ULPI_WU_MASK 0x80000000u

#define	USBHS_ULPI_VIEWPORT_ULPI_WU_SHIFT 31

#define	USBHS_ENDPTNAK_EPRN_MASK 0xFu

#define	USBHS_ENDPTNAK_EPRN_SHIFT 0

#define	USBHS_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x))<<USBHS_ENDPTNAK_EPRN_SHIFT))&USBHS_ENDPTNAK_EPRN_MASK)

#define	USBHS_ENDPTNAK_EPTN_MASK 0xF0000u

#define	USBHS_ENDPTNAK_EPTN_SHIFT 16

#define	USBHS_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x))<<USBHS_ENDPTNAK_EPTN_SHIFT))&USBHS_ENDPTNAK_EPTN_MASK)

#define	USBHS_ENDPTNAKEN_EPRNE_MASK 0xFu

#define	USBHS_ENDPTNAKEN_EPRNE_SHIFT 0

#define	USBHS_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x))<<USBHS_ENDPTNAKEN_EPRNE_SHIFT))&USBHS_ENDPTNAKEN_EPRNE_MASK)

#define	USBHS_ENDPTNAKEN_EPTNE_MASK 0xF0000u

#define	USBHS_ENDPTNAKEN_EPTNE_SHIFT 16

#define	USBHS_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x))<<USBHS_ENDPTNAKEN_EPTNE_SHIFT))&USBHS_ENDPTNAKEN_EPTNE_MASK)

#define	USBHS_PORTSC1_CCS_MASK 0x1u

#define	USBHS_PORTSC1_CCS_SHIFT 0

#define	USBHS_PORTSC1_CSC_MASK 0x2u

#define	USBHS_PORTSC1_CSC_SHIFT 1

#define	USBHS_PORTSC1_PE_MASK 0x4u

#define	USBHS_PORTSC1_PE_SHIFT 2

#define	USBHS_PORTSC1_PEC_MASK 0x8u

#define	USBHS_PORTSC1_PEC_SHIFT 3

#define	USBHS_PORTSC1_OCA_MASK 0x10u

#define	USBHS_PORTSC1_OCA_SHIFT 4

#define	USBHS_PORTSC1_OCC_MASK 0x20u

#define	USBHS_PORTSC1_OCC_SHIFT 5

#define	USBHS_PORTSC1_FPR_MASK 0x40u

#define	USBHS_PORTSC1_FPR_SHIFT 6

#define	USBHS_PORTSC1_SUSP_MASK 0x80u

#define	USBHS_PORTSC1_SUSP_SHIFT 7

#define	USBHS_PORTSC1_PR_MASK 0x100u

#define	USBHS_PORTSC1_PR_SHIFT 8

#define	USBHS_PORTSC1_HSP_MASK 0x200u

#define	USBHS_PORTSC1_HSP_SHIFT 9

#define	USBHS_PORTSC1_LS_MASK 0xC00u

#define	USBHS_PORTSC1_LS_SHIFT 10

#define	USBHS_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x))<<USBHS_PORTSC1_LS_SHIFT))&USBHS_PORTSC1_LS_MASK)

#define	USBHS_PORTSC1_PP_MASK 0x1000u

#define	USBHS_PORTSC1_PP_SHIFT 12

#define	USBHS_PORTSC1_PO_MASK 0x2000u

#define	USBHS_PORTSC1_PO_SHIFT 13

#define	USBHS_PORTSC1_PIC_MASK 0xC000u

#define	USBHS_PORTSC1_PIC_SHIFT 14

#define	USBHS_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x))<<USBHS_PORTSC1_PIC_SHIFT))&USBHS_PORTSC1_PIC_MASK)

#define	USBHS_PORTSC1_PTC_MASK 0xF0000u

#define	USBHS_PORTSC1_PTC_SHIFT 16

#define	USBHS_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x))<<USBHS_PORTSC1_PTC_SHIFT))&USBHS_PORTSC1_PTC_MASK)

#define	USBHS_PORTSC1_WKCN_MASK 0x100000u

#define	USBHS_PORTSC1_WKCN_SHIFT 20

#define	USBHS_PORTSC1_WKDS_MASK 0x200000u

#define	USBHS_PORTSC1_WKDS_SHIFT 21

#define	USBHS_PORTSC1_WKOC_MASK 0x400000u

#define	USBHS_PORTSC1_WKOC_SHIFT 22

#define	USBHS_PORTSC1_PHCD_MASK 0x800000u

#define	USBHS_PORTSC1_PHCD_SHIFT 23

#define	USBHS_PORTSC1_PFSC_MASK 0x1000000u

#define	USBHS_PORTSC1_PFSC_SHIFT 24

#define	USBHS_PORTSC1_PSPD_MASK 0xC000000u

#define	USBHS_PORTSC1_PSPD_SHIFT 26

#define	USBHS_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x))<<USBHS_PORTSC1_PSPD_SHIFT))&USBHS_PORTSC1_PSPD_MASK)

#define	USBHS_PORTSC1_PTS_MASK 0xC0000000u

#define	USBHS_PORTSC1_PTS_SHIFT 30

#define	USBHS_PORTSC1_PTS(x) (((uint32_t)(((uint32_t)(x))<<USBHS_PORTSC1_PTS_SHIFT))&USBHS_PORTSC1_PTS_MASK)

#define	USBHS_OTGSC_VD_MASK 0x1u

#define	USBHS_OTGSC_VD_SHIFT 0

#define	USBHS_OTGSC_VC_MASK 0x2u

#define	USBHS_OTGSC_VC_SHIFT 1

#define	USBHS_OTGSC_HAAR_MASK 0x4u

#define	USBHS_OTGSC_HAAR_SHIFT 2

#define	USBHS_OTGSC_OT_MASK 0x8u

#define	USBHS_OTGSC_OT_SHIFT 3

#define	USBHS_OTGSC_DP_MASK 0x10u

#define	USBHS_OTGSC_DP_SHIFT 4

#define	USBHS_OTGSC_IDPU_MASK 0x20u

#define	USBHS_OTGSC_IDPU_SHIFT 5

#define	USBHS_OTGSC_HABA_MASK 0x80u

#define	USBHS_OTGSC_HABA_SHIFT 7

#define	USBHS_OTGSC_ID_MASK 0x100u

#define	USBHS_OTGSC_ID_SHIFT 8

#define	USBHS_OTGSC_AVV_MASK 0x200u

#define	USBHS_OTGSC_AVV_SHIFT 9

#define	USBHS_OTGSC_ASV_MASK 0x400u

#define	USBHS_OTGSC_ASV_SHIFT 10

#define	USBHS_OTGSC_BSV_MASK 0x800u

#define	USBHS_OTGSC_BSV_SHIFT 11

#define	USBHS_OTGSC_BSE_MASK 0x1000u

#define	USBHS_OTGSC_BSE_SHIFT 12

#define	USBHS_OTGSC_MST_MASK 0x2000u

#define	USBHS_OTGSC_MST_SHIFT 13

#define	USBHS_OTGSC_DPS_MASK 0x4000u

#define	USBHS_OTGSC_DPS_SHIFT 14

#define	USBHS_OTGSC_IDIS_MASK 0x10000u

#define	USBHS_OTGSC_IDIS_SHIFT 16

#define	USBHS_OTGSC_AVVIS_MASK 0x20000u

#define	USBHS_OTGSC_AVVIS_SHIFT 17

#define	USBHS_OTGSC_ASVIS_MASK 0x40000u

#define	USBHS_OTGSC_ASVIS_SHIFT 18

#define	USBHS_OTGSC_BSVIS_MASK 0x80000u

#define	USBHS_OTGSC_BSVIS_SHIFT 19

#define	USBHS_OTGSC_BSEIS_MASK 0x100000u

#define	USBHS_OTGSC_BSEIS_SHIFT 20

#define	USBHS_OTGSC_MSS_MASK 0x200000u

#define	USBHS_OTGSC_MSS_SHIFT 21

#define	USBHS_OTGSC_DPIS_MASK 0x400000u

#define	USBHS_OTGSC_DPIS_SHIFT 22

#define	USBHS_OTGSC_IDIE_MASK 0x1000000u

#define	USBHS_OTGSC_IDIE_SHIFT 24

#define	USBHS_OTGSC_AVVIE_MASK 0x2000000u

#define	USBHS_OTGSC_AVVIE_SHIFT 25

#define	USBHS_OTGSC_ASVIE_MASK 0x4000000u

#define	USBHS_OTGSC_ASVIE_SHIFT 26

#define	USBHS_OTGSC_BSVIE_MASK 0x8000000u

#define	USBHS_OTGSC_BSVIE_SHIFT 27

#define	USBHS_OTGSC_BSEIE_MASK 0x10000000u

#define	USBHS_OTGSC_BSEIE_SHIFT 28

#define	USBHS_OTGSC_MSE_MASK 0x20000000u

#define	USBHS_OTGSC_MSE_SHIFT 29

#define	USBHS_OTGSC_DPIE_MASK 0x40000000u

#define	USBHS_OTGSC_DPIE_SHIFT 30

#define	USBHS_USBMODE_CM_MASK 0x3u

#define	USBHS_USBMODE_CM_SHIFT 0

#define	USBHS_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x))<<USBHS_USBMODE_CM_SHIFT))&USBHS_USBMODE_CM_MASK)

#define	USBHS_USBMODE_ES_MASK 0x4u

#define	USBHS_USBMODE_ES_SHIFT 2

#define	USBHS_USBMODE_SLOM_MASK 0x8u

#define	USBHS_USBMODE_SLOM_SHIFT 3

#define	USBHS_USBMODE_SDIS_MASK 0x10u

#define	USBHS_USBMODE_SDIS_SHIFT 4

#define	USBHS_USBMODE_TXHSD_MASK 0x7000u

#define	USBHS_USBMODE_TXHSD_SHIFT 12

#define	USBHS_USBMODE_TXHSD(x) (((uint32_t)(((uint32_t)(x))<<USBHS_USBMODE_TXHSD_SHIFT))&USBHS_USBMODE_TXHSD_MASK)

#define	USBHS_EPSETUPSR_EPSETUPSTAT_MASK 0xFu

#define	USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT 0

#define	USBHS_EPSETUPSR_EPSETUPSTAT(x) (((uint32_t)(((uint32_t)(x))<<USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT))&USBHS_EPSETUPSR_EPSETUPSTAT_MASK)

#define	USBHS_EPPRIME_PERB_MASK 0xFu

#define	USBHS_EPPRIME_PERB_SHIFT 0

#define	USBHS_EPPRIME_PERB(x) (((uint32_t)(((uint32_t)(x))<<USBHS_EPPRIME_PERB_SHIFT))&USBHS_EPPRIME_PERB_MASK)

#define	USBHS_EPPRIME_PETB_MASK 0xF0000u

#define	USBHS_EPPRIME_PETB_SHIFT 16

#define	USBHS_EPPRIME_PETB(x) (((uint32_t)(((uint32_t)(x))<<USBHS_EPPRIME_PETB_SHIFT))&USBHS_EPPRIME_PETB_MASK)

#define	USBHS_EPFLUSH_FERB_MASK 0xFu

#define	USBHS_EPFLUSH_FERB_SHIFT 0

#define	USBHS_EPFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x))<<USBHS_EPFLUSH_FERB_SHIFT))&USBHS_EPFLUSH_FERB_MASK)

#define	USBHS_EPFLUSH_FETB_MASK 0xF0000u

#define	USBHS_EPFLUSH_FETB_SHIFT 16

#define	USBHS_EPFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x))<<USBHS_EPFLUSH_FETB_SHIFT))&USBHS_EPFLUSH_FETB_MASK)

#define	USBHS_EPSR_ERBR_MASK 0xFu

#define	USBHS_EPSR_ERBR_SHIFT 0

#define	USBHS_EPSR_ERBR(x) (((uint32_t)(((uint32_t)(x))<<USBHS_EPSR_ERBR_SHIFT))&USBHS_EPSR_ERBR_MASK)

#define	USBHS_EPSR_ETBR_MASK 0xF0000u

#define	USBHS_EPSR_ETBR_SHIFT 16

#define	USBHS_EPSR_ETBR(x) (((uint32_t)(((uint32_t)(x))<<USBHS_EPSR_ETBR_SHIFT))&USBHS_EPSR_ETBR_MASK)

#define	USBHS_EPCOMPLETE_ERCE_MASK 0xFu

#define	USBHS_EPCOMPLETE_ERCE_SHIFT 0

#define	USBHS_EPCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x))<<USBHS_EPCOMPLETE_ERCE_SHIFT))&USBHS_EPCOMPLETE_ERCE_MASK)

#define	USBHS_EPCOMPLETE_ETCE_MASK 0xF0000u

#define	USBHS_EPCOMPLETE_ETCE_SHIFT 16

#define	USBHS_EPCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x))<<USBHS_EPCOMPLETE_ETCE_SHIFT))&USBHS_EPCOMPLETE_ETCE_MASK)

#define	USBHS_EPCR0_RXS_MASK 0x1u

#define	USBHS_EPCR0_RXS_SHIFT 0

#define	USBHS_EPCR0_RXT_MASK 0xCu

#define	USBHS_EPCR0_RXT_SHIFT 2

#define	USBHS_EPCR0_RXT(x) (((uint32_t)(((uint32_t)(x))<<USBHS_EPCR0_RXT_SHIFT))&USBHS_EPCR0_RXT_MASK)

#define	USBHS_EPCR0_RXE_MASK 0x80u

#define	USBHS_EPCR0_RXE_SHIFT 7

#define	USBHS_EPCR0_TXS_MASK 0x10000u

#define	USBHS_EPCR0_TXS_SHIFT 16

#define	USBHS_EPCR0_TXT_MASK 0xC0000u

#define	USBHS_EPCR0_TXT_SHIFT 18

#define	USBHS_EPCR0_TXT(x) (((uint32_t)(((uint32_t)(x))<<USBHS_EPCR0_TXT_SHIFT))&USBHS_EPCR0_TXT_MASK)

#define	USBHS_EPCR0_TXE_MASK 0x800000u

#define	USBHS_EPCR0_TXE_SHIFT 23

#define	USBHS_EPCR_RXS_MASK 0x1u

#define	USBHS_EPCR_RXS_SHIFT 0

#define	USBHS_EPCR_RXD_MASK 0x2u

#define	USBHS_EPCR_RXD_SHIFT 1

#define	USBHS_EPCR_RXT_MASK 0xCu

#define	USBHS_EPCR_RXT_SHIFT 2

#define	USBHS_EPCR_RXT(x) (((uint32_t)(((uint32_t)(x))<<USBHS_EPCR_RXT_SHIFT))&USBHS_EPCR_RXT_MASK)

#define	USBHS_EPCR_RXI_MASK 0x20u

#define	USBHS_EPCR_RXI_SHIFT 5

#define	USBHS_EPCR_RXR_MASK 0x40u

#define	USBHS_EPCR_RXR_SHIFT 6

#define	USBHS_EPCR_RXE_MASK 0x80u

#define	USBHS_EPCR_RXE_SHIFT 7

#define	USBHS_EPCR_TXS_MASK 0x10000u

#define	USBHS_EPCR_TXS_SHIFT 16

#define	USBHS_EPCR_TXD_MASK 0x20000u

#define	USBHS_EPCR_TXD_SHIFT 17

#define	USBHS_EPCR_TXT_MASK 0xC0000u

#define	USBHS_EPCR_TXT_SHIFT 18

#define	USBHS_EPCR_TXT(x) (((uint32_t)(((uint32_t)(x))<<USBHS_EPCR_TXT_SHIFT))&USBHS_EPCR_TXT_MASK)

#define	USBHS_EPCR_TXI_MASK 0x200000u

#define	USBHS_EPCR_TXI_SHIFT 21

#define	USBHS_EPCR_TXR_MASK 0x400000u

#define	USBHS_EPCR_TXR_SHIFT 22

#define	USBHS_EPCR_TXE_MASK 0x800000u

#define	USBHS_EPCR_TXE_SHIFT 23

#define	USBHS_USBGENCTRL_WU_IE_MASK 0x1u

#define	USBHS_USBGENCTRL_WU_IE_SHIFT 0

#define	USBHS_USBGENCTRL_WU_ULPI_EN_MASK 0x2u

#define	USBHS_USBGENCTRL_WU_ULPI_EN_SHIFT 1

#define	USBHS_USBGENCTRL_WU_INT_CLR_MASK 0x20u

#define	USBHS_USBGENCTRL_WU_INT_CLR_SHIFT 5

#define	USBHS_BASE_PTR ((USBHS_MemMapPtr)0x40034000u)

#define	USBHS_BASE_PTRS { USBHS_BASE_PTR }

#define	USBHS_ID USBHS_ID_REG(USBHS_BASE_PTR)

#define	USBHS_HWGENERAL USBHS_HWGENERAL_REG(USBHS_BASE_PTR)

#define	USBHS_HWHOST USBHS_HWHOST_REG(USBHS_BASE_PTR)

#define	USBHS_HWDEVICE USBHS_HWDEVICE_REG(USBHS_BASE_PTR)

#define	USBHS_HWTXBUF USBHS_HWTXBUF_REG(USBHS_BASE_PTR)

#define	USBHS_HWRXBUF USBHS_HWRXBUF_REG(USBHS_BASE_PTR)

#define	USBHS_GPTIMER0LD USBHS_GPTIMER0LD_REG(USBHS_BASE_PTR)

#define	USBHS_GPTIMER0CTL USBHS_GPTIMER0CTL_REG(USBHS_BASE_PTR)

#define	USBHS_GPTIMER1LD USBHS_GPTIMER1LD_REG(USBHS_BASE_PTR)

#define	USBHS_GPTIMER1CTL USBHS_GPTIMER1CTL_REG(USBHS_BASE_PTR)

#define	USBHS_USB_SBUSCFG USBHS_USB_SBUSCFG_REG(USBHS_BASE_PTR)

#define	USBHS_HCIVERSION USBHS_HCIVERSION_REG(USBHS_BASE_PTR)

#define	USBHS_HCSPARAMS USBHS_HCSPARAMS_REG(USBHS_BASE_PTR)

#define	USBHS_HCCPARAMS USBHS_HCCPARAMS_REG(USBHS_BASE_PTR)

#define	USBHS_DCIVERSION USBHS_DCIVERSION_REG(USBHS_BASE_PTR)

#define	USBHS_DCCPARAMS USBHS_DCCPARAMS_REG(USBHS_BASE_PTR)

#define	USBHS_USBCMD USBHS_USBCMD_REG(USBHS_BASE_PTR)

#define	USBHS_USBSTS USBHS_USBSTS_REG(USBHS_BASE_PTR)

#define	USBHS_USBINTR USBHS_USBINTR_REG(USBHS_BASE_PTR)

#define	USBHS_FRINDEX USBHS_FRINDEX_REG(USBHS_BASE_PTR)

#define	USBHS_DEVICEADDR USBHS_DEVICEADDR_REG(USBHS_BASE_PTR)

#define	USBHS_PERIODICLISTBASE USBHS_PERIODICLISTBASE_REG(USBHS_BASE_PTR)

#define	USBHS_ASYNCLISTADDR USBHS_ASYNCLISTADDR_REG(USBHS_BASE_PTR)

#define	USBHS_EPLISTADDR USBHS_EPLISTADDR_REG(USBHS_BASE_PTR)

#define	USBHS_TTCTRL USBHS_TTCTRL_REG(USBHS_BASE_PTR)

#define	USBHS_BURSTSIZE USBHS_BURSTSIZE_REG(USBHS_BASE_PTR)

#define	USBHS_TXFILLTUNING USBHS_TXFILLTUNING_REG(USBHS_BASE_PTR)

#define	USBHS_ULPI_VIEWPORT USBHS_ULPI_VIEWPORT_REG(USBHS_BASE_PTR)

#define	USBHS_ENDPTNAK USBHS_ENDPTNAK_REG(USBHS_BASE_PTR)

#define	USBHS_ENDPTNAKEN USBHS_ENDPTNAKEN_REG(USBHS_BASE_PTR)

#define	USBHS_CONFIGFLAG USBHS_CONFIGFLAG_REG(USBHS_BASE_PTR)

#define	USBHS_PORTSC1 USBHS_PORTSC1_REG(USBHS_BASE_PTR)

#define	USBHS_OTGSC USBHS_OTGSC_REG(USBHS_BASE_PTR)

#define	USBHS_USBMODE USBHS_USBMODE_REG(USBHS_BASE_PTR)

#define	USBHS_EPSETUPSR USBHS_EPSETUPSR_REG(USBHS_BASE_PTR)

#define	USBHS_EPPRIME USBHS_EPPRIME_REG(USBHS_BASE_PTR)

#define	USBHS_EPFLUSH USBHS_EPFLUSH_REG(USBHS_BASE_PTR)

#define	USBHS_EPSR USBHS_EPSR_REG(USBHS_BASE_PTR)

#define	USBHS_EPCOMPLETE USBHS_EPCOMPLETE_REG(USBHS_BASE_PTR)

#define	USBHS_EPCR0 USBHS_EPCR0_REG(USBHS_BASE_PTR)

#define	USBHS_EPCR1 USBHS_EPCR_REG(USBHS_BASE_PTR,0)

#define	USBHS_EPCR2 USBHS_EPCR_REG(USBHS_BASE_PTR,1)

#define	USBHS_EPCR3 USBHS_EPCR_REG(USBHS_BASE_PTR,2)

#define	USBHS_USBGENCTRL USBHS_USBGENCTRL_REG(USBHS_BASE_PTR)

#define	USBHS_EPCR(index) USBHS_EPCR_REG(USBHS_BASE_PTR,index)

#define	VREF_TRM_REG(base) ((base)->TRM)

#define	VREF_SC_REG(base) ((base)->SC)

#define	VREF_TRM_TRIM_MASK 0x3Fu

#define	VREF_TRM_TRIM_SHIFT 0

#define	VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)

#define	VREF_SC_MODE_LV_MASK 0x3u

#define	VREF_SC_MODE_LV_SHIFT 0

#define	VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)

#define	VREF_SC_VREFST_MASK 0x4u

#define	VREF_SC_VREFST_SHIFT 2

#define	VREF_SC_REGEN_MASK 0x40u

#define	VREF_SC_REGEN_SHIFT 6

#define	VREF_SC_VREFEN_MASK 0x80u

#define	VREF_SC_VREFEN_SHIFT 7

#define	VREF_BASE_PTR ((VREF_MemMapPtr)0x40074000u)

#define	VREF_BASE_PTRS { VREF_BASE_PTR }

#define	VREF_TRM VREF_TRM_REG(VREF_BASE_PTR)

#define	VREF_SC VREF_SC_REG(VREF_BASE_PTR)

#define	WDOG_STCTRLH_REG(base) ((base)->STCTRLH)

#define	WDOG_STCTRLL_REG(base) ((base)->STCTRLL)

#define	WDOG_TOVALH_REG(base) ((base)->TOVALH)

#define	WDOG_TOVALL_REG(base) ((base)->TOVALL)

#define	WDOG_WINH_REG(base) ((base)->WINH)

#define	WDOG_WINL_REG(base) ((base)->WINL)

#define	WDOG_REFRESH_REG(base) ((base)->REFRESH)

#define	WDOG_UNLOCK_REG(base) ((base)->UNLOCK)

#define	WDOG_TMROUTH_REG(base) ((base)->TMROUTH)

#define	WDOG_TMROUTL_REG(base) ((base)->TMROUTL)

#define	WDOG_RSTCNT_REG(base) ((base)->RSTCNT)

#define	WDOG_PRESC_REG(base) ((base)->PRESC)

#define	WDOG_STCTRLH_WDOGEN_MASK 0x1u

#define	WDOG_STCTRLH_WDOGEN_SHIFT 0

#define	WDOG_STCTRLH_CLKSRC_MASK 0x2u

#define	WDOG_STCTRLH_CLKSRC_SHIFT 1

#define	WDOG_STCTRLH_IRQRSTEN_MASK 0x4u

#define	WDOG_STCTRLH_IRQRSTEN_SHIFT 2

#define	WDOG_STCTRLH_WINEN_MASK 0x8u

#define	WDOG_STCTRLH_WINEN_SHIFT 3

#define	WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u

#define	WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4

#define	WDOG_STCTRLH_DBGEN_MASK 0x20u

#define	WDOG_STCTRLH_DBGEN_SHIFT 5

#define	WDOG_STCTRLH_STOPEN_MASK 0x40u

#define	WDOG_STCTRLH_STOPEN_SHIFT 6

#define	WDOG_STCTRLH_WAITEN_MASK 0x80u

#define	WDOG_STCTRLH_WAITEN_SHIFT 7

#define	WDOG_STCTRLH_TESTWDOG_MASK 0x400u

#define	WDOG_STCTRLH_TESTWDOG_SHIFT 10

#define	WDOG_STCTRLH_TESTSEL_MASK 0x800u

#define	WDOG_STCTRLH_TESTSEL_SHIFT 11

#define	WDOG_STCTRLH_BYTESEL_MASK 0x3000u

#define	WDOG_STCTRLH_BYTESEL_SHIFT 12

#define	WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)

#define	WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u

#define	WDOG_STCTRLH_DISTESTWDOG_SHIFT 14

#define	WDOG_STCTRLL_INTFLG_MASK 0x8000u

#define	WDOG_STCTRLL_INTFLG_SHIFT 15

#define	WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu

#define	WDOG_TOVALH_TOVALHIGH_SHIFT 0

#define	WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)

#define	WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu

#define	WDOG_TOVALL_TOVALLOW_SHIFT 0

#define	WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)

#define	WDOG_WINH_WINHIGH_MASK 0xFFFFu

#define	WDOG_WINH_WINHIGH_SHIFT 0

#define	WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)

#define	WDOG_WINL_WINLOW_MASK 0xFFFFu

#define	WDOG_WINL_WINLOW_SHIFT 0

#define	WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)

#define	WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu

#define	WDOG_REFRESH_WDOGREFRESH_SHIFT 0

#define	WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)

#define	WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu

#define	WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0

#define	WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)

#define	WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu

#define	WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0

#define	WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)

#define	WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu

#define	WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0

#define	WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)

#define	WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu

#define	WDOG_RSTCNT_RSTCNT_SHIFT 0

#define	WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)

#define	WDOG_PRESC_PRESCVAL_MASK 0x700u

#define	WDOG_PRESC_PRESCVAL_SHIFT 8

#define	WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)

#define	WDOG_BASE_PTR ((WDOG_MemMapPtr)0x40052000u)

#define	WDOG_BASE_PTRS { WDOG_BASE_PTR }

#define	WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG_BASE_PTR)

#define	WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG_BASE_PTR)

#define	WDOG_TOVALH WDOG_TOVALH_REG(WDOG_BASE_PTR)

#define	WDOG_TOVALL WDOG_TOVALL_REG(WDOG_BASE_PTR)

#define	WDOG_WINH WDOG_WINH_REG(WDOG_BASE_PTR)

#define	WDOG_WINL WDOG_WINL_REG(WDOG_BASE_PTR)

#define	WDOG_REFRESH WDOG_REFRESH_REG(WDOG_BASE_PTR)

#define	WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG_BASE_PTR)

#define	WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG_BASE_PTR)

#define	WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG_BASE_PTR)

#define	WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG_BASE_PTR)

#define	WDOG_PRESC WDOG_PRESC_REG(WDOG_BASE_PTR)

#define	PDB0_PO0EN PDB0_POEN

#define	PMC_REGSC_BGEN_MASK 0x10u

#define	PMC_REGSC_BGEN_SHIFT 4

#define	SIM_SCGC4_IIC2_MASK SIM_SCGC4_IIC0_MASK

#define	SIM_SCGC4_IIC2_SHIFT SIM_SCGC4_IIC0_SHIFT

#define	SIM_SCGC6_FTFE_MASK 0x1u

#define	SIM_SCGC6_FTFE_SHIFT 0

#define	SIM_SCGC7_PFLEXNVM_MASK 0x4u

#define	SIM_SCGC7_PFLEXNVM_SHIFT 2

#define	LCDC_LSR_GWLPM_MASK 0x10000000u

#define	LCDC_LSR_GWLPM_SHIFT 28

#define	LCDC_LIER_ERR_RES_EN_MASK 0x4u

#define	LCDC_LIER_ERR_RES_EN_SHIFT 2

#define	LCDC_LIER_GW_ERR_RES_EN_MASK 0x40u

#define	LCDC_LIER_GW_ERR_RES_EN_SHIFT 6

#define	LCDC_LISR_ERR_RES_MASK 0x4u

#define	LCDC_LISR_ERR_RES_SHIFT 2

#define	LCDC_LISR_GW_ERR_RES_MASK 0x40u

#define	LCDC_LISR_GW_ERR_RES_SHIFT 6

Typedefs
typedef struct ADC_MemMap *	ADC_MemMapPtr

typedef struct AIPS_MemMap *	AIPS_MemMapPtr

typedef struct AXBS_MemMap *	AXBS_MemMapPtr

typedef struct CAN_MemMap *	CAN_MemMapPtr

typedef struct CAU_MemMap *	CAU_MemMapPtr

typedef struct CMP_MemMap *	CMP_MemMapPtr

typedef struct CMT_MemMap *	CMT_MemMapPtr

typedef struct CRC_MemMap *	CRC_MemMapPtr

typedef struct CoreDebug_MemMap *	CoreDebug_MemMapPtr

typedef struct DAC_MemMap *	DAC_MemMapPtr

typedef struct DDR_MemMap *	DDR_MemMapPtr

typedef struct DMA_MemMap *	DMA_MemMapPtr

typedef struct DMAMUX_MemMap *	DMAMUX_MemMapPtr

typedef struct DWT_MemMap *	DWT_MemMapPtr

typedef struct ENET_MemMap *	ENET_MemMapPtr

typedef struct ETB_MemMap *	ETB_MemMapPtr

typedef struct ETF_MemMap *	ETF_MemMapPtr

typedef struct ETM_MemMap *	ETM_MemMapPtr

typedef struct EWM_MemMap *	EWM_MemMapPtr

typedef struct FB_MemMap *	FB_MemMapPtr

typedef struct FMC_MemMap *	FMC_MemMapPtr

typedef struct FPB_MemMap *	FPB_MemMapPtr

typedef struct FTFE_MemMap *	FTFE_MemMapPtr

typedef struct FTM_MemMap *	FTM_MemMapPtr

typedef struct GPIO_MemMap *	GPIO_MemMapPtr

typedef struct I2C_MemMap *	I2C_MemMapPtr

typedef struct I2S_MemMap *	I2S_MemMapPtr

typedef struct ITM_MemMap *	ITM_MemMapPtr

typedef struct LCDC_MemMap *	LCDC_MemMapPtr

typedef struct LLWU_MemMap *	LLWU_MemMapPtr

typedef struct LMEM_MemMap *	LMEM_MemMapPtr

typedef struct LPTMR_MemMap *	LPTMR_MemMapPtr

typedef struct MCG_MemMap *	MCG_MemMapPtr

typedef struct MCM_MemMap *	MCM_MemMapPtr

typedef struct MPU_MemMap *	MPU_MemMapPtr

typedef struct NFC_MemMap *	NFC_MemMapPtr

typedef struct NV_MemMap *	NV_MemMapPtr

typedef struct NVIC_MemMap *	NVIC_MemMapPtr

typedef struct OSC_MemMap *	OSC_MemMapPtr

typedef struct PDB_MemMap *	PDB_MemMapPtr

typedef struct PIT_MemMap *	PIT_MemMapPtr

typedef struct PMC_MemMap *	PMC_MemMapPtr

typedef struct PORT_MemMap *	PORT_MemMapPtr

typedef struct RCM_MemMap *	RCM_MemMapPtr

typedef struct RFSYS_MemMap *	RFSYS_MemMapPtr

typedef struct RFVBAT_MemMap *	RFVBAT_MemMapPtr

typedef struct RNG_MemMap *	RNG_MemMapPtr

typedef struct RTC_MemMap *	RTC_MemMapPtr

typedef struct SCB_MemMap *	SCB_MemMapPtr

typedef struct SDHC_MemMap *	SDHC_MemMapPtr

typedef struct SIM_MemMap *	SIM_MemMapPtr

typedef struct SMC_MemMap *	SMC_MemMapPtr

typedef struct SPI_MemMap *	SPI_MemMapPtr

typedef struct SysTick_MemMap *	SysTick_MemMapPtr

typedef struct TPIU_MemMap *	TPIU_MemMapPtr

typedef struct TSI_MemMap *	TSI_MemMapPtr

typedef struct UART_MemMap *	UART_MemMapPtr

typedef struct USB_MemMap *	USB_MemMapPtr

typedef struct USBDCD_MemMap *	USBDCD_MemMapPtr

typedef struct USBHS_MemMap *	USBHS_MemMapPtr

typedef struct VREF_MemMap *	VREF_MemMapPtr

typedef struct WDOG_MemMap *	WDOG_MemMapPtr

Enumerations
enum	IRQInterruptIndex { INT_Initial_Stack_Pointer = 0, INT_Initial_Program_Counter = 1, INT_NMI = 2, INT_Hard_Fault = 3, INT_Mem_Manage_Fault = 4, INT_Bus_Fault = 5, INT_Usage_Fault = 6, INT_Reserved7 = 7, INT_Reserved8 = 8, INT_Reserved9 = 9, INT_Reserved10 = 10, INT_SVCall = 11, INT_DebugMonitor = 12, INT_Reserved13 = 13, INT_PendableSrvReq = 14, INT_SysTick = 15, INT_DMA0_DMA16 = 16, INT_DMA1_DMA17 = 17, INT_DMA2_DMA18 = 18, INT_DMA3_DMA19 = 19, INT_DMA4_DMA20 = 20, INT_DMA5_DMA21 = 21, INT_DMA6_DMA22 = 22, INT_DMA7_DMA23 = 23, INT_DMA8_DMA24 = 24, INT_DMA9_DMA25 = 25, INT_DMA10_DMA26 = 26, INT_DMA11_DMA27 = 27, INT_DMA12_DMA28 = 28, INT_DMA13_DMA29 = 29, INT_DMA14_DMA30 = 30, INT_DMA15_DMA31 = 31, INT_DMA_Error = 32, INT_MCM = 33, INT_FTFE = 34, INT_Read_Collision = 35, INT_LVD_LVW = 36, INT_LLW = 37, INT_Watchdog = 38, INT_RNG = 39, INT_I2C0 = 40, INT_I2C1 = 41, INT_SPI0 = 42, INT_SPI1 = 43, INT_SPI2 = 44, INT_CAN0_ORed_Message_buffer = 45, INT_CAN0_Bus_Off = 46, INT_CAN0_Error = 47, INT_CAN0_Tx_Warning = 48, INT_CAN0_Rx_Warning = 49, INT_CAN0_Wake_Up = 50, INT_I2S0_Tx = 51, INT_I2S0_Rx = 52, INT_CAN1_ORed_Message_buffer = 53, INT_CAN1_Bus_Off = 54, INT_CAN1_Error = 55, INT_CAN1_Tx_Warning = 56, INT_CAN1_Rx_Warning = 57, INT_CAN1_Wake_Up = 58, INT_Reserved59 = 59, INT_UART0_LON = 60, INT_UART0_RX_TX = 61, INT_UART0_ERR = 62, INT_UART1_RX_TX = 63, INT_UART1_ERR = 64, INT_UART2_RX_TX = 65, INT_UART2_ERR = 66, INT_UART3_RX_TX = 67, INT_UART3_ERR = 68, INT_UART4_RX_TX = 69, INT_UART4_ERR = 70, INT_UART5_RX_TX = 71, INT_UART5_ERR = 72, INT_ADC0 = 73, INT_ADC1 = 74, INT_CMP0 = 75, INT_CMP1 = 76, INT_CMP2 = 77, INT_FTM0 = 78, INT_FTM1 = 79, INT_FTM2 = 80, INT_CMT = 81, INT_RTC = 82, INT_RTC_Seconds = 83, INT_PIT0 = 84, INT_PIT1 = 85, INT_PIT2 = 86, INT_PIT3 = 87, INT_PDB0 = 88, INT_USB0 = 89, INT_USBDCD = 90, INT_ENET_1588_Timer = 91, INT_ENET_Transmit = 92, INT_ENET_Receive = 93, INT_ENET_Error = 94, INT_Reserved95 = 95, INT_SDHC = 96, INT_DAC0 = 97, INT_DAC1 = 98, INT_TSI0 = 99, INT_MCG = 100, INT_LPTimer = 101, INT_Reserved102 = 102, INT_PORTA = 103, INT_PORTB = 104, INT_PORTC = 105, INT_PORTD = 106, INT_PORTE = 107, INT_PORTF = 108, INT_DDR = 109, INT_SWI = 110, INT_NFC = 111, INT_USBHS = 112, INT_LCD = 113, INT_CMP3 = 114, INT_Reserved115 = 115, INT_Reserved116 = 116, INT_FTM3 = 117, INT_ADC2 = 118, INT_ADC3 = 119, INT_I2S1_Tx = 120, INT_I2S1_Rx = 121 }

Detailed Description

Peripheral memory map for MK70F12.

Version: 1.12

Date: 2013-10-29 This header file implements peripheral memory map for MK70F12 processor.

Macro Definition Documentation

#define BITBAND_REG16	(	Reg,
		Bit
	)	(((uint16_t volatile)(BITBAND_REGADDR(Reg,Bit))))

Macro to access a single bit of a peripheral register (bit band region 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can be used for peripherals with 16bit access allowed.

Parameters

Reg	Register to access.
Bit	Bit number to access.

Returns: Value of the targeted bit in the bit band region.

#define BITBAND_REG32	(	Reg,
		Bit
	)	(((uint32_t volatile)(BITBAND_REGADDR(Reg,Bit))))

Macro to access a single bit of a peripheral register (bit band region 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can be used for peripherals with 32bit access allowed.

Parameters

Reg	Register to access.
Bit	Bit number to access.

Returns: Value of the targeted bit in the bit band region.

#define BITBAND_REG8	(	Reg,
		Bit
	)	(((uint8_t volatile)(BITBAND_REGADDR(Reg,Bit))))

Macro to access a single bit of a peripheral register (bit band region 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can be used for peripherals with 8bit access allowed.

Parameters

Reg	Register to access.
Bit	Bit number to access.

Returns: Value of the targeted bit in the bit band region.

#define BITBAND_REGADDR	(	Reg,
		Bit
	)	(0x42000000u + (32u((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u((uint32_t)(Bit))))

Macro to calculate address of an aliased word in the peripheral bitband area for a peripheral register and bit (bit band region 0x40000000 to 0x400FFFFF).

Parameters

Reg	Register to access.
Bit	Bit number to access.

Returns: Address of the aliased word in the peripheral bitband area.

#define MCU_MEM_MAP_VERSION 0x0100u

Memory map major version (memory maps with equal major version number are compatible)

#define MCU_MEM_MAP_VERSION_MINOR 0x000Cu

Memory map minor version

Data Structures

Macros

Typedefs

Enumerations

Detailed Description

Macro Definition Documentation